JPH0251424U - - Google Patents
Info
- Publication number
- JPH0251424U JPH0251424U JP13062188U JP13062188U JPH0251424U JP H0251424 U JPH0251424 U JP H0251424U JP 13062188 U JP13062188 U JP 13062188U JP 13062188 U JP13062188 U JP 13062188U JP H0251424 U JPH0251424 U JP H0251424U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- output
- circuit
- pair
- elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Description
第１図および第２図は本考案に関し、第１図は
本考案によるＭＯＳ出力回路の実施例回路図、第
２図はその動作を説明するための主な信号の波形
図である。第３図以降は従来技術に関し、第３図
は従来のＭＯＳ出力回路の回路図、第４図はその
主な信号の波形図である。図において、
１，２：出力トランジスタ、３，４：インバー
タ、１１，１２：出力トランジスタ、２０：電圧
分割回路、２１，２２：電圧分割要素、３１，３
２：スイツチ要素、４０：電圧分割回路、４１，
４２：電圧分割要素、５１，５２：スイツチ要素
、６０：インバータ、６１：ノアゲート、６２：
ナンドゲート、Ｃ：負荷としてのキヤパシタンス
、Ｇ１，Ｇ２：ゲート制御電圧、ｇ１，ｇ２：制
御電圧、ｉｓ：貫通電流、Ｌ：負荷回路内のイン
ダクタンス、Ｓｉ：入力信号、Ｓｏ：出力信号、
ｔ１〜ｔ４：時刻、Ｖｄ，Ｖｓ：電源電圧ないし
電源電位点、である。
1 and 2 relate to the present invention; FIG. 1 is a circuit diagram of an embodiment of a MOS output circuit according to the present invention, and FIG. 2 is a waveform diagram of main signals for explaining its operation. 3 and subsequent figures relate to the prior art. FIG. 3 is a circuit diagram of a conventional MOS output circuit, and FIG. 4 is a waveform diagram of its main signals. In the figure, 1, 2: output transistor, 3, 4: inverter, 11, 12: output transistor, 20: voltage divider circuit, 21, 22: voltage divider element, 31, 3
2: switch element, 40: voltage divider circuit, 41,
42: Voltage dividing element, 51, 52: Switch element, 60: Inverter, 61: NOR gate, 62:
NAND gate, C: capacitance as load, G1, G2: gate control voltage, g1, g2: control voltage, is: through current, L: inductance in load circuit, Si: input signal, So: output signal,
t1 to t4: time, Vd, Vs: power supply voltage or power supply potential point.
Claims (1)
用いられ入力信号に応じて出力信号の論理状態が
切り換えられる出力回路であつて、 (a) １対の電源電位点間に直列接続された入力
信号に応じてオンオフ動作して相互接続点から出
力信号が導出される１対の出力トランジスタと、 (b) 出力トランジスタごとに設けられ１対の電
圧分割要素により電圧を分割してゲート制御電圧
として出力トランジスタに与える電圧分割回路と
、 (c) 電圧分割回路にその各電圧分割要素を短絡
可能に接続された１対のスイツチ要素と、 を備えてなり、 (d) 入力信号により出力トランジスタのオフが
指定された場合は対応する１対のスイツチ要素の
一方を動作させて電圧分割回路にオフ指令電圧を
発生させ、 (e) 入力信号により出力トランジスタのオンが
指定された場合は対応する１対のスイツチ要素の
他方を出力信号が出力トランジスタのオフに対応
する状態にあることを条件に動作させて電圧分割
回路にオン指令電圧を発生させ、 (f) 電圧分割回路に接続された両スイツチ要素
がいずれも非動作のときその発生ゲート制御電圧
が対応する出力トランジスタのオン動作限界電圧
値とそれへのオン指令電圧値の中間になるように
電圧分割回路の電圧分割要素を設定した ことを特徴とするＭＯＳ出力回路。[Claims for Utility Model Registration] An output circuit in which a MOS transistor is used as an output transistor and the logic state of an output signal is switched according to an input signal, which circuit (a) is connected in series between a pair of power supply potential points; A pair of output transistors that turn on and off in response to an input signal to derive an output signal from an interconnection point; (b) A gate control voltage that divides the voltage by a pair of voltage dividing elements provided for each output transistor. (c) a pair of switch elements connected to the voltage divider circuit so that each of the voltage divider elements can be short-circuited; When OFF is specified, one of the corresponding pair of switch elements is operated to generate an OFF command voltage in the voltage dividing circuit; (e) When the output transistor is specified to be ON by the input signal, the corresponding 1 switch element is operated. The other of the pair of switch elements is operated on the condition that the output signal is in a state corresponding to the OFF state of the output transistor to generate an ON command voltage to the voltage divider circuit, and (f) both switches connected to the voltage divider circuit are operated. The voltage dividing elements of the voltage dividing circuit are set so that when none of the elements is in operation, the generated gate control voltage is between the on-operation limit voltage value of the corresponding output transistor and the on-command voltage value for it. Features MOS output circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13062188U JPH0251424U (en) | 1988-10-05 | 1988-10-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13062188U JPH0251424U (en) | 1988-10-05 | 1988-10-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0251424U true JPH0251424U (en) | 1990-04-11 |
Family
ID=31385956
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13062188U Pending JPH0251424U (en) | 1988-10-05 | 1988-10-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0251424U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02260918A (en) * | 1989-03-31 | 1990-10-23 | Oki Electric Ind Co Ltd | Data output circuit |
-
1988
- 1988-10-05 JP JP13062188U patent/JPH0251424U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02260918A (en) * | 1989-03-31 | 1990-10-23 | Oki Electric Ind Co Ltd | Data output circuit |
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