JPH0249224U - - Google Patents

Info

Publication number
JPH0249224U
JPH0249224U JP12738388U JP12738388U JPH0249224U JP H0249224 U JPH0249224 U JP H0249224U JP 12738388 U JP12738388 U JP 12738388U JP 12738388 U JP12738388 U JP 12738388U JP H0249224 U JPH0249224 U JP H0249224U
Authority
JP
Japan
Prior art keywords
clock oscillator
control signal
gate control
clock
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12738388U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12738388U priority Critical patent/JPH0249224U/ja
Publication of JPH0249224U publication Critical patent/JPH0249224U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例の回路図、第2図は
第1図の回路の各部の信号波形図、第3図は従来
例の回路図、第4図は従来例の回路の信号波形図
である。 10…クロツク発振子、11…ゲート回路(A
ND回路)、12…ゲート制御信号発生回路、1
3…コントロール端子、14…出力端子。
Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a signal waveform diagram of each part of the circuit of Fig. 1, Fig. 3 is a circuit diagram of a conventional example, and Fig. 4 is a signal of the conventional circuit. FIG. 10... Clock oscillator, 11... Gate circuit (A
ND circuit), 12...gate control signal generation circuit, 1
3...Control terminal, 14...Output terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] クロツク発振子と、ゲート制御信号により前記
クロツク発振子の出力を阻止または通過させるゲ
ート回路と、外部からのオンオフ状態コントロー
ル信号によつて前記クロツク発振子に同期したゲ
ート制御信号を発生するゲート制御信号発生回路
とからなり、外部からの信号によりクロツク発振
子に同期したクロツク出力のオンオフが可能なク
ロツク発振器。
a clock oscillator, a gate circuit that blocks or passes the output of the clock oscillator according to a gate control signal, and a gate control signal that generates a gate control signal synchronized with the clock oscillator according to an external on/off state control signal. A clock oscillator that consists of a generator circuit and can turn on and off the clock output in synchronization with the clock oscillator using an external signal.
JP12738388U 1988-09-30 1988-09-30 Pending JPH0249224U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12738388U JPH0249224U (en) 1988-09-30 1988-09-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12738388U JPH0249224U (en) 1988-09-30 1988-09-30

Publications (1)

Publication Number Publication Date
JPH0249224U true JPH0249224U (en) 1990-04-05

Family

ID=31379769

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12738388U Pending JPH0249224U (en) 1988-09-30 1988-09-30

Country Status (1)

Country Link
JP (1) JPH0249224U (en)

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