JPH0235500B2 - - Google Patents

Info

Publication number
JPH0235500B2
JPH0235500B2 JP55164846A JP16484680A JPH0235500B2 JP H0235500 B2 JPH0235500 B2 JP H0235500B2 JP 55164846 A JP55164846 A JP 55164846A JP 16484680 A JP16484680 A JP 16484680A JP H0235500 B2 JPH0235500 B2 JP H0235500B2
Authority
JP
Japan
Prior art keywords
data
transmission
processing device
transmitting
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP55164846A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5789358A (en
Inventor
Zenichi Yashiro
Mineo Nishiwaki
Shuhei Arima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP55164846A priority Critical patent/JPS5789358A/ja
Publication of JPS5789358A publication Critical patent/JPS5789358A/ja
Publication of JPH0235500B2 publication Critical patent/JPH0235500B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Computer And Data Communications (AREA)
JP55164846A 1980-11-22 1980-11-22 Line control system Granted JPS5789358A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55164846A JPS5789358A (en) 1980-11-22 1980-11-22 Line control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55164846A JPS5789358A (en) 1980-11-22 1980-11-22 Line control system

Publications (2)

Publication Number Publication Date
JPS5789358A JPS5789358A (en) 1982-06-03
JPH0235500B2 true JPH0235500B2 (fr) 1990-08-10

Family

ID=15801026

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55164846A Granted JPS5789358A (en) 1980-11-22 1980-11-22 Line control system

Country Status (1)

Country Link
JP (1) JPS5789358A (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6014555A (ja) * 1983-07-06 1985-01-25 Fuji Facom Corp 直列デ−タ受信装置
US5247616A (en) * 1989-10-23 1993-09-21 International Business Machines Corporation Computer system having different communications facilities and data transfer processes between different computers

Also Published As

Publication number Publication date
JPS5789358A (en) 1982-06-03

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