JPH0234014A - Composite semiconductor device - Google Patents

Composite semiconductor device

Info

Publication number
JPH0234014A
JPH0234014A JP18499288A JP18499288A JPH0234014A JP H0234014 A JPH0234014 A JP H0234014A JP 18499288 A JP18499288 A JP 18499288A JP 18499288 A JP18499288 A JP 18499288A JP H0234014 A JPH0234014 A JP H0234014A
Authority
JP
Japan
Prior art keywords
input impedance
nearly
transistor
inductor
whose
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18499288A
Other languages
Japanese (ja)
Inventor
Junichi Takahashi
順一 高橋
Hitoshi Furukawa
仁志 古川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP18499288A priority Critical patent/JPH0234014A/en
Publication of JPH0234014A publication Critical patent/JPH0234014A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Microwave Amplifiers (AREA)

Abstract

PURPOSE:To obtain a high stability figure at the time of matching and to attain a remarkably stable operation by applying the internal matching to a high input impedance transistor(TR) so as to form an optimum input impedance. CONSTITUTION:At first a MOS capacitor 108 whose capacitance is nearly 5pF is connected in parallel with a base of a high input impedance TR whose impedance is nearly (200-j200)OMEGA and a distributed constant inductor 109 whose length is 1mm and whose width is 20mum is connected in series with the TR. Moreover, a lumped constant inductor 110 nearly 10nH in its inductance is connected in series in response to the required frequency band and finally the inductor is connected to an external base terminal through a bonding gold wire 111. Through the constitution above, a high frequency small signal TR with the optimum input impedance of nearly 50OMEGA is configurated in such a way and a signal at a 800MHz band is amplified stably by one stage only of the said TR with a gain as high as 15dB at a low power consumption of 1V.1mA.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は高入力インピーダンストランジスタに内部整合
を施して最適入力インピーダンスにした複合半導体装置
に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a composite semiconductor device in which a high input impedance transistor is internally matched to have an optimum input impedance.

従来の技術 近年、高周波用以下種々の小信号トランジスタは、低駆
動電圧、低消費電流において十分な特性が得られる等の
高性能化が進み、応用も多角的になってきている。BACKGROUND OF THE INVENTION In recent years, various types of small signal transistors for high frequency use have been improved in performance, with sufficient characteristics being obtained at low drive voltages and low current consumption, and their applications have become more diverse.

以下に従来のＮＰＮ高周波小信号トランジスタについて
説明する。第４図、第５図は従来のＮＰＮ高周波小信号
トランジスタの平面図、要部断面図を示すものである。A conventional NPN high frequency small signal transistor will be explained below. FIGS. 4 and 5 show a plan view and a sectional view of essential parts of a conventional NPN high frequency small signal transistor.

第４図、第５図において、１はシリコン基板、２はＮ型
シリコンエピタキシャル層、３はＰ型ベース領域、４は
Ｎ型エミッタ領域、５はシリコン酸化膜、６はアルミ電
極、７はパシベーション保護膜である。4 and 5, 1 is a silicon substrate, 2 is an N-type silicon epitaxial layer, 3 is a P-type base region, 4 is an N-type emitter region, 5 is a silicon oxide film, 6 is an aluminum electrode, and 7 is a passivation layer. It is a protective film.

次に、この高周波小信号トランジスタについてその動作
を説明する。Next, the operation of this high frequency small signal transistor will be explained.

まず、第６図の回路例に示すように低駆動電圧、低消費
電流で動作させるトランジスタは高周波増幅用トランジ
スタ１１、局部発振用トランジスタ１２、周波数混合用
トランジスタ１３の回路構成により微弱電波を受信し、
増幅・周波数変換までおこなう受信機の中核部品である
。First, as shown in the circuit example of FIG. 6, a transistor that operates with low drive voltage and low current consumption receives weak radio waves with a circuit configuration of high frequency amplification transistor 11, local oscillation transistor 12, and frequency mixing transistor 13. ,
It is a core component of a receiver that performs amplification and frequency conversion.

発明が解決しようとする課題 しかしながら上記の従来の構成では、低駆動電圧、低消
費電流動作の本トランジスタは入力インピーダンスがも
ともと高いので、インピーダンス変換してインピーダン
スを外部回路により低下させており、この事により安定
指数が低下し、定数のばらつきにより寄生発振等の問題
が発生する欠点を有していた。Problems to be Solved by the Invention However, in the conventional configuration described above, the input impedance of this transistor, which operates at low driving voltage and low current consumption, is originally high, so the impedance is lowered by an external circuit by converting the impedance. This has disadvantages in that the stability index decreases and problems such as parasitic oscillation occur due to variations in constants.

本発明は上記従来の問題点を解決するもので、高入力イ
ンピーダンストランジスタに内部整合を施して最適入力
インピーダンスとし、外部回路でのインピーダンス変換
との組合せで安定指数の低下を防ぎ、安定な動作を提供
するものである。The present invention solves the above-mentioned conventional problems by internally matching high input impedance transistors to achieve optimal input impedance, and in combination with impedance conversion in an external circuit, prevents a decrease in stability index and ensures stable operation. This is what we provide.

課題を解決するための手段 この目的を達成するために、本発明のＮＰＮ高周波小信
号トランジスタは内部整合用ＭＯ３牛ヤバシタ１分布定
数線路、集中定数インダクタ、配線用ボンディング金線
等を有しており、高入力インピーダンスから最適入力イ
ンピーダンスにインピーダンス変換できるように構成さ
れている。Means for Solving the Problems In order to achieve this object, the NPN high frequency small signal transistor of the present invention has an internal matching MO3 conductor 1 distributed constant line, a lumped constant inductor, a bonding gold wire for wiring, etc. , is configured to be able to perform impedance conversion from a high input impedance to an optimal input impedance.

作用 この構成によって回路上不安定になる可能性のあった高
入力インピーダンス高周波小信号トランジスタを最適入
力インピーダンスにすることができ、その結果外部回路
との整合をとる時の安定指数が高くとれ、非常に安定な
動作を実現することができる。Effect: With this configuration, the high input impedance, high frequency, small signal transistor, which had the potential to become unstable in the circuit, can be made into the optimum input impedance, and as a result, the stability index when matching with the external circuit can be high, making it extremely It is possible to achieve stable operation.

実施例 以下に本発明の一実施例について、図面を参照しながら
説明する。EXAMPLE An example of the present invention will be described below with reference to the drawings.

第１図、第２図は本発明の実施例における高周波小信号
トランジスタの平面図、要部断面図を示すものである。FIGS. 1 and 2 show a plan view and a sectional view of a main part of a high frequency small signal transistor according to an embodiment of the present invention.

第１図、第２図において、１０１はシリコン基板、１０
２はＮ型シリコンエピタキシャル層、１０３はＰ型ベー
ス領域、１０４はＮ型エミッタ領域、１０５はシリコン
酸化膜、１０６はアルミニウム膜による電極、１０７は
パシベーション保護膜、１０８はＭＯＳキャパシタ、１
０９は分布定数インダクタ、１１０は集中定数インダク
タ、１１１はボンディング用金線である。第３図はその
等価回路図である。In FIGS. 1 and 2, 101 is a silicon substrate;
2 is an N-type silicon epitaxial layer, 103 is a P-type base region, 104 is an N-type emitter region, 105 is a silicon oxide film, 106 is an electrode made of an aluminum film, 107 is a passivation protective film, 108 is a MOS capacitor, 1
09 is a distributed constant inductor, 110 is a lumped constant inductor, and 111 is a bonding gold wire. FIG. 3 is its equivalent circuit diagram.

以上のように構成された高周波小信号トランジスタにつ
いて、以下その動作を説明する。The operation of the high frequency small signal transistor configured as described above will be described below.

まず、（２００−ｊ　２００）Ω程度の高入力インピー
ダンストランジスタのベースに５ｐＦのＭＯＳキャパシ
タ１０８を並列に接続して次に長さ１鴫９幅２０μｍの
分布定数インダクタ１１０を直列に接続し、次に必要周
波数帯に応じて約１ＯｎＨの集中定数インダクタ１１０
を直列に接続し、最後にインダクタの働きを持つボンデ
ィング用金線により外部ベース端子に接続する。以上に
よりほぼ５０Ωの最適入力インピーダンスの高周波小信
号トランジスタが構成され、８００ＭＨｚ帯で一段で１
５デシベルの高利得がＩＶｌｍＡという低消費電力下で
安定に増幅することができた。First, a 5 pF MOS capacitor 108 is connected in parallel to the base of a high input impedance transistor of about (200-j 200) Ω, and then a distributed constant inductor 110 with a length of 1 x 9 and a width of 20 μm is connected in series. Approximately 1 OnH lumped constant inductor 110 depending on the required frequency band
are connected in series, and finally connected to the external base terminal using a bonding gold wire that acts as an inductor. As described above, a high frequency small signal transistor with an optimum input impedance of approximately 50Ω is constructed, and one stage in the 800MHz band
A high gain of 5 dB could be stably amplified with low power consumption of IVlmA.

以上のように本実施例によれば、高入力インピーダンス
を持つ高周波小信号トランジスタに、同一チップ内部に
インダクタ、キャパシタを設けることにより、インピー
ダンス変換をおこない最適入力インピーダンスにして、
トランジスタ自身や外部回路のばらつきによる、寄生発
振等の不安定動作を防止することができる。As described above, according to this embodiment, by providing an inductor and a capacitor in the same chip for a high frequency small signal transistor with high input impedance, impedance conversion is performed and the optimum input impedance is achieved.
It is possible to prevent unstable operation such as parasitic oscillation due to variations in the transistor itself or external circuits.

なお、本実施例においては、ＮＰＮ高周波小信号トラン
ジスタを例としたが、ＰＮＰ高周波小信号トランジスタ
、ＮチャンネルＭＯＳトランジスタ、ＰチャンネルＭＯ
Ｓトランジスタにおいてもよい。In this embodiment, an NPN high frequency small signal transistor is used as an example, but a PNP high frequency small signal transistor, an N channel MOS transistor, a P channel MO
It may also be an S transistor.

発明の効果 以上のように、本発明によれば、インダクタとキャパシ
タを同一チップ内部に設は整合回路を構成することによ
り、高入力インピーダンスを最適入力インピーダンスに
変換させ、寄生発振等の不安定動作を防止することがで
きる。Effects of the Invention As described above, according to the present invention, by configuring a matching circuit by arranging an inductor and a capacitor inside the same chip, a high input impedance is converted to an optimal input impedance, thereby preventing unstable operation such as parasitic oscillation. can be prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図、第２図は本発明の実施例における高周波小信号
トランジスタの平面図、要部断面図、第３図はその等価
回路回路図、第４図、第５図は従来の高周波小信号トラ
ンジスタの平面図、要部断面図、第６図は回路構成例を
示す回路図である。 １、．１０１・・・・・・シリコン基板、２，１０２・
・・・・・Ｎ型シリコンエピタキシャル層、３．１０３
・・・・・・Ｐ型ベース領域、４，１０４・・・・・・
Ｎ型エミッタ領域、５．１０５・・・・・・シリコン酸
化膜、６．１０６・・・・・・アルミニウム電極、７，
１０７・・・・・・パシベーション保護膜、１１・・・
・・・高周波増幅用トランジス夕、１２・・・・・・局
部発振用トランジスタ、１３・旧・・周波数混合用トラ
ンジスタ、１０８・・・・・・ＭＯＳキャパシタ、１０
９・・・・・・分布定数インダクタ、１１０・・・・・
・集中定数インダクタ、１１１・・・・・・ボンディン
グ用金線。 代理人の氏名　弁理士　粟野重孝　はが１名第 図 ｔｏ３−−−Ｐ型Ａ′−ス（銭賊1 and 2 are a plan view and a sectional view of the main parts of a high frequency small signal transistor according to an embodiment of the present invention, FIG. 3 is an equivalent circuit diagram thereof, and FIGS. 4 and 5 are a conventional high frequency small signal transistor. FIG. 6 is a circuit diagram showing an example of a circuit configuration. 1. 101...Silicon substrate, 2,102.
...N-type silicon epitaxial layer, 3.103
...P-type base region, 4,104...
N-type emitter region, 5.105...Silicon oxide film, 6.106...Aluminum electrode, 7,
107...Passivation protective film, 11...
...Transistor for high frequency amplification, 12...Transistor for local oscillation, 13. Old...Transistor for frequency mixing, 108...MOS capacitor, 10
9...Distributed constant inductor, 110...
- Lumped constant inductor, 111...Gold wire for bonding. Name of agent: Patent attorney Shigetaka Awano (1 person)

Claims (1)

【特許請求の範囲】[Claims] 高入力インピーダンスを有するトランジスタにインダク
タとキャパシタからなる内部整合回路を設けて最適入力
インピーダンスに変換した複合半導体装置。A composite semiconductor device in which a transistor with high input impedance is converted to an optimal input impedance by providing an internal matching circuit consisting of an inductor and a capacitor.
JP18499288A 1988-07-25 1988-07-25 Composite semiconductor device Pending JPH0234014A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18499288A JPH0234014A (en) 1988-07-25 1988-07-25 Composite semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18499288A JPH0234014A (en) 1988-07-25 1988-07-25 Composite semiconductor device

Publications (1)

Publication Number Publication Date
JPH0234014A true JPH0234014A (en) 1990-02-05

Family

ID=16162896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18499288A Pending JPH0234014A (en) 1988-07-25 1988-07-25 Composite semiconductor device

Country Status (1)

Country Link
JP (1) JPH0234014A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011528168A (en) * 2008-07-04 2011-11-10 オスラム アクチエンゲゼルシャフト Circuit apparatus and method for operating at least a first LED and a second LED
JP2013017075A (en) * 2011-07-05 2013-01-24 Mitsubishi Electric Corp High frequency power amplifier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011528168A (en) * 2008-07-04 2011-11-10 オスラム アクチエンゲゼルシャフト Circuit apparatus and method for operating at least a first LED and a second LED
JP2013017075A (en) * 2011-07-05 2013-01-24 Mitsubishi Electric Corp High frequency power amplifier

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