JPH0228966A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0228966A JPH0228966A JP17811588A JP17811588A JPH0228966A JP H0228966 A JPH0228966 A JP H0228966A JP 17811588 A JP17811588 A JP 17811588A JP 17811588 A JP17811588 A JP 17811588A JP H0228966 A JPH0228966 A JP H0228966A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- inner lead
- lead
- lead frame
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 239000000853 adhesive Substances 0.000 claims abstract description 9
- 230000001070 adhesive effect Effects 0.000 claims abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 239000007787 solid Substances 0.000 abstract description 2
- 239000012811 non-conductive material Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005452 bending Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野コ
本発明は、半導体装置に係り、さらに詳しくは、リード
フレームへの半導体チップの取付方式の改良に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly, to an improvement in a method for attaching a semiconductor chip to a lead frame.
［従来の技術］
半導体装置は、周知のように集積回路等が形成された半
導体チップをリードフレームのダイパッドに接着剤等に
より取付け、半導体チップの各ボンディングパッドとこ
れに対応したリードフレームのインナリードとをワイヤ
で接続し、ついで半導体チップとその周辺のインナリー
ドとをプラスチックあるいはセラミックにより一体的に
成型し、封止する。そして成型されたパッケージの外側
において各インナリードをリードフレームから切り離し
、必要に応じて各インナリードを適宜折曲げて半導体装
置を製造している。[Prior Art] As is well known, in a semiconductor device, a semiconductor chip on which an integrated circuit or the like is formed is attached to a die pad of a lead frame using an adhesive or the like, and each bonding pad of the semiconductor chip is connected to a corresponding inner lead of the lead frame. Then, the semiconductor chip and the inner leads around it are integrally molded with plastic or ceramic and sealed. Then, each inner lead is separated from the lead frame on the outside of the molded package, and each inner lead is appropriately bent as necessary to manufacture a semiconductor device.
第４図はリードフレームに半導体チップを取付ける従来
例を模式的に示した平面図、第５図はその断面図である
。両図において、１はリードフレームで、中央部には支
持腕３で支持されたダイパッド２が設けられている。４
はリードフレーム１から中心部に向って突設された多数
のインナリードで、その先端部はダイパッド２の周辺に
ダイパッド２と所定の間隔を隔てて対向配置されている
。FIG. 4 is a plan view schematically showing a conventional example of mounting a semiconductor chip on a lead frame, and FIG. 5 is a sectional view thereof. In both figures, 1 is a lead frame, and a die pad 2 supported by support arms 3 is provided in the center. 4
are a large number of inner leads protruding from the lead frame 1 toward the center, and their tips are disposed around the die pad 2 to face the die pad 2 at a predetermined distance.
５はダイパッド２上に接着剤等により取付けられた半導
体チップで、半導体チップ５に設けたボンディングパッ
ド５ａと、これに対応する各インナリ−ド４とは、第５
図に示すようにそれぞれワイヤ６により接続されている
。5 is a semiconductor chip attached to the die pad 2 with an adhesive or the like, and the bonding pad 5a provided on the semiconductor chip 5 and each inner lead 4 corresponding thereto are
As shown in the figure, they are connected by wires 6, respectively.
上記のようにして多数のインナリード４に接続された半
導体チップ５は、インナリード４の一部を残して、例え
ば第４図に１点鎖線Ｐで示した範囲をダイパッド２と共
に、エポキシ樹脂の如きプラスチックによりパッケージ
７され、第６図に示すように封止される。ついで、１点
鎖線Ｃの位置で各インナリード４を切断し、パッケージ
７から突出したインナリード４を折曲げて端子とし、半
導体装置の組立が完了する。The semiconductor chip 5 connected to a large number of inner leads 4 as described above is attached to the die pad 2 along with the die pad 2, leaving a part of the inner leads 4, for example, in the area indicated by the dashed line P in FIG. The package 7 is made of a plastic material such as the like, and sealed as shown in FIG. Next, each inner lead 4 is cut at the position indicated by the dashed-dotted line C, and the inner lead 4 protruding from the package 7 is bent to form a terminal, completing the assembly of the semiconductor device.
［発明が解決しようとする課題］
上記のような従来の半導体装置においては、半導体チッ
プ５の大きさ、ボンディングパッド５ａの配置等に応じ
て、その都度これに適合する形状のリードフレーム１を
設計し、製作している。特に、最近では客先の仕様に応
じて半導体装置を製作する分野が拡大しており、半導体
チップ５の大きさやボンディングパッド５ａの配置等も
益々多様化している。[Problems to be Solved by the Invention] In the conventional semiconductor device as described above, the lead frame 1 is designed in a shape that matches the size of the semiconductor chip 5, the arrangement of the bonding pads 5a, etc. each time. and is being produced. In particular, recently, the field of manufacturing semiconductor devices according to customer specifications has expanded, and the size of semiconductor chips 5, the arrangement of bonding pads 5a, etc. are becoming increasingly diverse.
このため、半導体チップ５の種類の増加に伴ってリード
フレーム１の種類も増加の一途をたどっており、これを
その都度設計、製作しなければならないので、コスト高
になるばかりでなく、納期の長期化も避けられないとい
う問題があった。For this reason, as the types of semiconductor chips 5 increase, the types of lead frames 1 also continue to increase, and as these have to be designed and manufactured each time, not only does it increase costs, but also shortens delivery times. The problem was that it was inevitable that the situation would be prolonged.
本発明は、上記のような課題を解決すべくなされたもの
で、１種類のリードフレームで多種類の半導体チップに
対応することのできる半導体装置を得ることを目的とし
たものである。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device that can be used with many types of semiconductor chips using one type of lead frame.
［課題を解決するための手段］
本発明に係る半導体装置は、従来のダイパッドを省略し
、半導体チップをリードフレームのインナリードに直接
取付けるようにしたものである。[Means for Solving the Problems] A semiconductor device according to the present invention omits a conventional die pad, and a semiconductor chip is directly attached to an inner lead of a lead frame.
［作 用］
非導電性の接着剤により半導体チップをリードフレーム
のインナリードに直接接着し、半導体チップのボンディ
ングパッドとこれに対応したインナリードとをワイヤで
接続する。[Function] The semiconductor chip is directly bonded to the inner lead of the lead frame using a non-conductive adhesive, and the bonding pad of the semiconductor chip and the corresponding inner lead are connected with a wire.
［発明の実施例］ 第１図は本発明実施例を模式的に示した平面図である。[Embodiments of the invention] FIG. 1 is a plan view schematically showing an embodiment of the present invention.
図において、１はリードフレームで、多数のインナリー
ド４が中心部に向って突設されており、その先端部は小
形の半導体チップ５の平面積よりさらに小さい空間部８
を隔てて対向配置されている。５は半導体チップで、本
発明においてはダイパッドを省略し、第２図に示すよう
に、半導体チップ５を非導電性の接着剤９により、各イ
ンナリード４に直接接着したものである。In the figure, reference numeral 1 denotes a lead frame, in which a large number of inner leads 4 are provided protruding toward the center, and their tips end in a space 8 that is even smaller than the planar area of a small semiconductor chip 5.
are placed facing each other across. Reference numeral 5 denotes a semiconductor chip, in which the die pad is omitted in the present invention, and the semiconductor chip 5 is directly bonded to each inner lead 4 with a non-conductive adhesive 9, as shown in FIG.
この場合、インナリード４と半導体チップ５が直接接触
して短絡事故等が発生するのを防止するため、両者の間
に若干の間隙ｇを設けることが必要であり、このために
は、例えば第２図に示すように非導電材からなる固体（
例えば粒状のシリカ）１０を接着剤に混入し、間隙ｇを
保持するようにしてもよい。In this case, in order to prevent the inner lead 4 and the semiconductor chip 5 from directly contacting each other and causing a short circuit accident, it is necessary to provide a slight gap g between them. As shown in Figure 2, a solid (
For example, granular silica (10) may be mixed into the adhesive to maintain the gap g.
このようにして、各インナリード４に直接取付けられた
半導体チップ５は、第３図に示すように半導体チップ５
の各ボンディングパッド５ａと各インナリード４とをそ
れぞれワイヤ６で接続し、インナリード４の一部と半導
体チップ５とを、例えば第１図の１点鎖Ｉ！Ｐの範囲で
プラスチックパッケージ等により封止し、パッケージか
ら突出したインナリード４を折曲げて端子とすることに
より、半導体装置が得られる。In this way, the semiconductor chips 5 directly attached to each inner lead 4 are connected to
Each bonding pad 5a of FIG. A semiconductor device is obtained by sealing with a plastic package or the like within the range of P and bending the inner leads 4 protruding from the package to form terminals.
［発明の効果］
以上の説明から明らかなように、本発明は従来半導体チ
ップを取付けていたダイパッドを省略し、半導体チップ
をリードフレームのインナリードに直接取付けるように
したので、半導体チップの大きさに関係なく各種の半導
体チップを１種類のリードフレームに取付けることがで
き、また、半導体チップのボンディングパッドの配置位
置に関係なく、インナリードに接続することができる。[Effects of the Invention] As is clear from the above description, the present invention omits the die pad on which the semiconductor chip was conventionally attached and directly attaches the semiconductor chip to the inner lead of the lead frame, which reduces the size of the semiconductor chip. Various types of semiconductor chips can be attached to one type of lead frame regardless of the semiconductor chip, and it is possible to connect to the inner leads regardless of the arrangement position of the bonding pads of the semiconductor chip.
このため１種類のリードフレームで多種類の半導体チッ
プに対応できるので、設計、製造の工数を大幅に低減す
ることができ、コストを低減できるばかりでなく納期を
短縮できる等、実施による効果大である。As a result, one type of lead frame can be used for many types of semiconductor chips, which greatly reduces design and manufacturing man-hours, which not only reduces costs but also shortens delivery times. be.
第１図は本発明実施例を模式的に示した平面図、第２図
はその要部の拡大図、第３図はインナリードと半導体チ
ップとの接続状態を示す側面図、第４図は従来のインナ
リードと半導体チップとの接続状態を模式的に示した平
面図、第５図はその側面図、第６図は一部を断面で示し
た従来の半導体装置の斜視図である。
１：リードフレーム、４：インナリード、５：半導体チ
ップ、５ａ：ボンディングパッド、６：ワイヤ、９：接
着剤。Fig. 1 is a plan view schematically showing an embodiment of the present invention, Fig. 2 is an enlarged view of the main parts thereof, Fig. 3 is a side view showing the connection state between the inner lead and the semiconductor chip, and Fig. 4 is FIG. 5 is a plan view schematically showing a connection state between a conventional inner lead and a semiconductor chip, FIG. 5 is a side view thereof, and FIG. 6 is a perspective view of the conventional semiconductor device partially shown in cross section. 1: Lead frame, 4: Inner lead, 5: Semiconductor chip, 5a: Bonding pad, 6: Wire, 9: Adhesive.
Claims (1)
インナリードとをワイヤで接続し、これらをプラスチッ
ク等で封止してなる半導体装置において、 前記半導体チップを非導電性の接着剤により前記インナ
リードに直接取付け、前記半導体チップのボンディング
パッドとインナリードとをワイヤで接続したことを特徴
とする半導体装置。[Scope of Claims] A semiconductor device in which a bonding pad of a semiconductor chip and an inner lead of a lead frame are connected with a wire and these are sealed with plastic or the like, wherein the semiconductor chip is bonded to the bonding pad of the lead frame with a non-conductive adhesive. A semiconductor device, characterized in that it is directly attached to an inner lead, and the bonding pad of the semiconductor chip and the inner lead are connected with a wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63178115A JP2629853B2 (en) | 1988-07-19 | 1988-07-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63178115A JP2629853B2 (en) | 1988-07-19 | 1988-07-19 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0228966A true JPH0228966A (en) | 1990-01-31 |
| JP2629853B2 JP2629853B2 (en) | 1997-07-16 |
Family
ID=16042921
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63178115A Expired - Lifetime JP2629853B2 (en) | 1988-07-19 | 1988-07-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2629853B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04241445A (en) * | 1991-01-16 | 1992-08-28 | Nec Corp | Semiconductor integrated circuit device |
| WO1997029514A1 (en) * | 1996-02-09 | 1997-08-14 | Mci Computer Gmbh | Semiconductor component |
| US5753977A (en) * | 1996-03-22 | 1998-05-19 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and lead frame therefor |
| KR100642541B1 (en) * | 2005-02-07 | 2006-11-10 | 윤정덕 | set up structure to a insulaion curtain of a corral |
| EP4152379A1 (en) * | 2021-09-21 | 2023-03-22 | Infineon Technologies Austria AG | Semiconductor package and lead frame with enhanced device isolation |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60111449A (en) * | 1983-11-22 | 1985-06-17 | Nec Corp | Semiconductor device |
| JPS6382950U (en) * | 1986-11-17 | 1988-05-31 |
-
1988
- 1988-07-19 JP JP63178115A patent/JP2629853B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60111449A (en) * | 1983-11-22 | 1985-06-17 | Nec Corp | Semiconductor device |
| JPS6382950U (en) * | 1986-11-17 | 1988-05-31 |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04241445A (en) * | 1991-01-16 | 1992-08-28 | Nec Corp | Semiconductor integrated circuit device |
| WO1997029514A1 (en) * | 1996-02-09 | 1997-08-14 | Mci Computer Gmbh | Semiconductor component |
| US5753977A (en) * | 1996-03-22 | 1998-05-19 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and lead frame therefor |
| DE19708002B4 (en) * | 1996-03-22 | 2004-09-16 | Mitsubishi Denki K.K. | Connection frame for semiconductor components |
| KR100642541B1 (en) * | 2005-02-07 | 2006-11-10 | 윤정덕 | set up structure to a insulaion curtain of a corral |
| EP4152379A1 (en) * | 2021-09-21 | 2023-03-22 | Infineon Technologies Austria AG | Semiconductor package and lead frame with enhanced device isolation |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2629853B2 (en) | 1997-07-16 |
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