JPH02273961A - Lead frame and hybrid integrated circuit using same - Google Patents
Lead frame and hybrid integrated circuit using sameInfo
- Publication number
- JPH02273961A JPH02273961A JP9581789A JP9581789A JPH02273961A JP H02273961 A JPH02273961 A JP H02273961A JP 9581789 A JP9581789 A JP 9581789A JP 9581789 A JP9581789 A JP 9581789A JP H02273961 A JPH02273961 A JP H02273961A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- lead
- terminals
- circuit chip
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 21
- 229910000881 Cu alloy Inorganic materials 0.000 abstract 1
- 239000011347 resin Substances 0.000 description 11
- 229920005989 resin Polymers 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 239000000758 substrate Substances 0.000 description 7
- 239000002184 metal Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 238000010304 firing Methods 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4918—Disposition being disposed on at least two different sides of the body, e.g. dual array
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
基板の両面に電極を設けた混成集積回路の電極接続構造
に関し、
回路チップの表裏両面の導体配線間をスルーホールを使
用しないで簡易に接続することを目的とし、
回路チップを搭載するリードフレームの相隣る２本の内
部リード端子が連結されてタイバーに接続した連結内端
子を、少なくとも１箇所に設けてリードフレームを構成
し、前記リードフレームのステージ上に両面配線回路チ
ップを搭載し、前記両面配線回路チップの表裏両面の導
体配線接続用端子と前記連結内端子の２本の内部リード
端子とを、それぞれボンディングワイヤで接続して前記
表裏両面の接続用端子間を短絡して混成集積回路を構成
する。[Detailed Description of the Invention] [Summary] Regarding the electrode connection structure of a hybrid integrated circuit in which electrodes are provided on both sides of a substrate, the object is to easily connect conductor wiring on both the front and back sides of a circuit chip without using through holes. A lead frame is constructed by providing at least one connection internal terminal in which two adjacent internal lead terminals of a lead frame on which a circuit chip is mounted are connected and connected to a tie bar, and A double-sided wiring circuit chip is mounted on the double-sided wiring circuit chip, and the conductor wiring connection terminals on both the front and back sides of the double-sided wiring circuit chip and the two internal lead terminals of the connection inner terminal are respectively connected with bonding wires to connect the front and back sides. A hybrid integrated circuit is constructed by short-circuiting the terminals.
本発明は両面配線回路チップを用いた混成集積回路の端
子接続構造の改良に関する。The present invention relates to an improvement in the terminal connection structure of a hybrid integrated circuit using a double-sided wiring circuit chip.
近年、各種集積回路装置の集積度が増し、大規模化する
傾向がますます強くなってきた。これに伴い基板の両面
に導体配線を行い、さらに各種小形部品を搭載する、い
わゆる、両面実装方式が多く使用されるようになった。In recent years, the degree of integration of various integrated circuit devices has increased, and there has been a growing trend toward larger scale. Along with this, the so-called double-sided mounting method, in which conductor wiring is provided on both sides of the board and various small components are mounted, has come to be widely used.
両面に配線された回路基板で重要な問題の一つは、表裏
両面に形成されている導体間を接続することであり、簡
易で、かつ、信頼性の高い両面の配線間の接続構造の開
発が求められていた。One of the important issues with circuit boards with wiring on both sides is connecting the conductors formed on both the front and back sides, and we need to develop a simple and reliable connection structure between the wiring on both sides. was required.
第５図は従来の接続構造の一例を示す概観図である。図
中、１゛はアルミナ製セラミック板などを基板とした回
路チップで、２０は基板表面上に形成されている導体配
線の接続用端子、１０は図には示してない裏面配線との
導通を取るためのスルーホールであり、必要に応じて接
続用端子２０に隣接して所要数だけ配設されている。３
′はリードフレームで、中央部分に前記回路チップ１゛
をダイボンディングで搭載するステージ６が設けられて
いる。FIG. 5 is an overview diagram showing an example of a conventional connection structure. In the figure, 1'' is a circuit chip with a substrate made of an alumina ceramic plate, etc., 20 is a terminal for connecting conductor wiring formed on the surface of the substrate, and 10 is a circuit chip for connecting with the wiring on the back side (not shown in the figure). A required number of through holes are provided adjacent to the connection terminals 20 as necessary. 3
' is a lead frame, and a stage 6 on which the circuit chip 1' is mounted by die bonding is provided in the center part.
４０は内部リード端子で、回路チップ１゛の接続用端子
２０とボンディングワイヤ７により接続される。５はリ
ードフレームを連結しておくためのタイバーで、モール
ド樹脂外装をしたあと切断・除去される。Reference numeral 40 denotes an internal lead terminal, which is connected to the connection terminal 20 of the circuit chip 1'' by a bonding wire 7. 5 is a tie bar for connecting the lead frames, which is cut and removed after being covered with molded resin.
第６図は従来のスルーホールによる両面配線基板の接続
構造図で、第５図の接続部分を拡大して理解しやすいよ
うに示したものである。FIG. 6 is a diagram of a conventional connection structure of a double-sided wiring board using through holes, and the connection portion shown in FIG. 5 is enlarged for easier understanding.
同図（イ）は平面図、同図（ロ）はＡ−Ａ”断面図であ
る。Figure (a) is a plan view, and figure (b) is a sectional view taken along line A-A''.
接続用端子２０は、たとえば、Ａｇ／Ｐｄ系厚膜導体配
線８の末端の端子部に、＾Ｕ厚膜により形成されたポン
ディングパッドである。The connection terminal 20 is, for example, a bonding pad formed of a ^U thick film at the end terminal portion of the Ag/Pd thick film conductor wiring 8.
スルーホール１０は、たとえば、厚さ０．６５ｍｍのア
ルミナ基板に１１００ａφ程度の孔を穿ち、その内面を
金属導体で覆って表裏両面の導体配線８につながってい
るので、これによって、表裏両面の導体配線８は電気的
に接続されるのである。なお、スルーホール１０上の配
線接続部は直径２００μｍφ程度の大きさに広げて形成
されている。The through hole 10 is, for example, a hole of about 1,100 a diameter made in an alumina substrate with a thickness of 0.65 mm, and its inner surface is covered with a metal conductor to connect to the conductor wiring 8 on both the front and back surfaces. The wiring 8 is electrically connected. Note that the wiring connection portion on the through hole 10 is formed to be expanded to a diameter of about 200 μmφ.
さらに、第５図と同様に両面配線されスルーホール１０
を設けた回路ちっプｌ゛をリードフレーム３′のステー
ジ６に搭載し、前記回路ちっプ１゜の接続用端子２０と
リードフレーム３゛の内部リード端子４０とをボンディ
ングワイヤ７で接続すると、スルーホール１０で接続さ
れた表裏両面の導体配線８をリードフレーム外端子９に
引き出すことができる。Furthermore, the through hole 10 is wired on both sides as shown in FIG.
When the circuit chip 1'' provided with is mounted on the stage 6 of the lead frame 3', and the connection terminal 20 of the circuit chip 1'' and the internal lead terminal 40 of the lead frame 3'' are connected with the bonding wire 7, The conductor wiring 8 on both the front and back surfaces connected by the through hole 10 can be drawn out to the terminal 9 outside the lead frame.
なお、最近は上記スルーホール以外に、孔の中を全て金
属で充填した、いわゆる、金属ビアも同様の目的で使用
される場合がある。Recently, in addition to the above-mentioned through holes, so-called metal vias, in which the holes are completely filled with metal, are sometimes used for the same purpose.
上記のスルーホールの形成には、たとえば、セラミック
基板にレーザなどで孔を明け、そこにＣｕペーストなど
により導体層を形成する方法、あるいは、焼成前のセラ
ミックシート、いわゆる、グリーンシートと呼ばれるも
のに孔を明け、同じくＣｕペーストなどの金属導体を埋
め込む等の方法が行なわれている。The above-mentioned through holes can be formed by, for example, making holes in a ceramic substrate using a laser or the like and forming a conductor layer there using Cu paste, or by using a ceramic sheet before firing, a so-called green sheet. Other methods include drilling holes and filling them with metal conductors such as Cu paste.
しかし、前者の方法では、孔の中の導体層形成が不完全
で品質のバラツキが出やすい。However, in the former method, the formation of the conductor layer inside the hole is incomplete and the quality tends to vary.
また、後者の方法では、セラミック基板の焼成前に孔を
明けているので、高温焼成による基板の収縮があり、と
くに高密度、高精度の配線パターンのものに対しては、
基板の変形による孔の位置決めの困難さを生じるほか、
スルーホール部分の平坦性が悪くなるなど種々の問題が
あり、その解決が必要であった。In addition, in the latter method, holes are made before firing the ceramic substrate, so the substrate shrinks due to high-temperature firing, especially for those with high-density and high-precision wiring patterns.
In addition to making it difficult to position holes due to deformation of the board,
There were various problems such as poor flatness of the through-hole portion, and it was necessary to solve these problems.
上記の課題は、回路チップ１を搭載するリードフレーム
の相隣る内部リード端子４ａおよび４ｂが連結されてタ
イバー５に接続した連結内端子４を、少なくとも１箇所
に設けたリードフレーム３を設け、前記リードフレーム
３のステージ６上に両面配線回路チップ１を搭載し、前
記両面配線回路チップ１の表裏両面の導体配線接続用端
子２ａおよび２ｂと前記連結内端子４の内部リード端子
４ａおよび４ｂとを、それぞれボンディングワイヤ７で
接続して前記表裏両面の接続用端子２ａと２ｂの間を短
絡して混成集積回路を構成することにより解決すること
ができる。The above-mentioned problem is solved by providing a lead frame 3 in which adjacent internal lead terminals 4a and 4b of the lead frame on which the circuit chip 1 is mounted are connected and a connected internal terminal 4 is provided at at least one location and connected to a tie bar 5. The double-sided wiring circuit chip 1 is mounted on the stage 6 of the lead frame 3, and the conductor wiring connection terminals 2a and 2b on both the front and back surfaces of the double-sided wiring circuit chip 1 and the internal lead terminals 4a and 4b of the connection internal terminal 4 are connected to each other. This problem can be solved by constructing a hybrid integrated circuit by connecting the connecting terminals 2a and 2b on both the front and back surfaces with bonding wires 7 and short-circuiting them.
本発明によれば、表裏両面の導体配線間の接続は、２本
のボンディングワイヤ７とリードフレーム３の連結内端
子４によって行なわれるので、回路チップ１にはスルー
ホールを形成する必要がないのである。According to the present invention, since the connection between the conductor wiring on both the front and back surfaces is made by the two bonding wires 7 and the connecting terminals 4 of the lead frame 3, there is no need to form through holes in the circuit chip 1. be.
第１図は本発明のリードフレームの実施例を説明する図
で、リードフレーム３には、たとえば、厚さ０．１ ｍ
ｍの調合金製の薄板を使用する。FIG. 1 is a diagram for explaining an embodiment of the lead frame of the present invention, and the lead frame 3 has a thickness of 0.1 m, for example.
A thin plate made of a prepared alloy of m is used.
図中、４は連結内端子で、隣合った２本の内部リード端
子４ａと４ｂとがタイバー５とは別に図示のごとくショ
ートバーにより短絡されたＨ型の形状をなしている。６
は回路チップ１をグイボンディングするスデージで、本
発明では両面実装基板を対象としているので、裏面の実
装部の接触を避けるため、４分割ステージを用いている
。９はリードフレームの外端子である。In the figure, reference numeral 4 denotes a connection internal terminal, which has an H-shape in which two adjacent internal lead terminals 4a and 4b are short-circuited by a short bar in addition to the tie bar 5 as shown in the figure. 6
1 is a stage for firmly bonding the circuit chip 1, and since the present invention is intended for double-sided mounting boards, a 4-part stage is used to avoid contact between the mounting parts on the back side. 9 is an external terminal of the lead frame.
図には連結内端子４が各辺に１つ一一形成されているも
のを示したが、必要に応じて２個以上、また、その位置
も任意に配置することができる。Although the figure shows one connection inner terminal 4 formed on each side, two or more inner connection terminals 4 can be arranged as needed, and the positions thereof can be arbitrarily arranged.
また、本実施例は４辺からリードを出すリードフレーム
を示したが、その他、たとえば、対向する２辺からリー
ド端子を出す集積回路用リードフレームであっても適用
できることは言うまでもない。Further, although this embodiment shows a lead frame with leads coming out from four sides, it goes without saying that it can also be applied to other lead frames for integrated circuits, for example, lead terminals coming out from two opposing sides.
第２図は本発明の連結内端子の他の実施例を示す図であ
る。第１図ではＨ型の連結内端子を示したが、形状はそ
れに限定されるものではなく、多様な変形が考えられる
。たとえば、同図（イ）はフォーク型をなし、モールド
樹脂外装後のリード切断部のリード露出部を少なくする
ことができる。FIG. 2 is a diagram showing another embodiment of the connecting inner terminal of the present invention. Although FIG. 1 shows an H-shaped connecting inner terminal, the shape is not limited to this, and various modifications are possible. For example, FIG. 2A shows a fork-shaped structure, which can reduce the exposed portion of the lead at the lead cutting portion after sheathing with molded resin.
同図（ロ）は、第１図と同じくＨ型内端子であるが、外
端子が通常の端子ピッチで導出されており、モールド樹
脂外装後も遊び端子として、そのま−残しておけば外観
上も、また、デバイス支持の強度維持の点でも好ましい
ような場合に適している。The same figure (b) shows the H-shaped inner terminals as in Figure 1, but the outer terminals are drawn out at the normal terminal pitch, and can be left as idle terminals even after being covered with molded resin. The above is also suitable in cases where it is preferable to maintain the strength of supporting the device.
その他、同図（ハ）〜（ホ）などの変形された連結内端
子を使用することができる。In addition, modified internal connection terminals such as those shown in FIGS.
第３図は本発明のリードフレームを使用した接続構造の
実施例の詳細説明図で、同図（イ）は平面図、（ロ）は
Ａ−Ａ矢視図である。FIG. 3 is a detailed explanatory diagram of an embodiment of a connection structure using the lead frame of the present invention, in which (a) is a plan view and (b) is a view taken along the line A-A.
図中、２ａは回路チップ１の表面の導体配線パターン８
の接続用端子で、ボンディングワイヤ７ａのポンディン
グパッドとして用いられる。２ｂは同じく回路チップ１
の裏面の導体配線パターン８の接続用端子で、ボンディ
ングワイヤ７ｂのポンディングパッドとして用いられる
。In the figure, 2a is a conductor wiring pattern 8 on the surface of the circuit chip 1.
This connection terminal is used as a bonding pad for the bonding wire 7a. 2b is also circuit chip 1
This is a connection terminal for the conductor wiring pattern 8 on the back surface of the board, and is used as a bonding pad for the bonding wire 7b.
同図（イ）の−点破線Ｂ−Ｂ’は、後で述べるモールド
樹脂外装の外縁部を示しており、その破線から左側は樹
脂に覆われる。また、そこから右側は外リードとなる部
分で、モールド樹脂外装の後タイバー５をカットしリー
ドの曲げ加工を行なう。The - dotted broken line BB' in FIG. 3A indicates the outer edge of the molded resin exterior, which will be described later, and the left side of the broken line is covered with resin. Further, on the right side from there is a portion that will become the outer lead, and after the molded resin exterior, the tie bar 5 is cut and the lead is bent.
回路チップ１の表面の接続用端子２ａと裏面の接続用端
子２ｂとは、ボンディングワイヤ７ａ。The connection terminals 2a on the front surface of the circuit chip 1 and the connection terminals 2b on the back surface are bonding wires 7a.
７ｂ、およびフォーク型連結内端子４を通じて接続され
、上述のモールド樹脂外装後タイバー５をカットしても
、外装樹脂の内部において電気的に接続が保たれている
ことがわかる。7b and the fork-type connecting inner terminal 4, and it can be seen that even if the tie bar 5 is cut after the above-mentioned molded resin exterior, the electrical connection is maintained inside the exterior resin.
第４図は本発明による混成集積回路の実施例の外観図で
、１１はトランスファー成形によるモールド樹脂外装で
ある。Ｂ−Ｂ’の破線は前述のモールド樹脂外装の外縁
部である。連結内端子４は切断されて、切り口だけが外
装樹脂面に露出して見える。勿論、前記のごとく、これ
をカットせずに遊び端子として残しておいてもよいこと
は言うまでもない。FIG. 4 is an external view of an embodiment of a hybrid integrated circuit according to the present invention, and numeral 11 is a molded resin exterior formed by transfer molding. The broken line B-B' is the outer edge of the molded resin exterior described above. The connection inner terminal 4 is cut, and only the cut end is exposed and visible on the exterior resin surface. Of course, as mentioned above, it goes without saying that this may be left as an idle terminal without being cut.
なお、本発明は混成集積回路だけでなく、半導体集積回
路にも適用できることは勿論である。Note that the present invention is of course applicable not only to hybrid integrated circuits but also to semiconductor integrated circuits.
以上述べたように本発明によれば、基板にスルーホール
を設けることなく、両面配線回路チップの導体配線端子
間を、リードフレームの連結内端子により、極めて容易
に、かつ、確実に接続することができるので、混成集積
回路の高信頼度化と低価格化に寄与するところが極めて
大きい。As described above, according to the present invention, the conductor wiring terminals of the double-sided wiring circuit chip can be connected extremely easily and reliably by the connecting terminals of the lead frame without providing through holes in the board. This greatly contributes to higher reliability and lower cost of hybrid integrated circuits.
第１図は本発明のリードフレームの実施例を説明する図
、
第２図は本発明の連結内端子の他の実施例を示す図、
第３図は本発明のリードフレームを使用した接続構造の
実施例の詳細説明図、
第４図は本発明による混成集積回路の実施例の外観図、
第５図は従来の接続構造の一例を示す概観図、第６図は
従来のスルーホールによる両面配線基板の接続構造図で
ある。
図において、
１は回路チップ、
２ （２ａ、２ｂ）は接続用端子、
３はリードフレーム、
４ａ、４ｂは相隣る内部リード端子、
４は連結内端子、
５はタイバー
６はステージ、
７はボンディングワイヤ、
８は導体配線、
９はリードフレーム外端子、
１０はスルーホールである。
４改、４ｂ：布Ｎ年ゴ円郭９−Ｆ拙翳子不實明のり一ド
フし一ムの突如例と説明１１国第 １ 図
男４１１
（＝）
＄そ８月の浬斧６内嶋子の泡の奥オ仁１便ｊ＆ホ■図男
２図
第 ５ｒ５！ＪFig. 1 is a diagram illustrating an embodiment of the lead frame of the present invention, Fig. 2 is a diagram illustrating another embodiment of the connecting terminal of the present invention, and Fig. 3 is a connection structure using the lead frame of the present invention. 4 is an external view of an embodiment of the hybrid integrated circuit according to the present invention, FIG. 5 is an overview showing an example of a conventional connection structure, and FIG. 6 is a conventional through-hole double-sided connection diagram. It is a connection structure diagram of a wiring board. In the figure, 1 is a circuit chip, 2 (2a, 2b) are connection terminals, 3 is a lead frame, 4a, 4b are adjacent internal lead terminals, 4 is a connecting terminal, 5 is a tie bar 6 is a stage, 7 is a stage A bonding wire, 8 a conductor wiring, 9 a terminal outside the lead frame, and 10 a through hole. 4 revised, 4b: Cloth N year Goenkaku 9-F. Sudden example and explanation of Fujime Noriichi Dofu Shiichimu 11th country No. 1 Zuo 411 (=) $So August's Peng Ax 6 Uchijima Child's bubble Okuojin 1st flight j & ho ■ Zuo 2nd figure 5r5! J
Claims (2)
隣る内部リード端子（４ａ、４ｂ）が連結されてタイバ
ー（５）に接続した連結内端子（４）を、少なくとも１
箇所に設けたことを特徴とするリードフレーム。(1) Adjacent internal lead terminals (4a, 4b) of the lead frame on which the circuit chip (1) is mounted are connected and connected to the tie bar (5) at least once.
A lead frame characterized by being provided at certain points.
両面配線回路チップ（１）を搭載し、前記両面配線回路
チップ（１）の表裏両面の導体配線接続用端子（２ａ、
２ｂ）と前記連結内端子（４）の内部リード端子（４ａ
、４ｂ）とを、それぞれボンディングワイヤ（７）で接
続して前記表裏両面の接続用端子（２ａ、２ｂ）間を短
絡したことを特徴とする混成集積回路。(2) A double-sided wiring circuit chip (1) is mounted on the stage (6) of the lead frame (3), and conductor wiring connection terminals (2a,
2b) and the internal lead terminal (4a) of the connection internal terminal (4).
, 4b) are connected by bonding wires (7) to short-circuit between the connecting terminals (2a, 2b) on both the front and back surfaces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9581789A JPH02273961A (en) | 1989-04-14 | 1989-04-14 | Lead frame and hybrid integrated circuit using same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9581789A JPH02273961A (en) | 1989-04-14 | 1989-04-14 | Lead frame and hybrid integrated circuit using same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02273961A true JPH02273961A (en) | 1990-11-08 |
Family
ID=14147975
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9581789A Pending JPH02273961A (en) | 1989-04-14 | 1989-04-14 | Lead frame and hybrid integrated circuit using same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02273961A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5521428A (en) * | 1993-03-22 | 1996-05-28 | Motorola, Inc. | Flagless semiconductor device |
| DE19612392A1 (en) * | 1996-03-28 | 1997-10-02 | Siemens Ag | Semiconductor chip package of paddle-free design |
-
1989
- 1989-04-14 JP JP9581789A patent/JPH02273961A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5521428A (en) * | 1993-03-22 | 1996-05-28 | Motorola, Inc. | Flagless semiconductor device |
| DE19612392A1 (en) * | 1996-03-28 | 1997-10-02 | Siemens Ag | Semiconductor chip package of paddle-free design |
| DE19612392B4 (en) * | 1996-03-28 | 2004-01-22 | Infineon Technologies Ag | Semiconductor device with lead frame |
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