JP2000196153A - Chip electronic component and manufacture thereof - Google Patents

Chip electronic component and manufacture thereof

Info

Publication number
JP2000196153A
JP2000196153A JP10371267A JP37126798A JP2000196153A JP 2000196153 A JP2000196153 A JP 2000196153A JP 10371267 A JP10371267 A JP 10371267A JP 37126798 A JP37126798 A JP 37126798A JP 2000196153 A JP2000196153 A JP 2000196153A
Authority
JP
Japan
Prior art keywords
molded body
insulating substrate
electronic component
cut
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP10371267A
Other languages
Japanese (ja)
Inventor
Shoichiro Murata
昌一郎 村田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP10371267A priority Critical patent/JP2000196153A/en
Publication of JP2000196153A publication Critical patent/JP2000196153A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Led Device Packages (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a chip electronic component of side-mounting type and its manufacturing method, where the electronic component is surely enhanced in mounting strength and electrical connection reliability and self-aligned, when it is mounted on a motherboard. SOLUTION: A board 1 where an LED element 3 is assembled is sealed with a rectangular parallelopipedic molded epoxy resin 5. The LED element 3 is mounted on a board 1 to serve as a side light-emitting type element (the direction of light is shown by the arrow in figure), and the board 1 is so set in the resin molded body 5 as to face the front side of the molded body 5. Electrodes 6 provided on the surface of the molded body 5 are so arranged on the upper and lower edges of the molded body 5 for facedown bonding. The board electrodes and the molded body electrodes 6 are electrically connected together with electrodes that come out of the dicing face of the molded body 5 and a plating film formed on the dicing face.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、側面型チップ電子
部品に関し、より詳細には、チップ電子部品の樹脂モー
ルド体の表面に電極を形成してなるチップ電子部品及び
その製造方法に関し、特に例えば、ＬＥＤ、フォトカプ
ラ、フォトトランジスタ等の光半導体デバイスに有効に
適用し得るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a side-type chip electronic component, and more particularly, to a chip electronic component in which electrodes are formed on a surface of a resin mold body of the chip electronic component and a method of manufacturing the same. , LEDs, photocouplers, phototransistors and the like.

【０００２】[0002]

【従来の技術】従来の側面発光型チップＬＥＤの１例を
図１２に斜視図にて示す。図１２において、側面発光型
チップＬＥＤ２０は、マザーボード２１に組み付け、側
面発光する状態に載置した状態にある。側面発光型チッ
プＬＥＤ２０そのものは、ほぼ直方体状の絶縁基板１１
の一面にパターニングされた導電膜からなる電極１２に
半導体発光層を有するＬＥＤ素子１３をマウントし、さ
らにＬＥＤ素子１３を保護しかつ光を所定の方向に導く
ための機能を持つ封止樹脂１５で絶縁基板１１のＬＥＤ
素子１３が載置する面の一部を覆っている。図示の従来
例で採用されている基板の電極構造は、ＬＥＤ素子１３
がマウントされている面からその裏面にわたる４側面に
電極１２が設けられている。そして、絶縁基板１１の両
端の電極１２は、基板１１のＬＥＤ素子１３がマウント
されている面をマザーボード２１に対して垂直になるよ
うに半田接続されている。従って、チップＬＥＤ２０の
マザーボード２１と相対する基板１１の面には電極が存
在しない。これは、一枚の絶縁基板の周囲面に複数チッ
プ分の電極を形成した後、ダイシングにより各チップを
切り出し、切り出された面をマザーボード２１に相対す
るように実装するからである。2. Description of the Related Art FIG. 12 is a perspective view showing an example of a conventional side emission type chip LED. In FIG. 12, the side emission type chip LED 20 is mounted on the motherboard 21 and is placed in a state of emitting side emission. The side emission type chip LED 20 itself is a substantially rectangular parallelepiped insulating substrate 11.
An LED element 13 having a semiconductor light emitting layer is mounted on an electrode 12 made of a conductive film patterned on one surface, and a sealing resin 15 having a function of protecting the LED element 13 and guiding light in a predetermined direction. LED on insulating substrate 11
It covers a part of the surface on which the element 13 is mounted. The electrode structure of the substrate employed in the conventional example shown in FIG.
The electrodes 12 are provided on four side surfaces extending from the surface on which is mounted to the back surface thereof. The electrodes 12 on both ends of the insulating substrate 11 are soldered so that the surface of the substrate 11 on which the LED elements 13 are mounted is perpendicular to the motherboard 21. Therefore, no electrode exists on the surface of the substrate 11 facing the motherboard 21 of the chip LED 20. This is because after forming electrodes for a plurality of chips on the peripheral surface of one insulating substrate, each chip is cut out by dicing, and the cut out surface is mounted so as to face the motherboard 21.

【０００３】このように従来の電極構造では、取り付け
強度が弱く、接触によりチップ部品の脱落が起きる危険
性がある。特に、側面発光型チップＬＥＤの場合には、
マザーボードの端部に取り付けられることが多いので、
ボードを取り扱っている時に接触により脱落等が起きる
危険性が高い。さらに、マザーボードの配線面に対する
チップＬＥＤ側の面には電極が設けられていないことか
ら、半田付け時にセルフ・アライメントが働かず取り付
け後の位置精度が出ない、或いは接続不良が起きるとい
った問題や、小型のチップ部品の場合に半田付ができな
かったり、マンハッタン現象でチップが起立するという
問題が生じる。As described above, in the conventional electrode structure, the mounting strength is weak, and there is a danger that chip components may fall off due to contact. In particular, in the case of a side emission type chip LED,
Since it is often attached to the end of the motherboard,
When handling the board, there is a high risk of falling off due to contact. Furthermore, since no electrode is provided on the surface of the chip LED side with respect to the wiring surface of the motherboard, self-alignment does not work at the time of soldering, so that positional accuracy after mounting is not obtained, or a problem such as poor connection occurs, In the case of a small chip component, there are problems that soldering cannot be performed and the chip stands up due to the Manhattan phenomenon.

【０００４】[0004]

【発明が解決しようとする課題】本発明は、上述した従
来の側面型チップ電子部品における問題点に鑑みてなさ
れたものであって、その目的は、前記電子部品をマザー
ボードに実装接続する場合に、取り付け強度や電気的接
続が確保され、半田付け時にセルフ・アライメントが働
くような構造を持つ前記チップ電子部品及びその製造方
法を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems in the conventional side-type chip electronic component, and has as its object to mount and connect the electronic component to a motherboard. Another object of the present invention is to provide a chip electronic component having a structure in which mounting strength and electrical connection are ensured and self-alignment works during soldering, and a method of manufacturing the same.

【０００５】[0005]

【課題を解決するための手段】請求項１の発明は、導電
層を設けた絶縁基板に半導体素子をマウントし、該絶縁
基板と半導体素子を樹脂封止した素子モールド体であっ
て、その外面に該絶縁基板の端面が導電層の一部ととも
に露出する素子モールド体と、前記素子モールド体の外
面に前記導電層に導電接続するように設けた電極とを有
するチップ電子部品を構成する。According to a first aspect of the present invention, there is provided an element molded body in which a semiconductor element is mounted on an insulating substrate provided with a conductive layer, and the insulating substrate and the semiconductor element are sealed with a resin. A chip electronic component comprising: an element molded body in which an end face of the insulating substrate is exposed together with a part of the conductive layer; and an electrode provided on the outer surface of the element molded body so as to be conductively connected to the conductive layer.

【０００６】請求項２の発明は、請求項１記載のチップ
電子部品において、前記電極を設ける面を、前記半導体
素子がマウントされた前記絶縁基板の面に対して略垂直
をなすようにした前記素子モールド体の側面としたこと
を特徴とするものである。According to a second aspect of the present invention, in the chip electronic component according to the first aspect, the surface on which the electrode is provided is substantially perpendicular to the surface of the insulating substrate on which the semiconductor element is mounted. The side surface of the element mold body is characterized.

【０００７】請求項３の発明は、請求項１又は２記載の
側面型チップ電子部品において、前記絶縁基板にマウン
トされる素子を半導体発光素子としたことを特徴とする
ものである。According to a third aspect of the present invention, in the side-type chip electronic component according to the first or second aspect, the element mounted on the insulating substrate is a semiconductor light emitting element.

【０００８】請求項４の発明は、絶縁基板に半導体素子
に応じた形状の導電層の単位パターンの繰り返しパター
ンを形成し、前記パターンを形成した絶縁基板に複数の
半導体素子を組み立て、前記絶縁基板及び該絶縁基板に
組み立てた半導体素子を樹脂モールドし、このモールド
体を切断してその切断面に前記パターンの端部断面を露
出させる切り出しを行い、前記切り出しにより露出させ
たパターンの端部断面を含む切断面を同一面に配置し前
記モールド体から切り出されたモールド体をさらに樹脂
モールドして素子モールド体を形成し、この素子モール
ド体において同一面に配置された前記切断面を含む全面
に導電金属のメッキを施し、前記メッキを施した面から
不要なメッキ部分をパターニング除去し、前記メッキの
パターニング除去を行った素子モールド体を個々のチッ
プ電子部品に分割することを特徴とするチップ電子部品
の製造方法を構成する。According to a fourth aspect of the present invention, a repetitive pattern of a unit pattern of a conductive layer having a shape corresponding to a semiconductor element is formed on an insulating substrate, and a plurality of semiconductor elements are assembled on the insulating substrate on which the pattern is formed. And, the semiconductor element assembled on the insulating substrate is resin-molded, the molded body is cut, and a cut surface is cut out to expose an end cross section of the pattern, and an end cross section of the pattern exposed by the cut is formed. The cut surface including the cut surface is arranged on the same surface, and the molded body cut out from the molded body is further resin-molded to form an element molded body, and the entire surface of the element molded body including the cut surface arranged on the same surface is electrically conductive. Plating metal, removing unnecessary plating from the plated surface by patterning and removing the patterning of the plating. Dividing the went element molded body into individual chips electronic components constituting the manufacturing method of the chip electronic component according to claim.

【０００９】[0009]

【発明の実施の形態】以下、本発明によるチップ電子部
品及びその製造方法の実施の形態を添付する図面に基づ
いて説明する。図１は、本発明によるチップ電子部品の
一実施形態例の側面発光型チップＬＥＤの外観を斜視図
にて示す。また、図２及び図３は、図１に示される側面
発光型チップＬＥＤの平面図及び側面図をそれぞれ示
す。本実施形態のチップＬＥＤは、両端部に対向する一
対の導電層２，２を設けた平面視矩形状絶縁基板１と、
絶縁基板１の一方の導電層２上に下面を導体ペーストで
マウントされ、上面を他方の導電層２とワイヤ４で電気
的に接続されたＬＥＤ素子３とをエポキシ樹脂５で封止
し、図１に示すように、全体をほぼ直方体に成形した樹
脂モールド体をなす。ここでは、側面発光型を構成すべ
く（図１は側面発光状態にあり、発光方向を図示の矢印
にて示す）、樹脂モールド体の側面が発光面となるよう
にＬＥＤ素子３をマウントする基板１を発光面となる側
面に平行な関係におき、素子モールド体を成形する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a chip electronic component and a method of manufacturing the same according to the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a perspective view showing the appearance of a side-emitting chip LED as an embodiment of a chip electronic component according to the present invention. 2 and 3 show a plan view and a side view of the side-emitting chip LED shown in FIG. 1, respectively. The chip LED of the present embodiment includes a rectangular insulated substrate 1 in a plan view provided with a pair of conductive layers 2 and 2 opposed to both ends,
The lower surface is mounted on one conductive layer 2 of the insulating substrate 1 with a conductive paste, and the LED element 3 electrically connected to the other conductive layer 2 by wires 4 on the upper surface is sealed with epoxy resin 5. As shown in FIG. 1, a resin molded body formed into a substantially rectangular parallelepiped as a whole is formed. Here, in order to form a side emission type (FIG. 1 is in a side emission state, the light emission direction is indicated by an arrow in the drawing), a substrate on which the LED element 3 is mounted so that the side surface of the resin mold body becomes a light emission surface. 1 is placed in a relationship parallel to the side surface serving as a light emitting surface, and an element mold body is formed.

【００１０】また、素子モールド体の表面には、電極６
を設ける。電極６の配置は、図１乃至３に示すように、
マザーボード側の配線（図示せず）にボンディングする
ために、素子モールド体の上下面（すなわち、発光面を
なす側面に対する上下面）とし、この実施形態において
は、向かい合う上下面の両端部に沿い配置する。このよ
うに設けられる電極６には絶縁基板１の導電層２を導電
接続しなければならない。その接続方法は、絶縁基板１
に設けた導電層２を素子モールド体の上下面に絶縁基板
１の端面とともに露出させ、露出させた導電層２を含む
面に電極６を形成することにより行う。なお、本実施形
態では樹脂モールド体の上下両面に電極６を設けている
が、単一のＬＥＤ素子を載せる場合、電極は基本的にい
ずれかの面に一対あればよい。また、極性を選択してマ
ザーボード上に実装する必要がある場合には、共通の電
極を上下両面にそれぞれ設け、面を選択して用いる。The electrode 6 is provided on the surface of the element mold body.
Is provided. The arrangement of the electrodes 6 is as shown in FIGS.
In order to bond to the wiring (not shown) on the motherboard side, the upper and lower surfaces of the element mold body (that is, the upper and lower surfaces with respect to the side surface forming the light emitting surface) are provided. I do. The conductive layer 2 of the insulating substrate 1 must be conductively connected to the electrode 6 thus provided. The connection method is as follows.
This is performed by exposing the conductive layer 2 provided on the substrate and the end surface of the insulating substrate 1 to the upper and lower surfaces of the element mold body, and forming the electrode 6 on the surface including the exposed conductive layer 2. In the present embodiment, the electrodes 6 are provided on the upper and lower surfaces of the resin mold body. However, when a single LED element is mounted, basically the electrodes need only be paired on one of the surfaces. Further, when it is necessary to select the polarity and mount it on the motherboard, a common electrode is provided on each of the upper and lower surfaces, and the surface is selected and used.

【００１１】上記した側面発光型チップＬＥＤは、樹脂
モールド体の下面に必要な大きさの両極用の電極を設け
ているので、マザーボード側の配線にボンディングする
場合に、両電極がマザーボード側の配線パターン面に面
同士で接触することになる。そのため、取り付け強度や
電気的接続が十分に確保され、また、半田付けの際にセ
ルフアライメントが働くから、位置精度を出すことがで
き、接続不良や、マンハッタン現象でチップの起立が発
生するという問題が起きることがなく、半田付けの信頼
性が向上する。また、マザーボードの端部への実装を必
要とする側面発光型チップＬＥＤにおいて、従来の不完
全な接続方法を採ったために起きていた接触によるチッ
プの脱落を無くすことができる。In the above-mentioned side-emitting type chip LED, electrodes for both electrodes having a required size are provided on the lower surface of the resin mold body. Therefore, when bonding to the wiring on the motherboard side, both electrodes are connected to the wiring on the motherboard side. The surfaces come into contact with each other on the pattern surface. As a result, sufficient mounting strength and electrical connection are ensured, and self-alignment works during soldering, which can increase positional accuracy, resulting in poor connections and the chip standing up due to the Manhattan phenomenon. No soldering occurs and the reliability of soldering is improved. In addition, in the side-emitting chip LED that needs to be mounted on the end of the motherboard, it is possible to eliminate the chip coming off due to the contact caused by the conventional incomplete connection method.

【００１２】次に、本発明によるチップ電子部品の製造
方法の一実施形態として、上記で示した側面発光型チッ
プＬＥＤの作成法について、以下にその説明をする。図
４ないし図１１は、本実施形態の概要を説明するための
図で、作成過程で加工・処理されるチップＬＥＤの状態
を順に表す図である。なお、同図中においてチップＬＥ
Ｄの構成要素には図１乃至３と共通の参照番号を付して
いる。図４ないし図１１に基づき、以下に本実施形態の
側面発光型チップＬＥＤの作成の工程に従い、詳細に説
明する。なお、この実施形態では、図４に示すように、
導電層２を絶縁基板１の片面上のみに形成した例を示し
ているが、基板１の両面に側面を介して亘るように形成
してもよく、この場合、基板１の両面にＬＥＤ素子を組
み立てることも出来る。Next, as one embodiment of a method of manufacturing a chip electronic component according to the present invention, a method of manufacturing the above-described side-emitting chip LED will be described below. 4 to 11 are diagrams for explaining the outline of the present embodiment, and are diagrams sequentially illustrating states of chip LEDs that are processed and processed in a production process. Note that in FIG.
The components of D are denoted by the same reference numerals as in FIGS. 4 to 11, a detailed description will be given below in accordance with the steps of manufacturing the side-emitting chip LED of the present embodiment. In this embodiment, as shown in FIG.
Although the example in which the conductive layer 2 is formed only on one surface of the insulating substrate 1 is shown, the conductive layer 2 may be formed on both surfaces of the substrate 1 via side surfaces. In this case, LED elements are provided on both surfaces of the substrate 1. Can be assembled.

【００１３】（素子組立工程：図４参照）ＬＥＤ素子３
を絶縁基板１へ組み立てる工程で、この例では、絶縁基
板１上に縦及び横方向に整列した繰り返しパターン配列
で形成されている複数チップ分の導電層２の各素子マウ
ント部に、ＬＥＤ素子３を銀ペースト等によりダイボン
ディングし、さらに、ＬＥＤ素子３のもう一方の電極と
前記マウント部と対向する導電層２との間に、金線のワ
イヤ４によりワイヤボンディングを行う工程である。(Element assembling step: see FIG. 4) LED element 3
In this example, the LED element 3 is mounted on each element mounting portion of the conductive layer 2 for a plurality of chips formed on the insulating substrate 1 in a repetitive pattern arrangement aligned in the vertical and horizontal directions. Is performed by die bonding with a silver paste or the like, and further, wire bonding is performed with a gold wire 4 between the other electrode of the LED element 3 and the conductive layer 2 facing the mount portion.

【００１４】（樹脂封止工程：図５参照）この工程で
は、前工程で組み立てた絶縁基板１上のＬＥＤ素子３及
びボンディングしたワイヤ４まわりを透光性の樹脂でモ
ールドし、少なくともＬＥＤ素子３とワイヤ４部分を封
止する。この樹脂封止工程を終了した時点における状態
を図５に示す。ここでは、ＬＥＤ素子３及びボンディン
グしたワイヤ４まわりをモールドした樹脂５が凸部状に
横方向に一定の高さで連なり、樹脂５の凸部と凸部の間
は、樹脂モールドしないために導電層２が露出してい
る。(Resin sealing step: see FIG. 5) In this step, the periphery of the LED element 3 and the bonded wire 4 on the insulating substrate 1 assembled in the previous step is molded with a translucent resin, and at least the LED element 3 And the wire 4 are sealed. FIG. 5 shows a state at the time when the resin sealing step is completed. Here, the resin 5 molded around the LED element 3 and the bonded wire 4 is connected in a convex shape at a constant height in the horizontal direction, and between the convex portions of the resin 5 is not conductive because the resin is not molded. Layer 2 is exposed.

【００１５】（樹脂封止基板切り出し工程：図６参照）
この工程は、前の樹脂封止工程で封止された基板を切り
出す工程で、ダイサー等の手段を用い導電層２の縦方向
の配列に沿い、かつ樹脂封止工程で封止を必要としたＬ
ＥＤ素子３及びボンディングしたワイヤ４まわりが保存
されるように、素子列の中間（図５のＡ−Ａ破線）を切
断してバー状の素子列を切り出す。図６は、この樹脂封
止基板切り出し工程を終了した時点における状態を示
す。図示のように、前工程で導電層２は、繰り返しパタ
ーンを縦及び横方向に連続パターンの形態をとるように
形成しているので、この切り出しにより、横方向に並ぶ
素子３の間で連続していた導電層２が切り離され、導電
層２の端部断面が露出される。(Resin sealing substrate cutting process: see FIG. 6)
This step is a step of cutting out the substrate sealed in the previous resin encapsulation step, along the vertical arrangement of the conductive layers 2 using a dicer or the like, and requires encapsulation in the resin encapsulation step. L
A bar-shaped element row is cut out by cutting the middle of the element row (broken line AA in FIG. 5) so that the periphery of the ED element 3 and the bonded wire 4 are preserved. FIG. 6 shows a state at the time when the resin sealing substrate cutting step is completed. As shown in the figure, in the previous step, the conductive layer 2 is formed so that the repetitive pattern takes the form of a continuous pattern in the vertical and horizontal directions. The conductive layer 2 which has been cut off is separated, and an end section of the conductive layer 2 is exposed.

【００１６】（樹脂モールド工程：図７、図８参照）こ
の工程は、前の樹脂封止基板切り出し工程にて切り出さ
れた素子列を配列し直し、全体を樹脂モールドする工程
である。この工程では、先ず、図７に示すように、切り
出された各素子列を横置きにし、かつ各素子列の切断面
を同一平面上に置き、さらに各素子列を縦方向に素子の
単位で整列させるようにして各素子列を重ね配列し直
す。このように配列することにより、後述する各チップ
ＬＥＤへのダイシングによる分割を可能とする次に、こ
の様な配列を保って上下を成形金型（図示せず）で締め
付け、成形金型と各素子列とにより作られるキャビテイ
に透光性の樹脂５ｍを充填し、固化させ樹脂モールドす
る。図８は、この樹脂モールド工程を終了した時点にお
ける状態を示す。図示のように、図７における各素子列
間の空間に樹脂５ｍが充填され、全体として直方体のモ
ールド体をなしている。なお、図８の状態にあるモール
ド体の上面（及び／又は下面）は、図７の配置を取った
時の各素子列の切断面を維持していること、つまり、樹
脂封止基板切り出し工程で切り出された素子列の切断面
内に導電層２の端部断面を露出していることが必要であ
る。従って、樹脂モールド工程で露出していた導電層２
が樹脂５ｍで覆われた場合又はより確実に露出させたい
場合には、露出させる工程（例えば、研磨による）を行
えばよい。(Resin molding step: see FIGS. 7 and 8) This step is a step of rearranging the element rows cut out in the previous resin sealing substrate cutting step and performing resin molding on the whole. In this step, first, as shown in FIG. 7, each cut element row is placed horizontally, and the cut surface of each element row is placed on the same plane, and each element row is vertically arranged in units of elements. Each element row is overlapped and rearranged so as to be aligned. By arranging in this way, it is possible to divide by dicing into each chip LED, which will be described later. Next, while maintaining such an arrangement, the upper and lower parts are tightened by a molding die (not shown), The cavity formed by the element rows is filled with a translucent resin 5m, solidified, and resin molded. FIG. 8 shows a state at the time when the resin molding step is completed. As shown in the drawing, the space between the respective element rows in FIG. 7 is filled with a resin 5m to form a rectangular parallelepiped molded body as a whole. The upper surface (and / or lower surface) of the mold body in the state of FIG. 8 maintains the cut surface of each element row when the arrangement of FIG. 7 is taken, that is, the resin sealing substrate cutting step. It is necessary that the end section of the conductive layer 2 is exposed in the cut surface of the element row cut out by the above. Therefore, the conductive layer 2 exposed in the resin molding process
In the case where is covered with 5 m of resin or when it is desired to expose the resin more reliably, a step of exposing (for example, by polishing) may be performed.

【００１７】（導電金属膜メッキ工程：図９参照）この
工程は、前工程の樹脂モールド工程で得られた直方体状
のモールド体の絶縁基板１の切断面が露出する上面及び
／又は下面の全面に導電金属膜６、例えば、Ｃｕ・Ｎｉ
合金に加えフラッシュ金のメッキを設ける。この時、モ
ールド体の上面（及び／又は下面）に露出している導電
層２に導電金属膜６が接触し、両者間が導電接続する。(Conductive metal film plating step: see FIG. 9) This step is performed on the entire upper surface and / or lower surface where the cut surface of the insulating substrate 1 of the rectangular parallelepiped molded body obtained in the preceding resin molding step is exposed. A conductive metal film 6, for example, Cu.Ni
Flash gold plating is provided in addition to the alloy. At this time, the conductive metal film 6 comes into contact with the conductive layer 2 exposed on the upper surface (and / or lower surface) of the mold body, and the two are conductively connected.

【００１８】（導電金属膜除去工程：図１０参照）この
工程は、前の導電金属膜メッキ工程で行ったメッキ面か
ら不要な部分を除去する工程である。前の工程で直方体
状のモールド体の上面（及び／又は下面）の全面に導電
金属膜６がメッキされているので、各ＬＥＤ素子３が電
気的に接続された対向する一対の導電層２はこの導電金
属膜６により導通された状態にある。そこで、エッチン
グ、研磨等により導電金属膜６を帯状にを除去すること
により各素子列の各ＬＥＤ素子３の対向する一対の導電
層２を一度に分離する。すなわち、先の工程で素子列を
整列させており、導電金属膜６と接続する素子列側の各
ＬＥＤ素子３の導電層２との接続点は直線上に並んでい
るので、この工程が終わった状態を示す図１０に示すよ
うに、縦方向に帯状に導電金属膜６を残し、それ以外の
部分は除去する。(Step of removing conductive metal film: see FIG. 10) This step is a step of removing unnecessary portions from the plated surface performed in the previous conductive metal film plating step. Since the conductive metal film 6 is plated on the entire upper surface (and / or lower surface) of the rectangular parallelepiped mold body in the previous step, the pair of conductive layers 2 to which each LED element 3 is electrically connected is opposed to each other. The conductive metal film 6 is in a conductive state. Then, the conductive metal film 6 is removed in a strip shape by etching, polishing, or the like, thereby separating the pair of conductive layers 2 facing each LED element 3 in each element row at a time. That is, since the element rows are aligned in the previous step, and the connection points of the LED elements 3 connected to the conductive metal film 6 with the conductive layer 2 of each LED element 3 are aligned in a straight line, this step is completed. 10, the conductive metal film 6 is left in a strip shape in the vertical direction, and other portions are removed.

【００１９】（ダイシング工程：図１１参照）この工程
は、側面発光型チップＬＥＤとしての個々の部品に分割
する工程でダイサーにより素子分割を行う。縦方向につ
いては、前工程で帯状に残した導電金属膜６の幅の中央
をカットラインとし、横方向についても等しいピッチで
所定の位置をカットすることにより、図１乃至３に示さ
れたチップＬＥＤを得ることが出来る。ここでは、メッ
キ工程で形成された導電金属膜６の幅の中央をカットラ
インとし、個々のチップＬＥＤへの分割を行っているの
で、分割後のチップＬＥＤの向かい合う上下面における
導電金属膜６による電極の配置は、両端部に沿う配置を
とることになり、チップＬＥＤの構造に図１乃至３に示
すような特徴をもたらす。(Dicing step: see FIG. 11) This step is a step of dividing into individual components as a side emission type chip LED, in which an element is divided by a dicer. In the vertical direction, the center of the width of the conductive metal film 6 left in a strip shape in the previous process is set as a cut line, and predetermined positions are also cut at the same pitch in the horizontal direction, so that the chip shown in FIGS. LED can be obtained. Here, since the center of the width of the conductive metal film 6 formed in the plating step is used as a cut line to divide the individual chip LEDs, the divided portions of the conductive metal film 6 on the upper and lower surfaces facing the chip LEDs after the division are used. The arrangement of the electrodes is arranged along both ends, and brings the features of the chip LED as shown in FIGS.

【００２０】[0020]

【発明の効果】本発明によると、端部に導電層を有する
絶縁基板に素子を載せた組立部品の樹脂モールド体の外
面に絶縁基板の端面を前記導電層とともに露出させ、露
出した導電層の一部乃至全部を含むように樹脂モールド
体の外面に電極を形成することにより、電極と導電層の
導電接続を確保してチップ電子部品を横置き実装に対応
する構成としたため、チップ電子部品を横向きに実装し
た時、樹脂モールド体の下面に形成した電極がマザーボ
ード側の配線パターン面に面同士で接触するので、取り
付け強度や電気的接続が十分に確保される。さらに、電
極と配線とを面同士の接触で半田による接続を行う場合
に、半田付け時にセルフアライメントが働くことから、
従来の例えば側面発光型チップＬＥＤにおいて問題であ
った取り付け後の位置精度、接続不良、或いはマンハッ
タン現象でチップの起立が発生するという問題が生じる
ことがない。また、しばしばマザーボードの端部への実
装が必要である側面発光型チップＬＥＤへ本発明を適用
することにより、従来の側面発光型チップＬＥＤを実装
した場合に起きていた不完全な接続によるチップの脱落
を少なくすることが可能となる。また、本発明の方法に
より、前記特徴を備えた側面型チップ電子部品を容易か
つ効率良く作成することが出来る。According to the present invention, the end surface of the insulating substrate is exposed together with the conductive layer on the outer surface of the resin mold body of the assembled part having the element mounted on the insulating substrate having the conductive layer at the end. Since the electrodes are formed on the outer surface of the resin mold body so as to include a part or all of them, the conductive connection between the electrodes and the conductive layer is ensured, and the chip electronic component is configured to support horizontal mounting. When mounted horizontally, the electrodes formed on the lower surface of the resin mold body are in surface-to-surface contact with the wiring pattern surface on the motherboard side, so that sufficient mounting strength and electrical connection are ensured. Furthermore, when the electrodes and wiring are connected by soldering by surface-to-surface contact, self-alignment works during soldering,
There is no problem that, for example, a problem of a conventional side-emitting chip LED, such as a positional accuracy after mounting, a connection failure, or a problem that the chip is erected due to the Manhattan phenomenon. In addition, by applying the present invention to a side-emitting chip LED that often needs to be mounted on the end of the motherboard, the chip may be incompletely connected due to imperfect connection that occurs when the conventional side-emitting chip LED is mounted. It is possible to reduce the dropout. Further, according to the method of the present invention, it is possible to easily and efficiently produce a side-type chip electronic component having the above characteristics.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明による側面発光型チップＬＥＤの一実施
形態を示す斜視図である。FIG. 1 is a perspective view showing an embodiment of a side-emitting chip LED according to the present invention.

【図２】図１に示される側面発光型チップＬＥＤの平面
図である。FIG. 2 is a plan view of the side-emitting chip LED shown in FIG.

【図３】図１に示される側面発光型チップＬＥＤの側面
図である。FIG. 3 is a side view of the side-emitting chip LED shown in FIG. 1;

【図４】側面発光型チップＬＥＤの製造工程を説明する
図で、素子組立工程における製品の状態を示す。FIG. 4 is a view for explaining a manufacturing process of the side emission type chip LED, showing a state of a product in an element assembling process.

【図５】側面発光型チップＬＥＤの製造工程を説明する
図で、樹脂封止工程における製品の状態を示す。FIG. 5 is a diagram for explaining a manufacturing process of the side emission type chip LED, showing a state of a product in a resin sealing process.

【図６】側面発光型チップＬＥＤの製造工程を説明する
図で、樹脂封止基板切り出し工程における製品の状態を
示す。FIG. 6 is a view for explaining a manufacturing process of the side emission type chip LED, showing a state of a product in a resin sealing substrate cutting step.

【図７】側面発光型チップＬＥＤの製造工程を説明する
図で、樹脂モールド工程における素子列の配置状態を示
す。FIG. 7 is a diagram for explaining a manufacturing process of the side emission type chip LED, and shows an arrangement state of element rows in a resin molding process.

【図８】側面発光型チップＬＥＤの製造工程を説明する
図で、導電金属膜メッキ工程における製品の状態を示
す。FIG. 8 is a view for explaining a manufacturing process of the side emission type chip LED, showing a state of a product in a conductive metal film plating step.

【図９】側面発光型チップＬＥＤの製造工程を説明する
図で、導電金属膜除去工程における製品の状態を示す。FIG. 9 is a view for explaining a manufacturing process of the side emission type chip LED, and shows a state of a product in a conductive metal film removing step.

【図１０】側面発光型チップＬＥＤの製造工程を説明す
る図で、導電金属膜除去工程における製品の状態を示
す。FIG. 10 is a view for explaining the manufacturing process of the side-emitting chip LED, and shows the state of the product in the conductive metal film removing step.

【図１１】側面発光型チップＬＥＤの製造工程を説明す
る図で、ダイシング工程における製品の状態を示す。FIG. 11 is a diagram for explaining a manufacturing process of the side emission type chip LED, showing a state of a product in a dicing process.

【図１２】従来の側面発光型チップＬＥＤの１例をマザ
ーボードへのマウント状態にて示す斜視図である。FIG. 12 is a perspective view showing an example of a conventional side emission type chip LED mounted on a motherboard.

【符号の説明】[Explanation of symbols]

１、１１…絶縁基板、 ２、１２…導電層、 ３、１３…ＬＥＤ素子、 ４…ワイヤ、 ５、１５…樹脂、 ６…電極（導電金属膜）、 ２０…側面発光型チップＬＥＤ、 ２１…マザーボード。 1, 11: insulating substrate, 2, 12: conductive layer, 3, 13: LED element, 4: wire, 5, 15: resin, 6: electrode (conductive metal film), 20: side-emitting chip LED, 21: Motherboard.

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 導電層を設けた絶縁基板に半導体素子を
マウントし、該絶縁基板と半導体素子を樹脂封止した素
子モールド体であって、その外面に該絶縁基板の端面が
導電層の一部とともに露出する素子モールド体と、前記
素子モールド体の外面に前記導電層に導電接続するよう
に設けた電極とを有するチップ電子部品。1. An element molded body in which a semiconductor element is mounted on an insulating substrate provided with a conductive layer, and the insulating substrate and the semiconductor element are sealed with a resin. A chip electronic component comprising: an element mold exposed together with a portion; and an electrode provided on an outer surface of the element mold so as to be conductively connected to the conductive layer. 【請求項２】 前記電極を設ける面を、前記半導体素子
がマウントされた前記絶縁基板の面に対して略垂直をな
すようにした前記素子モールド体の側面としたことを特
徴とする請求項１記載のチップ電子部品。2. The device according to claim 1, wherein the surface on which the electrodes are provided is a side surface of the element mold body that is substantially perpendicular to a surface of the insulating substrate on which the semiconductor element is mounted. The described chip electronic component. 【請求項３】 前記絶縁基板にマウントされる素子を半
導体発光素子としたことを特徴とする請求項１又は２記
載のチップ電子部品。3. The chip electronic component according to claim 1, wherein the element mounted on the insulating substrate is a semiconductor light emitting element. 【請求項４】 絶縁基板に半導体素子に応じた形状の導
電層の単位パターンの繰り返しパターンを形成し、前記
パターンを形成した絶縁基板に複数の半導体素子を組み
立て、前記絶縁基板及び該絶縁基板に組み立てた半導体
素子を樹脂モールドし、このモールド体を切断してその
切断面に前記パターンの端部断面を露出させる切り出し
を行い、前記切り出しにより露出させたパターンの端部
断面を含む切断面を同一面に配置し前記モールド体から
切り出されたモールド体をさらに樹脂モールドして素子
モールド体を形成し、この素子モールド体において同一
面に配置された前記切断面を含む全面に導電金属のメッ
キを施し、前記メッキを施した面から不要なメッキ部分
をパターニング除去し、前記メッキのパターニング除去
を行った素子モールド体を個々のチップ電子部品に分割
することを特徴とするチップ電子部品の製造方法。4. A repetitive pattern of a unit pattern of a conductive layer having a shape corresponding to a semiconductor element is formed on an insulating substrate, a plurality of semiconductor elements are assembled on the insulating substrate on which the pattern is formed, and a plurality of semiconductor elements are assembled on the insulating substrate and the insulating substrate. The assembled semiconductor element is subjected to resin molding, the molded body is cut, and a cut is made to expose an end cross section of the pattern on the cut surface, and the cut surface including the end cross section of the pattern exposed by the cut is the same. The molded body cut out from the molded body placed on the surface is further resin-molded to form an element molded body, and the entire surface of the element molded body including the cut surface arranged on the same surface is plated with a conductive metal. An element molding that removes an unnecessary plating portion from the plated surface by patterning and removes the plating by patterning; A chip electronic component manufacturing method comprising dividing a chip body into individual chip electronic components.
JP10371267A 1998-12-25 1998-12-25 Chip electronic component and manufacture thereof Withdrawn JP2000196153A (en)

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JP10371267A JP2000196153A (en) 1998-12-25 1998-12-25 Chip electronic component and manufacture thereof

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JP10371267A JP2000196153A (en) 1998-12-25 1998-12-25 Chip electronic component and manufacture thereof

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US7687292B2 (en) 2005-06-20 2010-03-30 Samsung Electro-Mechanics Co., Ltd. Light emitting diode package with metal reflective layer and method of manufacturing the same
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