JPH02249255A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02249255A JPH02249255A JP7110689A JP7110689A JPH02249255A JP H02249255 A JPH02249255 A JP H02249255A JP 7110689 A JP7110689 A JP 7110689A JP 7110689 A JP7110689 A JP 7110689A JP H02249255 A JPH02249255 A JP H02249255A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- mask
- resist pattern
- etched
- contact hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 239000010410 layer Substances 0.000 abstract description 18
- 238000013508 migration Methods 0.000 abstract description 6
- 230000005012 migration Effects 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract description 2
- 238000005530 etching Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 101000797951 Anguilla japonica Galactose-binding lectin l-1 Proteins 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に多層配線を有する半導
体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having multilayer wiring.
従来の技術では、異なる層の配線を同一の目的で形成す
ることは少なく、形成する場合には、特開昭５９−４０
５４９号のように多数の接続孔により接続をとっている
。In the conventional technology, wiring in different layers is rarely formed for the same purpose, and when it is formed, it is
As in No. 549, connections are made through a large number of connection holes.
しかし前述した技術では、微細化が進み、配線に流れる
電流が大きくなる場合には、マイグレーション等による
断線を防止する為に、配線を太くする必要が生じ、チッ
プの面積が大きくなるという課題が生じる。又、特開昭
５９−４０５４９号のように多数の接続孔に比べ、溝型
の接続孔を使用した場合には、接続孔への配線材料のつ
きまわりが向上する。多数の接続孔の場合にはマイグレ
ーション等により接続孔の部分で断線が生じる可能性が
ある。However, with the above-mentioned technology, as miniaturization progresses and the current flowing through the wiring increases, it becomes necessary to make the wiring thicker to prevent disconnections due to migration, etc., which creates the problem of increasing the area of the chip. . Furthermore, when a groove-shaped connection hole is used, the coverage of the wiring material to the connection hole is improved compared to the case of using a large number of connection holes as in JP-A No. 59-40549. In the case of a large number of connection holes, there is a possibility that wire breakage may occur at the connection holes due to migration or the like.
本発明は、このような問題点を解決するもので、その目
的とするところは、マイグレーション等による断線を防
止し、配線幅の増大を抑制した半導体装置を提供すると
ころにある。The present invention is intended to solve these problems, and its purpose is to provide a semiconductor device that prevents disconnection due to migration and the like and suppresses increase in wiring width.
本発明の半導体装置は、多層配線を有し、異なる層の同
一の目的で形成されている配線が互いに溝型の一つの接
続孔により接続されていることを特徴とする特
〔実 施 例〕
以下、本発明について、実施例に基づき詳細に説明する
。[Example] The semiconductor device of the present invention is characterized in that it has multilayer wiring, and wirings formed for the same purpose in different layers are connected to each other by one groove-shaped connection hole. Hereinafter, the present invention will be described in detail based on examples.
第１図、第２図は、本発明の一実施例を示す平面図及び
断面図である。FIGS. 1 and 2 are a plan view and a sectional view showing an embodiment of the present invention.
まずａ）図の如く、トランジスタ等が形成されている半
導体基板１０１上に第１のＡＮ−１％５ｉ１０２を０．
５μｍスパッタ法で形成し、レジストパターンをマスク
として、前記第１のＡｌ−１％Ｓ ｔ １０２をＢＣ，
１７３、ＣＩ２等をエツチングガスとして用いたドライ
エツチング法により、エツチングし、レジストを除去し
、下層配線を形成する。次に前記第１のＡｊｌ−１％５
ｉ１０２上に層間絶縁膜として、ＣＶＤ法により５ｉＯ
ｚ１０３を０．５μｍ形成する。First, a) as shown in the figure, a first AN-1%5i102 film of 0.00.degree.
The first Al-1% S t 102 was formed by a 5 μm sputtering method using a resist pattern as a mask.
Etching is performed by a dry etching method using 173, CI2, etc. as an etching gas, the resist is removed, and a lower layer wiring is formed. Next, the first Ajl-1%5
5iO was deposited on i102 as an interlayer insulating film by CVD method.
z103 is formed to have a thickness of 0.5 μm.
次いでｂ）図の如く、レジストパターンをマスクとして
、前記５ｉ０２１０３をＣＨＦ３、ＣＦ４等をエツチン
グガスとして用いたドライエツチング法で、エツチング
し、レジストを除去し、薄型の接続孔１０４を形成する
。Then, b) as shown in the figure, using the resist pattern as a mask, the 5i02103 is etched by a dry etching method using CHF3, CF4, etc. as an etching gas, the resist is removed, and a thin connection hole 104 is formed.
次にＣ）図の如く第２のＡｌ−１％５１１０５を０．８
μｍスパッタ法で形成し、下層配線の場合と同様に、レ
ジストパターンをマスクとして、ドライエツチング法で
エツチングし、レジストを除去して、所望の配線パター
ンを上層配線として形成する。このようにして形成され
た配線は、配線の幅を広くすることなく、断面積を広く
することが可能で、マイグレーション等による断線を防
止できる配線を限られた領域内に形成することができる
。又、本発明の如く接続孔を溝型とすることにより、第
２のＡｆｉ−１％Ｓｉは、非常に良いつきまわりとなり
、接続孔の部分で断線することはない。Next, C) Add 0.8 of the second Al-1% 51105 as shown in the figure.
It is formed by the μm sputtering method, and as in the case of the lower layer wiring, etching is performed using the dry etching method using the resist pattern as a mask, the resist is removed, and a desired wiring pattern is formed as the upper layer wiring. The wiring formed in this manner can have a large cross-sectional area without increasing the width of the wiring, and can form a wiring in a limited area that can prevent disconnection due to migration or the like. Furthermore, by making the connection hole into a groove type as in the present invention, the second Afi-1%Si has a very good power distribution and will not be disconnected at the connection hole.
ここでは、下層配線、及び上層配線として、Ａｌ−１％
Ｓｉを使用したが、他に多結晶シリコン、高融点金属、
高融点金属のシリサイドが使用できる。層間絶縁膜とし
て、ここでは、５ｉｏ２を使用したが、他にＳｉ３Ｎ４
、有機系の絶縁膜等が使用できる。Here, as the lower layer wiring and upper layer wiring, Al-1%
Although Si was used, other materials such as polycrystalline silicon, high melting point metal,
Silicides of high melting point metals can be used. As the interlayer insulating film, 5io2 was used here, but Si3N4 may also be used.
, an organic insulating film, etc. can be used.
又、本発明は、第３図に示すように、３層以上の配線に
も適用が可能である。Further, the present invention can be applied to wiring of three or more layers, as shown in FIG.
本発明を適用すべき配線の領域に、他の目的で使用され
る下層配線又は、上層配線が存在する場合、それぞれ第
４図、第５図のように適用できる。When lower layer wiring or upper layer wiring used for other purposes exists in the wiring area to which the present invention is applied, the invention can be applied as shown in FIGS. 4 and 5, respectively.
上述の如く本発明によれば、異なる層の配線を一つの接
続孔により接続し、１本の配線とすることにより、配線
の幅を広げることなくマイグレーション等による断線を
防止することができる。As described above, according to the present invention, wires in different layers are connected through one contact hole to form a single wire, thereby making it possible to prevent wire breakage due to migration or the like without increasing the width of the wire.
線が存在する場合の実施例をそれぞれ示す図である。FIG. 6 is a diagram showing examples in which lines exist.
１０２書 １０３・ １０４・ １０６争 １０７・ ・半導体基板 ・第１のｌ！−１％Ｓｉ 尋ｓｉｏ。102 books 103・ 104・ 106 races 107・ ・Semiconductor substrate ・First l! -1%Si Hirosio.
・接続孔 ・第２のＡｆｌ−１９６Ｓｉ ・第２の５ｉｎ２ ・第３のＡＮ−１％Ｓｉ・Connection hole ・Second Afl-196Si ・Second 5in2 ・Third AN-1%Si
第１図（ａ）〜（ｃ）および第２図（ａ）〜（ｃ）は、
本発明の一実施例を示す図であり、第１図（ａ）〜（ｃ
）は平面図、第２図（ａ）〜（ｃ）は、それぞれ第１図
（ａ）〜（Ｃ）の断面図である。
第３図は、本発明を３層配線に適用した場合の断面図で
ある。
第４図（ａ）、（ｂ）および第５図（ａ）、（ｂ）は、
他の目的で使用される下層、上層の配量上
出願人 セイコーエプソン株式会社
代理人 弁理士 鈴 木 喜三部（他１名）寡
図
箋
ユ
■
第
菅
■Figures 1 (a) to (c) and Figures 2 (a) to (c) are
1A to 1C are diagrams showing one embodiment of the present invention.
) is a plan view, and FIGS. 2(a) to 2(c) are sectional views of FIGS. 1(a) to (C), respectively. FIG. 3 is a cross-sectional view when the present invention is applied to three-layer wiring. FIGS. 4(a), (b) and 5(a), (b) are
Assignment of lower and upper layers used for other purposes Applicant: Seiko Epson Co., Ltd. Agent Patent attorney: Kisanbe Suzuki (and 1 other person)
Claims (1)
同一のパターンで形成されている部分の配線が互いに溝
型の一つの接続孔により接続されていることを特徴とす
る半導体装置。1. A semiconductor device having multilayer wiring, characterized in that wiring in portions formed in substantially the same pattern in different layers are connected to each other by one groove-shaped connection hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7110689A JPH02249255A (en) | 1989-03-23 | 1989-03-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7110689A JPH02249255A (en) | 1989-03-23 | 1989-03-23 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02249255A true JPH02249255A (en) | 1990-10-05 |
Family
ID=13450971
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7110689A Pending JPH02249255A (en) | 1989-03-23 | 1989-03-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02249255A (en) |
-
1989
- 1989-03-23 JP JP7110689A patent/JPH02249255A/en active Pending
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