JPH02246398A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02246398A JPH02246398A JP6864389A JP6864389A JPH02246398A JP H02246398 A JPH02246398 A JP H02246398A JP 6864389 A JP6864389 A JP 6864389A JP 6864389 A JP6864389 A JP 6864389A JP H02246398 A JPH02246398 A JP H02246398A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- element substrate
- insulating layer
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 238000005530 etching Methods 0.000 claims abstract description 14
- 239000004020 conductor Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 75
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 3
- 244000228957 Ferula foetida Species 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体装置の製造方法に関し、
配線接続部の低コンタクト抵抗を実現した半導体装置を
高い再現性をもって容易に形成できる製造方法の提供を
目的とし、
表面より順に、第１の導電材料からなる素子基板、絶縁
層、支持基板が重なってなる基板の表面に、絶縁層を形
成し、該絶縁層、該素子基板を順にエツチング除去し、
該絶縁層を露出させ、コンタクト穴を形成する工程と、
該絶縁層に等方性エツチングを施して、コンタクト穴近
傍で該素子基板の裏面を露出させる工程と、該素子基板
の表面。[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device, the purpose of the present invention is to provide a manufacturing method that can easily form a semiconductor device with high reproducibility that achieves low contact resistance at a wiring connection portion, and in order from the surface, Forming an insulating layer on the surface of a substrate formed by overlapping an element substrate made of a first conductive material, an insulating layer, and a support substrate, and removing the insulating layer and the element substrate in order,
exposing the insulating layer and forming a contact hole;
A step of isotropically etching the insulating layer to expose the back surface of the device substrate near the contact hole, and a front surface of the device substrate.
側面、裏面に、第２の導電材料からなる配線層を形成す
る工程とを有して構成する。The method includes a step of forming a wiring layer made of a second conductive material on the side surfaces and the back surface.
本発明は、半導体装置の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor device.
近年、半導体装置を製造するにあたり、基板面方向に平
面的にだけ配線を行う単純な配線方法を採っていたので
は、高密度化している半導体装置に対処できなくなって
きた。そこで最近盛んに用いられるのが、素子の間を立
体的に配線しようとする所謂多層配線構造である。In recent years, when manufacturing semiconductor devices, a simple wiring method in which wiring is performed only two-dimensionally in the direction of the substrate surface has become unable to cope with the increasing density of semiconductor devices. Therefore, a so-called multilayer wiring structure, in which elements are interconnected three-dimensionally, has been widely used recently.
しかし、この多層配線構造には欠点がある。すなわちコ
ンタクトをとるべき部分、つまり第一層目の配線と第二
層目の配線とが重なる部分が、半導体デバイス自体の微
細化に伴って狭小化したために、二つの配線の接続部で
のコンタクト抵抗が大きくなるという問題が生じてきた
。However, this multilayer wiring structure has drawbacks. In other words, the area where contact should be made, that is, the area where the first layer wiring and the second layer wiring overlap, has become narrower due to the miniaturization of semiconductor devices themselves. A problem has arisen in that resistance increases.
特開昭５８−１９１４５０号公報記載の発明（多層配線
構造）は、このコンタクト抵抗の問題を改善すべくなさ
れたものである。この多層配線構造は、上層配線パター
ンのおもて面と下層配線パターンのおもて面とが単に二
次元的に接触するのではない。The invention (multilayer wiring structure) described in Japanese Patent Application Laid-Open No. 58-191450 was made to improve this problem of contact resistance. In this multilayer wiring structure, the front surface of the upper layer wiring pattern and the front surface of the lower layer wiring pattern do not simply contact two-dimensionally.
以下、第２図を参照しつつこの発明の詳細な説明する。The present invention will be described in detail below with reference to FIG.
第２図は従来の多層配線構造の断面図である。第２図中
、基板１１の表面には下層配線パターン１２と上層配線
パターン１６が形成され、再配線パターン間には眉間絶
縁膜１３が形成される。この多層配線構造では、下層配
線パターンＩ２が上層配線パターン１６に庇状に食い込
んでいるので、再配線パターンのコンタクト部分となる
この庇部では、従来どおり配線パターンのおもて面で接
触するだけでなく、側面２底面でも接触できて実質的な
コンタクト面積が広がり、このコンタクト面積の拡大に
よ、ってコンタクト抵抗は低減できるというものである
。FIG. 2 is a cross-sectional view of a conventional multilayer wiring structure. In FIG. 2, a lower layer wiring pattern 12 and an upper layer wiring pattern 16 are formed on the surface of a substrate 11, and a glabella insulating film 13 is formed between the rewiring patterns. In this multilayer wiring structure, the lower layer wiring pattern I2 digs into the upper layer wiring pattern 16 like an eave, so that at this eave part, which becomes the contact part of the rewiring pattern, only the front surface of the wiring pattern makes contact as before. Instead, contact can be made on both the side surfaces and the bottom surface, increasing the substantial contact area, and by increasing the contact area, the contact resistance can be reduced.
ところが、この従来の多層配線構造は、第２図のように
下層配線パターン１２が庇状に長く張り出した構造をし
ているので、この構造を形成するにはパターニングを幾
度も繰り返さねばならず、工程が複雑で再現性に乏しい
ものになる。However, in this conventional multilayer wiring structure, as shown in FIG. 2, the lower wiring pattern 12 has a long overhanging structure, so patterning must be repeated many times to form this structure. The process becomes complicated and has poor reproducibility.
以上のように、配線接続部での低いコンタクト抵抗を実
現した従来公知の多層配線構造は、再現性に乏しいもの
である。As described above, the conventionally known multilayer wiring structure that achieves low contact resistance at wiring connection portions has poor reproducibility.
本発明は、このような従来技術の課題に鑑みてなされた
ものであり、配線接続部の低コンタクト抵抗を実現した
半導体装置を高い再現性をもって容易に形成できる製造
方法の提供を目的とする。The present invention has been made in view of the problems of the prior art, and an object of the present invention is to provide a manufacturing method that can easily form a semiconductor device with high reproducibility that achieves low contact resistance at a wiring connection portion.
本発明では、前記課題を解決するための手段として、表
面より順に、第１の導電材料からなる素子基板、絶縁層
、支持基板が重なってなる基板の表面に、絶縁層を形成
し、該絶縁層、酸素子基板を順にエツチング除去し、該
絶縁層を露出させ、コンタクト穴を形成する工程と、該
絶縁層に等方性エツチングを施して、コンタクト穴近傍
で該素子基板の裏面を露出させる工程と、該素子基板の
表面、側面、裏面に、第２の導電材料からなる配線層を
形成する工程とを有する。In the present invention, as a means for solving the above problem, an insulating layer is formed on the surface of a substrate formed by overlapping an element substrate made of a first conductive material, an insulating layer, and a support substrate in order from the surface, and a step of sequentially etching and removing the insulating layer and the oxygen element substrate to expose the insulating layer and forming a contact hole, and isotropically etching the insulating layer to expose the back surface of the element substrate near the contact hole. and a step of forming a wiring layer made of a second conductive material on the front surface, side surface, and back surface of the element substrate.
本発明では、シリコン等の導電層でＳｉＯ□等の絶縁層
をサンドインチした構造の基板を用いる。このような基
板としては、例えば入手も製作も容易なＳ ＯＩ （Ｓ
ｉｌｉｃｏｎ Ｏｎ Ｉｎ５ｕｌａｔｏｒ）基板が知ら
れている。この基板の表面側導電層に異方性エツチング
を施して開孔し、下層である絶縁層を露出させる。この
絶縁層に開孔部より等方性エツチングを施せば、表面側
導電層はその上面、裏面、側面で露出する。この三面と
コンタクトを取ることは、ＣＶＤ法を用いてシリコン層
等を成長することで容易に行える。The present invention uses a substrate having a structure in which an insulating layer such as SiO□ is sandwiched between a conductive layer such as silicon. As such a substrate, for example, SOI (S
ilicon On In5ulator) substrates are known. The conductive layer on the surface side of this substrate is anisotropically etched to open a hole and expose the underlying insulating layer. If this insulating layer is isotropically etched through the opening, the front conductive layer will be exposed on its top, back, and side surfaces. Contact with these three surfaces can be easily achieved by growing a silicon layer or the like using the CVD method.
本発明によれば、前記実施例に比しても温かに再現性良
好であり、また確実かつ容易に三次元的に多層配ｖＡＮ
のコンタクトが可能になる。According to the present invention, the reproducibility is excellent compared to the above-mentioned embodiments, and the multi-layered VAN can be reliably and easily arranged in three dimensions.
contact becomes possible.
以下、本発明の多層配線構造を有した半導体装置の製造
方法を、第１図を参照しつつ一実施例により説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device having a multilayer wiring structure according to the present invention will be described below by way of an example with reference to FIG.
第１図は本発明の一実施例に則した半導体装置の製造方
法の工程説明図である。図中、１は基板。FIG. 1 is a process explanatory diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. In the figure, 1 is the board.
２は５ｉＯｚ層、３は素子基板、４は５ｉｎｔ層、５は
支持基＋Ｎ、 ６１．６２．６３はレジスト ９はコン
タクト穴、１０は配線層である。2 is a 5iOz layer, 3 is an element substrate, 4 is a 5int layer, 5 is a support base +N, 61, 62, 63 are resists, 9 is a contact hole, and 10 is a wiring layer.
以下の工程（ａ）、（ｂ）では、Ｓｉｎｇが埋められ素
子間絶縁分離するための穴をつくるためにＳｔＯ□層２
．素子基板３を順に開孔する。In the following steps (a) and (b), the StO
．． Holes are sequentially opened in the element substrate 3.
第１図（ａ）参照
先ず支持基板５．ＳｉＯ，層４６素子基板３が順に積層
したＳ ＯＩ （Ｓｉｌｉｃｏｎ Ｏｎ Ｉｎ５ｕｌａ
ｔｏｒ）基板ｌを用意する。各層の厚さは、それぞれ支
持基板５が０．５〜１ ａｍ、 ＳｉＯ２層４が２〜３
ｕｍ、素子基板３が１μｍである。このＳｏｌ基板工の
表面にＳｉＯ□層２を１〜２μｍＣＶＤ成長する。この
後、Ｓｉ０２層２の表面に開孔部を有するレジスト６１
を形成して、まずＣＦ４ （四フッ化炭素）のＲＩ
Ｅ （Ｒｅａｃｔｉｖｅ Ｉｏｎ Ｂｔｃｈｉｎｇ）で
素子基板３が露出するまでＳｉｎｇ層２を食刻除去する
。Refer to FIG. 1(a). First, support substrate 5. SOI (Silicon On In5ula) in which SiO, layer 46 and element substrate 3 are laminated in order.
(tor) Prepare a substrate l. The thickness of each layer is 0.5 to 1 am for the supporting substrate 5, and 2 to 3 am for the SiO2 layer 4.
um, and the element substrate 3 is 1 μm. A SiO□ layer 2 is grown by CVD to a thickness of 1 to 2 μm on the surface of this Sol substrate. After this, a resist 61 having openings on the surface of the Si02 layer 2 is applied.
First, RI of CF4 (carbon tetrafluoride)
The Sing layer 2 is etched away using E (Reactive Ion Butching) until the element substrate 3 is exposed.
第１図（ｂ）参照
工程（ａ）でできた開孔部で露出した素子基板３の表面
を、ＳｉＯ□層４が露出するまでＣｂ （塩素） ＋
ＳＦ＆のＲＩ Ｅ （Ｒｅａｃｔｉｖｅ Ｉｏｎ Ｅｔ
ｃｈｉｎｇ）で除去する。Refer to FIG. 1(b) The surface of the element substrate 3 exposed through the opening made in step (a) is heated with Cb (chlorine) + until the SiO□ layer 4 is exposed.
SF & RI E (Reactive Ion Et
(ching).
第１図（Ｃ）参照
続イテ、まずレジスト６１を０． ＲＩ Ｅ （Ｒｅａ
ｃｔｉｖｅＪｏｎ Ｅｔｃｈｉｎｇ）により剥離し、次
いで表面の絶縁層２を除去すべく例えばＨＦ （フッ酸
）等の工１．チャントを基板面に作用させる。しかしこ
の工程で同時に絶縁層４も等方的にエツチングされる。Referring to FIG. 1(C), first, the resist 61 is set to 0. RI E (Rea
Then, in order to remove the insulating layer 2 on the surface, a process such as HF (hydrofluoric acid) is applied. Apply a chant to the substrate surface. However, in this step, the insulating layer 4 is also etched isotropically.
この後、素子基板３の表面にｎ″層３１を形成するため
に、ｎ型不純物イオンとしてＡｓ” （ヒ素）２Ｐ。After that, in order to form an n'' layer 31 on the surface of the element substrate 3, As'' (arsenic) 2P is used as an n-type impurity ion.
リン）をドーズＩＩ Ｘｌ０１４ｃｍ＋−”、 ５０〜
７０ｋｅＶで注入する。Dose II Xl014cm+-", 50~
Inject at 70 keV.
第１図（ｄ）参照
この後基板の表面に、−様に５ｊＯＪＪ４５を厚さ２０
００〜４０００人程度ＣＶＤで形変形る。形成されたＳ
ｉＯ７層４５のうち、素子分離のために残さねばならな
い部分の表面には、レジスト６２を厚さ１μｍ〜２μｍ
形成する。Refer to Fig. 1(d). After that, apply 5jOJJ45 to a thickness of 20 mm on the surface of the substrate.
Approximately 00 to 4000 people are transformed by CVD. formed S
A resist 62 is applied to a thickness of 1 μm to 2 μm on the surface of the portion of the iO7 layer 45 that must be left for element isolation.
Form.
第１図（ｅ）参照
前工程で形成されたレジスト６２をマスクとして、Ｓｉ
Ｏ２層４５をフッ素系エツチングガスによりＲＩＥ（Ｒ
ｅａｃｔｉｖｅ Ｉｏｎ Ｅｔｃｈｉｎｇ）する、この
後、Ｓｉ０２層４５の表面に形成されたレジスト６２を
、まず０ｔＲＩＥ（Ｒｅａｃｔｉｖｅ Ｉｏｎ Ｅｔｃ
ｈｉｎｇ）により剥離する。Refer to FIG. 1(e) Using the resist 62 formed in the previous step as a mask, Si
The O2 layer 45 is subjected to RIE (RIE) using a fluorine-based etching gas.
After that, the resist 62 formed on the surface of the Si02 layer 45 is first subjected to 0tRIE (Reactive Ion Etching).
peel off by hing).
以下の工程（ｆ）〜（ｋ）では、分離された素子領域表
面にＭＯＳデバイスを形成する。このＭＯＳデバイスの
ゲート電極上面、側面ともＳｉＯ□層で覆って周囲に形
成される配線層との絶縁を確保する。In the following steps (f) to (k), MOS devices are formed on the surfaces of the separated element regions. Both the top and side surfaces of the gate electrode of this MOS device are covered with a SiO□ layer to ensure insulation from the surrounding wiring layers.
それでは、以下順に詳述する。Now, the details will be explained in order below.
第１図ＣＩ）参照
まず、熱酸化して厚さ２００Å以下のゲート酸化膜４６
を基板面に一様に形成する。さらに、基板の全面にゲー
ト電極となる多結晶シリコン層７を厚さ２０００人〜４
０００人程度変形ＶＤ形成する。さらに、厚さ２０００
人〜３０００人のＳ ｉ Ｏｚ ｊｉｉ７４をＣＶＤで
一様に形成する。このＳｉＯ□層７４は、ゲート電極の
上面を覆う絶縁膜となる。続いて、後にゲート部分での
エツチングストッパとなるＳｉＮ （窒化硅素）層７
ｎを厚さ５００〜１０００人にＣＶＤ形成する。このＳ
ｉＯ１層７４のゲートとなる表面にはレジスト６３を厚
さ１μｍ〜２μｍ形成する。Refer to FIG. 1 CI) First, a gate oxide film 46 with a thickness of 200 Å or less is thermally oxidized.
is formed uniformly on the substrate surface. Furthermore, a polycrystalline silicon layer 7 that will become a gate electrode is formed on the entire surface of the substrate to a thickness of 2,000 to 400 nm.
About 000 people will form a modified VD. Furthermore, the thickness is 2000
~3000 S i Oz jii 74 are uniformly formed by CVD. This SiO□ layer 74 becomes an insulating film covering the upper surface of the gate electrode. Next, a SiN (silicon nitride) layer 7 that will later become an etching stopper at the gate portion is formed.
CVD to a thickness of 500 to 1000 mm. This S
A resist 63 with a thickness of 1 μm to 2 μm is formed on the surface of the iO1 layer 74 that will become the gate.
第１図（ｇ）参照
前工程でゲートとなる部分の表面に形成したレジスト６
３によって、ｓｉｓ （窒化硅素）層？ｎ、 ５ｉＯ
ｚ７４、多結晶シリコン層７を順にＲＩ Ｅ（Ｒｅａｃ
ｔｉｖｅｔｏｎ Ｅｔｃｈｉｎｇ） シて、ゲート部分
以外を食刻除去する。Refer to Fig. 1(g) Resist 6 formed on the surface of the part that will become the gate in the previous step
By 3, the sis (silicon nitride) layer? n, 5iO
z74 and polycrystalline silicon layer 7 in this order.
(Tiveton Etching) Then, remove the etching except for the gate part.
第１図（ｈ）参照
レジスト６３剥離後、基板の全面に厚さ１０００人程度
変形ｉＯ□層８４をＣＶＤ形成する。このＳｉｎ、層８
４は後にゲート電極のサイドウオールとなるものである
。After removing the resist 63 (see FIG. 1(h)), a deformed iO□ layer 84 having a thickness of about 1000 layers is formed on the entire surface of the substrate by CVD. This Sin, layer 8
4, which will later become a sidewall of the gate electrode.
第１図（ｉ）参照
前工程で基板面に形成したＳｉＯ□層８４は、フッ素系
ガスのＲＩ Ｅ （Ｒｅａｃｔｉｖｅ ｔｏｎ Ｅｔｃ
ｈｉｎｇ）により食刻除去する。但しこの工程では５ｉ
Ｎ（窒化硅素）層７ｎがエツチングストッパとして作用
し、ゲート電極側面にはサイドウオールとなって５ｉＣ
ｈ層８４が残る。続いて基板の全面に、ＳｉＮ （窒
化硅素）層８ｎを厚さ５００〜１０００人程度ＣＶＤ形
変形る。The SiO□ layer 84 formed on the substrate surface in the previous step (see FIG. 1(i)) is coated with fluorine-based gas RI E (Reactive ton Etc.
etching by hing). However, in this process, 5i
The N (silicon nitride) layer 7n acts as an etching stopper, and the 5iC layer forms a sidewall on the side surface of the gate electrode.
The h layer 84 remains. Subsequently, a SiN (silicon nitride) layer 8n is deformed to a thickness of about 500 to 1000 layers by CVD over the entire surface of the substrate.
第１図（ｊ）参照
ゲート電極表面以外のＳｉＮ層８ｎ、 ＳｉＯ□層４６
を食刻除去する。次いで、まず基板表面をマスキング後
、ｃｐ、＋ｏｉのＲＩ Ｅ （Ｒｅａｃｔｉｖｅ Ｉｏ
ｎ Ｅｔｃｈｉｎｇ）で素子基板３に異方性エツチング
を施し、コンタクト穴９を形成する。さらに基板表面を
ＨＦ（フッ酸）を含むエツチング液にさらして、コンタ
クト穴９底部のｓｉｏｇｉｉ４を等方的に食刻除去し、
素子基板３の裏面を露出させる。FIG. 1(j) SiN layer 8n and SiO□ layer 46 other than the reference gate electrode surface
etching away. Next, after first masking the substrate surface, cp, +oi RI E (Reactive Io
Then, the element substrate 3 is anisotropically etched to form a contact hole 9. Furthermore, the surface of the substrate is exposed to an etching solution containing HF (hydrofluoric acid), and the siogii 4 at the bottom of the contact hole 9 is isotropically etched away.
The back surface of the element substrate 3 is exposed.
第１図（ｋ）参照
配線１ｉｆＩＯを例えばポリシリコンでＣＶＤ形成する
。FIG. 1(k) A reference wiring 1ifIO is formed by CVD using polysilicon, for example.
以上の工程を経て、配線コンタクト抵抗増大の問題を容
易に解決した半導体装置が完成できた。Through the above steps, a semiconductor device that easily solved the problem of increased wiring contact resistance was completed.
なお本発明は、開示したこの一実施例に限定されること
なく、多数の変形が可能である。Note that the present invention is not limited to this one embodiment disclosed, but can be modified in many ways.
本発明の製造方法によれば、配線コンタクト抵抗増大の
問題を解決した半導体装置を容易に実現できるという効
果がある。According to the manufacturing method of the present invention, it is possible to easily realize a semiconductor device that solves the problem of increased wiring contact resistance.
第１図は本発明の一実施例に則した半導体装置の製造工
程図、第２図は従来の多層配線構造の断面図である。
図中、
１・・・基板、２・・・絶縁層（ＳｉＯｘ層）、３・・
・素子基板。
３１・・・ｎ土層、４・・・絶縁膜（Ｓｉ０２） 、
４５．４６・・・ＳｉＯｘ層。
５・・・支持基板（絶縁物基板） 、 ６１．６２．６
３・・・レジスト、７・・・多結晶シリコン層、７４・
・・Ｓｉｎ、層、 ７ｎ・・・ＳｉＮ層、８４・・・Ｓ
ｉＯ□層、 ８ｎ・・・ＳｉＮ層、９・・・コンタクト
穴、 １０・・・配線層（ポリシリコン層）、１１・・
・基板。
１２・・・下層配線パターン、１３・・・層間絶縁膜、
１６・・・上層配線パターンである。FIG. 1 is a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional multilayer wiring structure. In the figure, 1...substrate, 2...insulating layer (SiOx layer), 3...
・Element substrate. 31...n soil layer, 4...insulating film (Si02),
45.46...SiOx layer. 5... Support substrate (insulator substrate), 61.62.6
3... Resist, 7... Polycrystalline silicon layer, 74...
...Sin layer, 7n...SiN layer, 84...S
iO□ layer, 8n...SiN layer, 9... contact hole, 10... wiring layer (polysilicon layer), 11...
·substrate. 12... Lower layer wiring pattern, 13... Interlayer insulating film,
16... Upper layer wiring pattern.
Claims (1)
），絶縁層（４），支持基板（５）が重なってなる基板
（１）の表面に、絶縁層（２）を形成し、該絶縁層（２
），該素子基板（３）を順にエッチング除去し、該絶縁
層（４）を露出させ、コンタクト穴（９）を形成する工
程と、 該絶縁層（４）に等方性エッチングを施して、コンタク
ト穴（９）近傍で該素子基板（３）の裏面を露出させる
工程と、 該素子基板（３）の表面，側面，裏面に、第２の導電材
料からなる配線層（１０）を形成する工程とを有する半
導体装置の製造方法。[Claims] In order from the surface, element substrates (3
), an insulating layer (4), and a supporting substrate (5) are formed on the surface of the substrate (1), and an insulating layer (2) is formed on the surface of the substrate (1).
), sequentially etching away the element substrate (3), exposing the insulating layer (4), and forming a contact hole (9); performing isotropic etching on the insulating layer (4); A step of exposing the back surface of the element substrate (3) near the contact hole (9), and forming a wiring layer (10) made of a second conductive material on the front, side, and back surfaces of the element substrate (3). A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6864389A JPH02246398A (en) | 1989-03-20 | 1989-03-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6864389A JPH02246398A (en) | 1989-03-20 | 1989-03-20 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02246398A true JPH02246398A (en) | 1990-10-02 |
Family
ID=13379610
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6864389A Pending JPH02246398A (en) | 1989-03-20 | 1989-03-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02246398A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001057930A1 (en) * | 2000-02-02 | 2001-08-09 | Hitachi, Ltd. | Semiconductor device and its manufacturing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6085572A (en) * | 1983-10-18 | 1985-05-15 | Semiconductor Energy Lab Co Ltd | Manufacture of photoelectric conversion semiconductor device |
| JPS62147759A (en) * | 1985-12-23 | 1987-07-01 | Hitachi Ltd | Manufacture of semiconductor device |
-
1989
- 1989-03-20 JP JP6864389A patent/JPH02246398A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6085572A (en) * | 1983-10-18 | 1985-05-15 | Semiconductor Energy Lab Co Ltd | Manufacture of photoelectric conversion semiconductor device |
| JPS62147759A (en) * | 1985-12-23 | 1987-07-01 | Hitachi Ltd | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001057930A1 (en) * | 2000-02-02 | 2001-08-09 | Hitachi, Ltd. | Semiconductor device and its manufacturing method |
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