JPH02237206A - Amplifier - Google Patents
AmplifierInfo
- Publication number
- JPH02237206A JPH02237206A JP1057025A JP5702589A JPH02237206A JP H02237206 A JPH02237206 A JP H02237206A JP 1057025 A JP1057025 A JP 1057025A JP 5702589 A JP5702589 A JP 5702589A JP H02237206 A JPH02237206 A JP H02237206A
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- voltage gain
- input terminal
- resistor
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 230000003321 amplification Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000011144 upstream manufacturing Methods 0.000 description 1
Landscapes
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は非反転増幅器と反転増幅器の出力間より大出力
を得ることを目的とした、いわゆる、バランスド，トラ
ンスフォーマレス形式（以下ＢＴＬと記す。）の増幅器
に関するものである。[Detailed Description of the Invention] Industrial Application Field The present invention is a so-called balanced, transformerless type (hereinafter referred to as BTL), which aims to obtain a large output between the outputs of a non-inverting amplifier and an inverting amplifier. This relates to an amplifier.
従来の技術
近年、大出力，高音質，容量の削減を目的として、ＢＴ
Ｌ増幅器が利用されている。Conventional technology In recent years, BT
L amplifier is used.
以下に従来のＢＴＬ増幅器について説明する。A conventional BTL amplifier will be explained below.
第２図は従来のＢＴＬ増幅器の構成図を示すものである
。第２図において、２１は第１の増幅器で、入力信号を
非反転増幅する。２２と２３は帰還抵抗で、第１の増幅
器２１の電圧利得を決めている。２４は第２の増幅器で
、入力信号を反転増幅する。２５と２６は帰還抵抗で、
第２の増幅器の電圧利得を決めている。２７は基準電圧
源である。２８は出力負荷抵抗である。FIG. 2 shows a block diagram of a conventional BTL amplifier. In FIG. 2, 21 is a first amplifier that non-inverts and amplifies the input signal. Feedback resistors 22 and 23 determine the voltage gain of the first amplifier 21. A second amplifier 24 inverts and amplifies the input signal. 25 and 26 are feedback resistors,
The voltage gain of the second amplifier is determined. 27 is a reference voltage source. 28 is an output load resistance.
まず、入力信号は、第１の増幅器２１の正入力端子と第
２の増幅器２４の負入力端子との間に印加され、それぞ
れ、第１の増幅器２１では、帰還抵抗２２．２３で決め
られた電圧利得で非反転増幅され、第２の増幅器２４で
は、帰還抵抗２５，２６で決められた電圧利得で反転増
幅され、第１，第２の増幅器２１，２４は、同じ電圧利
得になるように構成されており、第１，第２の増幅器２
１．２４間の出力信号は出力負荷抵抗２８の両端に印加
される。したがって、出力負荷抵抗′２８に、検出され
る出力信号は、それぞれの帰還抵抗で決められた電圧利
得の２倍の電圧利得で入力信号が増幅され、最大出力は
１つの増幅器で構成された場合より２倍の最大出力とな
る。First, an input signal is applied between the positive input terminal of the first amplifier 21 and the negative input terminal of the second amplifier 24. The second amplifier 24 performs non-inverting amplification with a voltage gain determined by feedback resistors 25 and 26, and the first and second amplifiers 21 and 24 are configured to have the same voltage gain. The first and second amplifiers 2
An output signal between 1.24 and 1.24 is applied across the output load resistor 28. Therefore, the output signal detected by the output load resistor '28 is amplified by the input signal with a voltage gain twice the voltage gain determined by each feedback resistor, and the maximum output is when configured with one amplifier. The maximum output is twice as high.
発明が解決しようとする課題
しかしながら上記の従来の構成では、第１，第２の各増
幅器が各々直流電圧利得を持っているため、入力端子と
基準電圧源との電位差がＢＴＬ増幅器の電位利得だけ増
幅され、負荷抵抗２８の両端に大きな電位差が生じると
いう欠点を有していた。Problems to be Solved by the Invention However, in the above conventional configuration, since each of the first and second amplifiers has a DC voltage gain, the potential difference between the input terminal and the reference voltage source is only the potential gain of the BTL amplifier. This has the drawback of being amplified, resulting in a large potential difference across the load resistor 28.
本発明は上記従来の課題を解決するもので、負荷抵抗の
両端の電位差を小さ《するＢＴＬ増幅器を提供すること
を目的とする。The present invention solves the above-mentioned conventional problems, and aims to provide a BTL amplifier that reduces the potential difference between both ends of a load resistor.
課題を解決するための手段
この目的を達成するために、本発明の増幅器は、出力が
負荷抵抗に接続されている非反転増幅器と反転増幅器と
、前記２つの贈幅器の前段に配置された直流電圧利得を
持たない増幅器とから構成されている。Means for Solving the Problems To achieve this object, the amplifier of the present invention comprises a non-inverting amplifier and an inverting amplifier, the outputs of which are connected to a load resistor, and which are arranged upstream of the two amplifiers. It consists of an amplifier with no DC voltage gain.
作用
この構成によって、前段の直流電圧利得を持たない増幅
器の電圧利得だけ、次段の非反転増幅器と反転幅器の電
圧利得を下げることができ、同時に直流電圧利得も下げ
ることができる。よって、入力端子と基準電圧源との電
位差が直流電圧利得によって増幅されて生じる負荷抵抗
両端の電位差を、前段め増幅器の電圧利得の比率だけ、
小さくすることができる。Effect: With this configuration, it is possible to reduce the voltage gain of the non-inverting amplifier and inverting amplifier in the next stage by the voltage gain of the preceding stage amplifier having no DC voltage gain, and at the same time, the DC voltage gain can also be lowered. Therefore, the potential difference between both ends of the load resistor, which is generated when the potential difference between the input terminal and the reference voltage source is amplified by the DC voltage gain, is reduced by the ratio of the voltage gain of the previous stage amplifier.
Can be made smaller.
実施例
以下本発明の一実施例について、図面を参照しながら説
明する。EXAMPLE An example of the present invention will be described below with reference to the drawings.
第１図は本発明実施例のＢＴＬ増幅器の構成図である。FIG. 1 is a block diagram of a BTL amplifier according to an embodiment of the present invention.
第１図において、１は第１の増幅器、２は抵抗、３は抵
抗、４は容量、５は第２の増幅器、６は抵抗、７は第３
の増幅器、８は抵抗、９は基準電圧源、１０は抵抗、１
１は抵抗、１２は負荷抵抗である。このように構成され
たＢＴＬ増幅回路について、次に、その動作を説明する
。In FIG. 1, 1 is a first amplifier, 2 is a resistor, 3 is a resistor, 4 is a capacitor, 5 is a second amplifier, 6 is a resistor, and 7 is a third
amplifier, 8 is a resistor, 9 is a reference voltage source, 10 is a resistor, 1
1 is a resistance, and 12 is a load resistance. Next, the operation of the BTL amplifier circuit configured as described above will be explained.
まず、入力信号は、第１の増幅器１の正入力端子に入力
端子に入力され、帰還抵抗２，３で決められた電圧利得
で増幅され、第１の増幅器１の出力端子より出力される
。第１の増幅器１より出力された信号は、第２の増幅器
５の正入力端子と第３の増幅器７の負入力端子に印加さ
れ、それぞれ、第２の増幅器５では、帰還抵抗８，１０
で決められた電圧利得で非反転増幅され、第３の増幅器
７では帰還抵抗６，１１で決められた電圧利得で反転増
幅され、第２，第３の各増幅器５，７は、同じ電圧利得
になるように構成されており、第２と第３の増幅器の出
力信号は出力負荷抵抗１２の両端に印加され、出力負荷
抵抗８に検出される出力信号は、帰還抵抗で決められた
電圧利得の２倍の電圧利得で入力信号が増幅され、最大
出力は１つの増幅器で構成された場合より２倍の最大出
力となる。First, an input signal is input to the positive input terminal of the first amplifier 1, is amplified with a voltage gain determined by the feedback resistors 2 and 3, and is output from the output terminal of the first amplifier 1. The signal output from the first amplifier 1 is applied to the positive input terminal of the second amplifier 5 and the negative input terminal of the third amplifier 7.
The third amplifier 7 performs non-inverting amplification with a voltage gain determined by the feedback resistors 6 and 11, and the second and third amplifiers 5 and 7 each have the same voltage gain. The output signals of the second and third amplifiers are applied across the output load resistor 12, and the output signal detected by the output load resistor 8 has a voltage gain determined by the feedback resistor. The input signal is amplified with a voltage gain twice that of , and the maximum output is twice that of the case where the amplifier is configured with one amplifier.
以上のように、本実施例によれば、出力が負荷抵抗に接
続されている非反転増幅器と反転増幅器との前段に直流
電圧利得を持たない増幅器を設けることにより、入力端
子と基準電圧源との電位差が直流電圧利得によって増幅
されて生じる負荷抵抗両端の電位差を、前段の増幅器の
電位利得の比率だけ、小さ《することができる。As described above, according to this embodiment, by providing an amplifier having no DC voltage gain in front of a non-inverting amplifier and an inverting amplifier whose outputs are connected to a load resistor, the input terminal and the reference voltage source can be connected to each other. The potential difference across the load resistor, which is generated when the potential difference is amplified by the DC voltage gain, can be reduced by the ratio of the potential gain of the preceding stage amplifier.
発明の効果
以上のように本発明によれば、出力が負荷抵抗に接続さ
れている非反転増幅器と反転増幅器の前段に直流電圧利
得を持たない増幅器を設けることにより、入力端子と基
準電圧源との電位差が直流電圧利得によって増幅されて
生じる負荷抵抗両端の電位差を、前段の増幅器の電圧利
得の比率だけ、小さ《することができ、優れたＢＴＬ増
幅器を実現できる。Effects of the Invention As described above, according to the present invention, by providing an amplifier having no DC voltage gain before a non-inverting amplifier and an inverting amplifier whose outputs are connected to a load resistor, the input terminal and the reference voltage source can be connected to each other. The potential difference across the load resistor, which is generated when the potential difference is amplified by the DC voltage gain, can be reduced by the ratio of the voltage gain of the preceding stage amplifier, making it possible to realize an excellent BTL amplifier.
第１図は本発明の実施例のＢ Ｔ Ｌ増幅器の構成図、
第２図は従来のＢＴＬ増幅器の構成図である。
■・・・・・・増幅器、２・・・・・・抵抗、３・・・
・・・抵抗、４・・・・・・容量、５・・・・・・増幅
器、６・・・・・・抵抗、７・・・・・・増幅器、８・
・・・・・抵抗、９・・・・・・基準電圧源、１０・・
・・・・抵抗、１１・・・・・・抵抗、１２・・・・・
・負荷抵抗、２１・・・・・・増幅器、２２・・・・・
・抵抗、２３・・・・・・抵抗、２４・・・・・・増幅
器、２５・・・・・・抵抗、２６・・・・・・抵抗、２
７・・・・・・基準電圧源、２８・・・・・・負荷抵抗
。FIG. 1 is a configuration diagram of a BTL amplifier according to an embodiment of the present invention,
FIG. 2 is a block diagram of a conventional BTL amplifier. ■...Amplifier, 2...Resistor, 3...
...Resistance, 4...Capacitance, 5...Amplifier, 6...Resistance, 7...Amplifier, 8.
...Resistance, 9...Reference voltage source, 10...
...Resistance, 11...Resistance, 12...
・Load resistance, 21...Amplifier, 22...
・Resistor, 23... Resistor, 24... Amplifier, 25... Resistor, 26... Resistor, 2
7...Reference voltage source, 28...Load resistance.
Claims (1)
記第１の増幅器の負入力端子およびその出力端子の間に
、帰還抵抗を接続し、前記第１の増幅器の負入力端子と
接地との間に、抵抗および容量を直列に接続し、前記第
１の増幅器の出力端子を、第２の増幅器の正入力端子と
、抵抗を通って第３の増幅器の負入力端子に接続し、前
記第２の増幅器の負入力端子およびその出力端子の間に
、帰還抵抗を接続し、前記第２の増幅器の負入力端子と
、基準電圧源との間に、抵抗を接続し、前記第３の増幅
器の正入力端子を前記基準電圧源に接続し、前記第３の
増幅器の負入力端子およびその出力端子の間に、帰還抵
抗を接続し、前記第２、第３の各増幅器の両出力端子間
に、負荷抵抗を接続した増幅器。The positive input terminal of the first amplifier is used as a signal input terminal, a feedback resistor is connected between the negative input terminal of the first amplifier and its output terminal, and the negative input terminal of the first amplifier is connected to ground. between, a resistor and a capacitor are connected in series, and the output terminal of the first amplifier is connected to the positive input terminal of the second amplifier and the negative input terminal of the third amplifier through the resistor; A feedback resistor is connected between the negative input terminal of the second amplifier and its output terminal, a resistor is connected between the negative input terminal of the second amplifier and the reference voltage source, and the third A positive input terminal of the amplifier is connected to the reference voltage source, a feedback resistor is connected between the negative input terminal of the third amplifier and its output terminal, and both output terminals of each of the second and third amplifiers are connected. An amplifier with a load resistor connected between.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1057025A JP2507029B2 (en) | 1989-03-09 | 1989-03-09 | amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1057025A JP2507029B2 (en) | 1989-03-09 | 1989-03-09 | amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02237206A true JPH02237206A (en) | 1990-09-19 |
| JP2507029B2 JP2507029B2 (en) | 1996-06-12 |
Family
ID=13043892
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1057025A Expired - Fee Related JP2507029B2 (en) | 1989-03-09 | 1989-03-09 | amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2507029B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103246306A (en) * | 2013-04-11 | 2013-08-14 | 刘雄 | High-precision three-port chip |
-
1989
- 1989-03-09 JP JP1057025A patent/JP2507029B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103246306A (en) * | 2013-04-11 | 2013-08-14 | 刘雄 | High-precision three-port chip |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2507029B2 (en) | 1996-06-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |