JPH0219974Y2 - - Google Patents
Info
- Publication number
- JPH0219974Y2 JPH0219974Y2 JP1979175925U JP17592579U JPH0219974Y2 JP H0219974 Y2 JPH0219974 Y2 JP H0219974Y2 JP 1979175925 U JP1979175925 U JP 1979175925U JP 17592579 U JP17592579 U JP 17592579U JP H0219974 Y2 JPH0219974 Y2 JP H0219974Y2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- electrode
- contact
- ring
- compensating plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 238000003466 welding Methods 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 claims 5
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Thyristors (AREA)
Description
【考案の詳細な説明】
この考案は平形サイリスタなどの半導体装置に
関し、特に半導体素子とこれに接触する主電極と
の位置決め構造に係わるものである。[Detailed Description of the Invention] This invention relates to a semiconductor device such as a flat thyristor, and particularly relates to a positioning structure between a semiconductor element and a main electrode in contact with the semiconductor element.
従来の平形サイリスタの構造を第1図に示して
ある。この第1図において、1は半導体素子であ
つて、PNPN構造の半導体基体を第1電極とな
るモリブデン円板にロー付けすると共に、表面側
にアルミ蒸着などで第2電極および第3(ゲート)
電極を形成させ、かつジヤンクシヨンが露出する
周辺部を安定化処理してある。また2はアルミセ
ラミツクからなる絶縁筒体であつて、その一方の
端面には前記第1電極に接してこれを位置決めし
得るようにした第1主電極となる金属薄板3が、
他方の端面には溶接リング4が、かつ筒体中程に
はゲートパイプ5が各々にロー付けされている。 The structure of a conventional flat thyristor is shown in FIG. In FIG. 1, numeral 1 is a semiconductor element, in which a semiconductor substrate with a PNPN structure is brazed to a molybdenum disk serving as a first electrode, and a second electrode and a third (gate) are formed by aluminum vapor deposition on the surface side.
Electrodes are formed and the periphery where the junction is exposed is stabilized. Reference numeral 2 denotes an insulating cylindrical body made of aluminum ceramic, and on one end surface thereof, a thin metal plate 3 serving as a first main electrode is arranged in contact with the first electrode so as to position it.
A welding ring 4 is brazed to the other end face, and a gate pipe 5 is brazed to the middle of the cylinder.
そしてまた6は前記絶縁筒体2の内側に嵌入さ
れるガイドリング、7はこのガイドリング6によ
り位置決めされて、前記第2電極に接する熱補償
板、8はこの熱補償板7に嵌合されるゲートリン
グ、9は一端部を前記ゲートパイプ5に嵌挿さ
せ、他端を前記ゲートリング8に挿通位置決めし
て第3電極に接圧させたゲートスプリング、10
はこのゲートスプリング9に挿通した絶縁チユー
ブであり、さらに11は前記ゲートスプリング9
を絶縁チユーブ10の被覆部分で受入れると共
に、一端部を前記ガイドリング6に位置決めして
熱補償板7に接した金属ブロツク、12は金属ブ
ロツク11の他端部に接して、これを位置決めし
得るようにした第2主電極となる金属薄板であつ
て、前記溶接リング4と溶接される。 Further, 6 is a guide ring fitted inside the insulating cylinder 2, 7 is a heat compensating plate positioned by this guide ring 6 and in contact with the second electrode, and 8 is fitted to this heat compensating plate 7. A gate ring 9 has one end fitted into the gate pipe 5, and a gate spring 10 whose other end is inserted and positioned through the gate ring 8 and brought into contact with a third electrode.
11 is an insulating tube inserted into the gate spring 9, and 11 is an insulating tube inserted into the gate spring 9.
is received by the covered portion of the insulating tube 10, and one end thereof is positioned in the guide ring 6 and is in contact with the heat compensating plate 7, and the metal block 12 is in contact with the other end of the metal block 11 and can be positioned. It is a thin metal plate that becomes the second main electrode, and is welded to the welding ring 4.
しかして前記従来構成の平形サイリスタを組み
立てるのには、まず前記半導体素子1を絶縁筒体
2内に挿入させて、その第1電極を第1主電極と
なる金属薄板3の内面に位置決め接触させた上
で、ガイドリング6、熱補償板7およびゲートリ
ング8を各々所定通りにセツトさせ、ついで絶縁
チユーブ10を被覆させたゲートスプリング9を
配して、その一端部をゲートパイプ5に嵌挿さ
せ、かつ他端をゲートリング8を通して第3電極
に接圧させ、さらに金属ブロツク11を前記熱補
償板7を介して第2電極に接触させたのち、この
金属ブロツク11に第2主電極となる金属薄板1
2をセツトさせ、その後、この金属薄板12と絶
縁筒体2の溶接リング4とを、各外周部で溶接し
て取付け、かつゲートパイプ5から装置内部の排
気を行なつて、代わりに不活性ガスを封入し、最
後にこのゲートパイプ端部をゲートスプリング端
部と共に溶接封止して密封するのである。 In order to assemble the conventional flat thyristor, the semiconductor element 1 is first inserted into the insulating cylinder 2, and its first electrode is positioned and brought into contact with the inner surface of the thin metal plate 3, which will serve as the first main electrode. After that, the guide ring 6, heat compensator 7, and gate ring 8 are each set as specified, and then the gate spring 9 covered with the insulating tube 10 is arranged, and one end of the gate spring 9 is inserted into the gate pipe 5. Then, the other end is brought into contact with the third electrode through the gate ring 8, and the metal block 11 is brought into contact with the second electrode through the heat compensating plate 7, and then the metal block 11 is connected to the second main electrode. Metal thin plate 1
After that, the thin metal plate 12 and the welding ring 4 of the insulating cylinder 2 are welded and attached at each outer circumference, and the inside of the device is evacuated from the gate pipe 5, and an inert gas is used instead. Gas is filled in and finally the end of the gate pipe is welded and sealed together with the end of the gate spring.
しかし乍らこのように構成される従来の平形サ
イリスタでは、半導体素子の第1ないし第3の各
電極に接する各部材のうち、一方の主面側の第1
電極と、他方の主面側の第2および第3電極とが
個別に位置決めされているために、外部から振
動、衝撃などが加えられると、各主面側での部材
間にずれを生じ易く、特に第3電極、すなわちゲ
ート電極に接圧しているゲートスプリングがずれ
てしまつて、ゲート特性不良という致命的な欠陥
を招き、使用不能となるという不都合があつた。 However, in the conventional flat thyristor configured in this way, among the members in contact with the first to third electrodes of the semiconductor element, the first
Since the electrode and the second and third electrodes on the other main surface side are individually positioned, when vibrations, shocks, etc. are applied from the outside, it is easy to cause misalignment between the members on each main surface side. In particular, the gate spring that is in contact with the third electrode, that is, the gate electrode, is displaced, resulting in a fatal defect of poor gate characteristics, and the device becomes unusable.
この考案は従来のこのような欠点を改善するた
めに、従来、第2電極に接する熱補償板およびこ
の熱補償板に接する金属ブロツクを各々に位置決
めし、かつ熱補償板を介してゲートリングの位置
決めを行なうガイドリングにより、半導体素子自
体の位置決めをも行なわせるようにしたものであ
る。 In order to improve such drawbacks of the conventional device, this invention involves positioning the heat compensating plate in contact with the second electrode and the metal block in contact with this heat compensating plate, respectively, and connecting the gate ring through the heat compensating plate. The guide ring for positioning also allows the semiconductor element itself to be positioned.
以下、この考案に係わる半導体装置の一実施例
につき、第2図を参照して詳細に説明する。 Hereinafter, one embodiment of the semiconductor device according to this invention will be described in detail with reference to FIG. 2.
第2図において前記第1図と同一符号は同一ま
たは相当部分を示しており、この実施例では、前
記絶縁筒体2の内側に嵌入されて位置決め確保さ
れ、かつ同時にその内側で前記熱補償板7および
金属ブロツク11を位置決めしているガイドリン
グ6に突出部6aを形成させ、この突出部6aに
よつて前記半導体素子1の側周部、ひいては半導
体素子1自体の位置決めをも行なえるようにした
ものである。 In FIG. 2, the same reference numerals as those in FIG. A protrusion 6a is formed on the guide ring 6 that positions the semiconductor element 1 and the metal block 11, so that the side circumference of the semiconductor element 1, and even the semiconductor element 1 itself can be positioned by the protrusion 6a. This is what I did.
従つてこのように構成されたこの実施例によれ
ば、従来、半導体素子を第1電極のある一方の主
面側と、第2および第3電極のある他方の主面側
とで各別に位置決めしていたために生じたところ
の、第3電極、すなわちゲート電極とゲートスプ
リングとのずれは、この第3電極を含む他方の主
面側での位置決めの役割りを果すガイドリングに
より、半導体素子自体の位置決め確保をさせるよ
うにしているから、たとえ外部から振動、衝撃な
どが加えられても、半導体素子とそのゲート電極
に接圧されているゲートスプリングとは、常に一
体化されることになつて、両者の間にずれを生ず
ることがなくなるもので、極めて簡単な構造であ
るにも拘らずその効果が極めて大きい。 Therefore, according to this embodiment configured as described above, conventionally, the semiconductor element is positioned separately on one main surface side where the first electrode is located and on the other main surface side where the second and third electrodes are located. The misalignment between the third electrode, that is, the gate electrode, and the gate spring caused by Therefore, even if vibrations, shocks, etc. are applied from the outside, the semiconductor element and the gate spring that is in contact with the gate electrode will always be integrated. This eliminates any misalignment between the two, and although it has an extremely simple structure, its effects are extremely large.
第1図は従来例による平形サイリスタの構成を
示す断面図、第2図はこの考案の一実施例を適用
した平形サイリスタの構造を示す断面図である。
1……半導体素子、2……絶縁筒体、3,12
……金属薄板、4……溶接リング、5……ゲート
パイプ、6……ガイドリング、6a……ガイドリ
ングの突出部、7……熱補償板、8……ゲートリ
ング、9……ゲートスプリング、10……絶縁チ
ユーブ、11……金属ブロツク。
FIG. 1 is a sectional view showing the structure of a conventional flat thyristor, and FIG. 2 is a sectional view showing the structure of a flat thyristor to which an embodiment of this invention is applied. 1... Semiconductor element, 2... Insulating cylinder, 3, 12
...Thin metal plate, 4...Welding ring, 5...Gate pipe, 6...Guide ring, 6a...Protrusion of guide ring, 7...Heat compensator plate, 8...Gate ring, 9...Gate spring , 10...Insulating tube, 11...Metal block.
Claims (1)
び第3(ゲート)電極をもつ半導体素子と、一端
部に前記第1電極に接して第1主電極となる金属
薄板を、他端部に溶接リングを各々に設け、かつ
ゲートパイプを配した絶縁筒体と、前記第2電極
に接する熱補償板およびこの熱補償板に位置決め
支持されるゲートリングと、一端部を前記ゲート
パイプに嵌挿させ、他端部を前記ゲートリングに
通し位置保持して前記第3(ゲート)電極に接圧
させ、かつ絶縁チユーブで被覆したゲートスプリ
ングと、このゲートスプリングの絶縁チユーブ部
分を受け入れて前記熱補償板に接する金属ブロツ
クと、前記金属ブロツクに接して第2主電極とな
り、かつ前記溶接リングに溶接される金属薄板と
を備えて気密封止するものにおいて、前記金属ブ
ロツクの熱補償板側の端面の周縁角部を切り欠い
て凹部を設けて、この凹部と前記絶縁筒体の内周
面との間にガイドリングを嵌入して、このガイド
リングの内周面の前記熱補償板側の端部をこの熱
補償板の周側面に当接させるとともに、ガイドリ
ングの前記半導体素子に対向する端面の外周部に
突出部を設けて、この突出部の内周面を前記半導
体素子の周側面に当接させるようにしたことを特
徴とする半導体装置。 A semiconductor element having a first electrode on one main surface and second and third (gate) electrodes on the other main surface, and a thin metal plate that contacts the first electrode at one end and becomes the first main electrode, and another an insulating cylindrical body each provided with a welding ring at its end and provided with a gate pipe; a heat compensating plate in contact with the second electrode; a gate ring positioned and supported by the heat compensating plate; The other end is inserted into the gate ring, the other end is passed through the gate ring, and held in position so as to be in contact with the third (gate) electrode, and the gate spring is covered with an insulating tube, and the insulating tube portion of the gate spring is received. A metal block that is in contact with the heat compensating plate, and a thin metal plate that is in contact with the metal block and serves as a second main electrode, and is welded to the welding ring and is hermetically sealed, the heat compensating plate of the metal block. A recess is provided by cutting out a peripheral edge corner of the side end face, and a guide ring is fitted between the recess and the inner peripheral surface of the insulating cylinder, and the heat compensating plate is disposed on the inner peripheral surface of the guide ring. At the same time, a protrusion is provided on the outer periphery of the end face of the guide ring facing the semiconductor element, and the inner periphery of the protrusion is brought into contact with the peripheral surface of the semiconductor element. A semiconductor device characterized in that the semiconductor device is brought into contact with a peripheral side surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1979175925U JPH0219974Y2 (en) | 1979-12-18 | 1979-12-18 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1979175925U JPH0219974Y2 (en) | 1979-12-18 | 1979-12-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5694064U JPS5694064U (en) | 1981-07-25 |
JPH0219974Y2 true JPH0219974Y2 (en) | 1990-05-31 |
Family
ID=29686572
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1979175925U Expired JPH0219974Y2 (en) | 1979-12-18 | 1979-12-18 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0219974Y2 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS416670Y1 (en) * | 1964-09-16 | 1966-04-05 | ||
JPS5023593A (en) * | 1973-06-29 | 1975-03-13 | ||
JPS5037368A (en) * | 1973-06-19 | 1975-04-08 |
-
1979
- 1979-12-18 JP JP1979175925U patent/JPH0219974Y2/ja not_active Expired
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS416670Y1 (en) * | 1964-09-16 | 1966-04-05 | ||
JPS5037368A (en) * | 1973-06-19 | 1975-04-08 | ||
JPS5023593A (en) * | 1973-06-29 | 1975-03-13 |
Also Published As
Publication number | Publication date |
---|---|
JPS5694064U (en) | 1981-07-25 |
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