JPS6127901B2 - - Google Patents

Info

Publication number
JPS6127901B2
JPS6127901B2 JP7057380A JP7057380A JPS6127901B2 JP S6127901 B2 JPS6127901 B2 JP S6127901B2 JP 7057380 A JP7057380 A JP 7057380A JP 7057380 A JP7057380 A JP 7057380A JP S6127901 B2 JPS6127901 B2 JP S6127901B2
Authority
JP
Japan
Prior art keywords
main electrode
electrode plate
cathode
main
pressure contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP7057380A
Other languages
Japanese (ja)
Other versions
JPS56167353A (en
Inventor
Yuzuru Konishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7057380A priority Critical patent/JPS56167353A/en
Publication of JPS56167353A publication Critical patent/JPS56167353A/en
Publication of JPS6127901B2 publication Critical patent/JPS6127901B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01042Molybdenum [Mo]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】 この発明は、加圧接触形半導体装置の主電極板
の位置決め構造に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure for positioning a main electrode plate of a pressure contact type semiconductor device.

この明細書での「主電極板」にはゲートリード
が挿通される貫通孔を有するものも含むものとす
る。
In this specification, the term "main electrode plate" includes a plate having a through hole through which a gate lead is inserted.

以下、半導体制御整流装置を例にとつて説明を
行う。
A description will be given below using a semiconductor-controlled rectifier as an example.

第1図は従来の加圧接触形半導体制御整流装置
の一例の要部の縦断面図である。第1図におい
て、1はPNPN構造を有する半導体基体であるシ
リコンウエハー、2はアルミニウム蒸着層からな
りシリコンウエハー1の一方の主面の中心部上に
形成されたゲート電極、3はアルミニウム蒸着層
からなりゲート電極2が形成された主面上にゲー
ト電極2を取り囲んで形成された一方の主電極で
あるカソード電極、4はシリコンと熱膨張係数が
ほぼ等しい材料であるモリブデン、タングステン
などからなり、シリコンウエハー1の他方の主面
にろう付けされたアノード電極、5は金属弾性体
からなり金属弾性体のばね力により一端がゲート
電極2に加圧接触させられるゲートリード、6は
絶縁体からなりゲートリード5を後述のカソード
リングおよびカソード銅ブロツクと接触しないよ
うに支持するゲート支持棒、7はシリコンと熱膨
張係数がほぼ等しい材料であるモリブデン、タン
グステン、鉄・ニツケル系合金などからなりカソ
ード電極3に加圧接触させられる主電極板である
カソードリング、8はカソードリング7に加圧接
触させられる一方の主電極導電体であるカソード
銅ブロツク、9はアノード電極4に加圧接触させ
られる他方の主電極導電体であるアノード銅ブロ
ツクである。
FIG. 1 is a longitudinal cross-sectional view of a main part of an example of a conventional pressurized contact type semiconductor-controlled rectifier. In FIG. 1, 1 is a silicon wafer which is a semiconductor substrate having a PNPN structure, 2 is a gate electrode made of an aluminum vapor deposited layer and formed on the center of one main surface of the silicon wafer 1, and 3 is a gate electrode made of an aluminum vapor deposited layer. The cathode electrode 4, which is one of the main electrodes, is formed on the main surface on which the gate electrode 2 is formed, surrounding the gate electrode 2, and is made of a material such as molybdenum or tungsten, which has a coefficient of thermal expansion almost equal to that of silicon. An anode electrode is brazed to the other main surface of the silicon wafer 1, a gate lead 5 is made of an elastic metal body and one end is brought into pressure contact with the gate electrode 2 by the spring force of the elastic metal body, and 6 is made of an insulator. A gate support rod 7 supports the gate lead 5 so as not to come into contact with a cathode ring and a cathode copper block, which will be described later, and a cathode electrode 7 is made of a material such as molybdenum, tungsten, or an iron-nickel alloy, which has a coefficient of thermal expansion almost equal to that of silicon. 3 is a cathode ring which is a main electrode plate which is brought into pressure contact with the cathode ring 7; 8 is a cathode copper block which is one main electrode conductor which is brought into pressure contact with the cathode ring 7; and 9 is the other which is brought into pressure contact with the anode electrode 4. The main electrode conductor is the anode copper block.

ゲートリード5とゲート電極2およびカソード
リング7とカソード電極3は、互いの位置がずれ
ないように位置決めされなければならない。この
ため、従来の半導体制御整流装置では、カソード
銅ブロツク8の中心部にあけた孔によりゲート支
持棒6を位置決めし、ゲート支持棒6の外周でカ
ソードリング7を位置決めしていた。しかしなが
ら、上記従来の構造では、各構成部分を順次組み
立てる際、カソードリング7がゲート支持棒6か
ら外れて移動し易く、移動したカソードリング7
がゲート電極2とゲート電極3とを短絡する難点
があつた。
The gate lead 5 and the gate electrode 2, and the cathode ring 7 and the cathode electrode 3 must be positioned so that their positions do not deviate from each other. For this reason, in the conventional semiconductor-controlled rectifier, the gate support rod 6 is positioned through a hole drilled in the center of the cathode copper block 8, and the cathode ring 7 is positioned around the outer periphery of the gate support rod 6. However, in the conventional structure described above, when assembling each component in sequence, the cathode ring 7 easily comes off the gate support rod 6 and moves.
However, there was a problem in that gate electrode 2 and gate electrode 3 were short-circuited.

この発明は、上記の点に鑑みてなされたもので
あり、主電極板の周辺部に主電極導電体の外周を
取り囲みこの主電極導電体に位置決めされる周壁
を設けることによつて、主電極板の位置ずれが生
じないようにした加圧接触形半導体装置を提供す
ることを目的としたものである。
This invention has been made in view of the above points, and by providing a peripheral wall surrounding the outer periphery of the main electrode conductor and positioned on the main electrode conductor in the peripheral part of the main electrode plate, the main electrode It is an object of the present invention to provide a pressurized contact type semiconductor device in which positional displacement of the plate does not occur.

以下、この発明を半導体制御整流装置に適用し
た実施例に基づいて、この発明を説明する。
The present invention will be described below based on an example in which the present invention is applied to a semiconductor-controlled rectifier.

第2図はこの発明による加圧接触形半導体制御
整流装置の一実施例の要部の縦断面図である。第
2図において、第1図と同一符号は第1図にて示
したものと同様のものを表わしている。7aはシ
リコンと熱膨張係数がほぼ等しいモリブデン、タ
ワグステン、鉄・ニツケル系合金などからなり周
辺にカソード銅ブロツク8の外周を取り囲む周壁
を有しこの周壁の内周面からカソード銅ブロツク
8の外周面に突接するように設けられた少なくと
も三つの突出部71によつてカソード銅ブロツク
8に位置決めされているカソードリングである。
第3図は第2図の実施例のカソードリングの平面
図である。
FIG. 2 is a longitudinal sectional view of a main part of an embodiment of a pressurized contact type semiconductor-controlled rectifier according to the present invention. In FIG. 2, the same reference numerals as in FIG. 1 represent the same components as shown in FIG. 7a is made of molybdenum, tawagsten, iron-nickel alloy, etc., which has a coefficient of thermal expansion almost equal to that of silicon, and has a peripheral wall surrounding the outer periphery of the cathode copper block 8, and extends from the inner peripheral surface of this peripheral wall to the outer peripheral surface of the cathode copper block 8. The cathode ring is positioned on the cathode copper block 8 by at least three protrusions 71 provided so as to come into contact with the cathode copper block 8.
FIG. 3 is a plan view of the cathode ring of the embodiment of FIG. 2.

実施例の構造では、各構成部分を順次組み立て
る際、カソードリング7aがカソード銅ブロツク
から外れないため、カソードリング7aが移動し
て、ゲート電極2とカソード電極3とが短絡する
とか、ずれのため部分的にシリコンウエハ1に過
圧接させられてシリコンウエハ1が割れたりこれ
にクラツクが入るなどの不具合を完全に防ぐこと
ができる。従つて、実施例の半導体制御整流装置
は信頼度の高いものとなる。また、組立作業が容
易である。さらに、カソードリング7aがゲート
支持棒6で位置決めされる必要がないため、モリ
ブデン、タングステンなど高価な材料を使用する
カソードリング7aに薄板を用いることができる
から、安価に作製することができる。
In the structure of the embodiment, when assembling each component in sequence, the cathode ring 7a does not come off from the cathode copper block, so the cathode ring 7a moves and the gate electrode 2 and cathode electrode 3 are short-circuited or misaligned. It is possible to completely prevent problems such as the silicon wafer 1 being cracked or cracked due to excessive pressure being applied to a portion of the silicon wafer 1. Therefore, the semiconductor-controlled rectifier of the embodiment has high reliability. Moreover, assembly work is easy. Further, since the cathode ring 7a does not need to be positioned by the gate support rod 6, a thin plate can be used for the cathode ring 7a, which is made of expensive materials such as molybdenum and tungsten, and can be manufactured at low cost.

上記の実施例においては、この発明を半導体制
御整流装置に適用した場合について述べたが、こ
の発明は、電力用ダイオード、トライアツク、逆
導通サイリスタなどのスタツド形または平形の加
圧接触形半導体装置に広く適用することができる
ものである。
In the above embodiment, the present invention was applied to a semiconductor-controlled rectifier, but the present invention can also be applied to stud-type or flat-type pressurized contact type semiconductor devices such as power diodes, triacs, and reverse conduction thyristors. It can be widely applied.

以上説明したように、この発明による加圧接触
形半導体装置においては、主電極板が、その周辺
部に主電極導電体の外周を取り囲みこの主電極導
電体に位置決めされる周壁を有するから、主電極
板が位置ずれして、主電極と他の電極とが短絡し
たり、主電極板が半導体基体に部分的に過圧接さ
せられて、半導体基体が割れたりこれにクラツク
が入るなどの不具合を完全に防ぐことができる。
また、主電極板に薄板を用いることができる。従
つて、この発明による加圧接触形半導体装置は、
信頼性の高いものとなり、組み立てが容易であ
り、かつ価格が低下する。
As explained above, in the pressure contact type semiconductor device according to the present invention, the main electrode plate has a peripheral wall surrounding the outer periphery of the main electrode conductor and positioned on the main electrode conductor. This prevents malfunctions such as misalignment of the electrode plate, resulting in a short circuit between the main electrode and other electrodes, or partial excessive pressure contact between the main electrode plate and the semiconductor substrate, which may cause the semiconductor substrate to crack or crack. Completely preventable.
Further, a thin plate can be used for the main electrode plate. Therefore, the pressurized contact type semiconductor device according to the present invention has the following features:
It is more reliable, easier to assemble, and lower in price.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の加圧接触形半導体制御整流装置
の一例の要部の縦断面図、第2図はこの発明によ
る加圧接触形半導体制御整流装置の一実施例の要
部の縦断面図、第3図は第2図の実施例のカソー
ドリングの平面図である。 図において、1はシリコンウエハ(半導体基
体)、3はカソード電極(主電極)、7,7aはカ
ソードリング(主電極板)、71は突出部、8は
カソード銅ブロツク(主電極導電体)である。な
お、図中同一符号はそれぞれ同一または相当部分
を示す。
FIG. 1 is a longitudinal cross-sectional view of a main part of an example of a conventional pressurized contact type semiconductor-controlled rectifier, and FIG. 2 is a longitudinal cross-sectional view of a main part of an embodiment of a pressurized contact type semiconductor-controlled rectifier according to the present invention. , FIG. 3 is a plan view of the cathode ring of the embodiment of FIG. 2. In the figure, 1 is a silicon wafer (semiconductor substrate), 3 is a cathode electrode (main electrode), 7 and 7a are cathode rings (main electrode plate), 71 is a protrusion, and 8 is a cathode copper block (main electrode conductor). be. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】 1 少なくとも一つのPN接合を有する半導体基
体、この半導体基体の一主面上に設けられた主電
極、上記半導体基体の材料と熱膨張係数がほぼ等
しい材料からなり上記主電極に加圧接触させられ
る主電極板、およびこの主電極板に加圧接触させ
られる主電極導電体を備えたものにおいて、上記
主電極板における上記主電極導電体側の面に、主
電極導電体に向つて立ち上がり主電極導電体の側
壁に当つて位置決めされる立ち上がり壁を設けた
ことを特徴とする加圧接触形半導体装置。 2 主電極板の周壁がその内周に主電極導電体の
外周面に係止される突出部を少なくとも3個有す
ることを特徴とする特許請求の範囲第1項記載の
加圧接触形半導体装置。 3 主電極板がゲートリードを挿通させる貫通孔
を有することを特徴とする特許請求の範囲第1項
または第2項記載の加圧接触形半導体装置。
[Scope of Claims] 1. A semiconductor substrate having at least one PN junction, a main electrode provided on one main surface of the semiconductor substrate, and the main electrode made of a material having a coefficient of thermal expansion substantially equal to that of the material of the semiconductor substrate. In a device comprising a main electrode plate that is brought into pressure contact with the main electrode plate and a main electrode conductor that is brought into pressure contact with the main electrode plate, a surface of the main electrode plate on the side of the main electrode conductor is provided with a 1. A pressure contact type semiconductor device comprising a rising wall that rises toward the side and is positioned against a side wall of a main electrode conductor. 2. The pressurized contact type semiconductor device according to claim 1, wherein the peripheral wall of the main electrode plate has at least three protrusions on its inner periphery that are engaged with the outer peripheral surface of the main electrode conductor. . 3. The pressure contact type semiconductor device according to claim 1 or 2, wherein the main electrode plate has a through hole through which a gate lead is inserted.
JP7057380A 1980-05-26 1980-05-26 Pressure-welding type semiconductor device Granted JPS56167353A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7057380A JPS56167353A (en) 1980-05-26 1980-05-26 Pressure-welding type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7057380A JPS56167353A (en) 1980-05-26 1980-05-26 Pressure-welding type semiconductor device

Publications (2)

Publication Number Publication Date
JPS56167353A JPS56167353A (en) 1981-12-23
JPS6127901B2 true JPS6127901B2 (en) 1986-06-27

Family

ID=13435423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7057380A Granted JPS56167353A (en) 1980-05-26 1980-05-26 Pressure-welding type semiconductor device

Country Status (1)

Country Link
JP (1) JPS56167353A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007258372A (en) * 2006-03-22 2007-10-04 Toyota Central Res & Dev Lab Inc Semiconductor apparatus
KR20210097738A (en) * 2018-11-27 2021-08-09 아체트엘 아헨 게엠베하 Compression processing equipment for flat material

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6452261B1 (en) * 1997-03-26 2002-09-17 Hitachi, Ltd. Flat semiconductor device and power converter employing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007258372A (en) * 2006-03-22 2007-10-04 Toyota Central Res & Dev Lab Inc Semiconductor apparatus
JP4727471B2 (en) * 2006-03-22 2011-07-20 株式会社豊田中央研究所 Semiconductor device
KR20210097738A (en) * 2018-11-27 2021-08-09 아체트엘 아헨 게엠베하 Compression processing equipment for flat material

Also Published As

Publication number Publication date
JPS56167353A (en) 1981-12-23

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