JPH02170543A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPH02170543A JPH02170543A JP32490188A JP32490188A JPH02170543A JP H02170543 A JPH02170543 A JP H02170543A JP 32490188 A JP32490188 A JP 32490188A JP 32490188 A JP32490188 A JP 32490188A JP H02170543 A JPH02170543 A JP H02170543A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- region
- semiconductor
- source
- recrystallized
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000010409 thin film Substances 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 60
- 239000010408 film Substances 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims description 8
- 238000000206 photolithography Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 230000003213 activating effect Effects 0.000 claims description 2
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 239000013078 crystal Substances 0.000 abstract description 2
- 239000002245 particle Substances 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、絶縁性基体上の薄膜トランジスタの製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a thin film transistor on an insulating substrate.
［従来の技術］
従来の技術としては特開昭６５−１３６６２３号公報に
記載されたものがある。これは第２図（Ｃ＋、、）に示
すように絶縁基板１３上に第１半導体膜１４を成膜した
後、エネルギービーム１５を照射し第１半導体膜１４を
再結晶化し再結晶半導体膜１６とし、第２図（ｂ）に示
すようにソースとドレイン電極に低抵抗な第２半導体膜
１７と絶縁膜１８を残し、再びエネルギービームを照射
し、第２半導体膜１７を活性化し低抵抗にする。次に第
２図（Ｃ）に示すようにゲート絶縁膜９を堆積し、低抵
抗の第３半導体膜１９を堆積後、ゲート電極１０．ソー
ス電極１１ ドレイン電極１２を形成する薄膜トランジ
スタの製造方法であった。[Prior Art] As a conventional technique, there is one described in Japanese Patent Application Laid-Open No. 136623/1983. As shown in FIG. 2 (C+, , ), after a first semiconductor film 14 is formed on an insulating substrate 13, an energy beam 15 is irradiated to recrystallize the first semiconductor film 14, and a recrystallized semiconductor film 16 is formed. Then, as shown in FIG. 2(b), the second semiconductor film 17 and the insulating film 18 with low resistance are left on the source and drain electrodes, and the energy beam is irradiated again to activate the second semiconductor film 17 and make it low resistance. do. Next, as shown in FIG. 2(C), a gate insulating film 9 is deposited, and after depositing a low resistance third semiconductor film 19, a gate electrode 10. This was a method for manufacturing a thin film transistor in which a source electrode 11 and a drain electrode 12 are formed.
［発明が解決しようとする課題］
しかし、かかる従来の薄板トランジスタの製造方法は、
チャンネル領域となる第１半導体膜１４を均一に再結晶
化し再結晶半導体膜１６を構成するために一度エネルギ
ービーム１５を照射し、さらに低抵抗な第２半導体膜１
７を活性化しより低抵抗な膜にするために再度エネルギ
ービーム１５を照射する必要があった。さらに、チャン
ネル領域となる第１半導体膜１４とオーミック接触層と
なる低抵抗な第２半導体膜１７とは成膜条件が異なり、
製造方法が複雑なものとなる問題点を有していた：
そこで、本発明は従来のこのような問題点を解決するた
め、チャンネル領域の半導体層の再結晶化と低抵抗なオ
ーミック接触層の構成のためのエネルギービーム照射を
一回だけとし、さらにチャンネル領域の半導体層とソー
ス領域とドレイン領域の半導体層との成膜条件・を同じ
ものとして製造方法を簡略化できる簿膜トランジスタの
製造方法を提供することを目的とする。[Problems to be Solved by the Invention] However, the conventional thin plate transistor manufacturing method has the following problems:
In order to uniformly recrystallize the first semiconductor film 14 that will become the channel region and form the recrystallized semiconductor film 16, the energy beam 15 is irradiated once, and then the second semiconductor film 1 having a low resistance is further irradiated with the energy beam 15.
It was necessary to irradiate the energy beam 15 again to activate the film 7 and make it a film with lower resistance. Furthermore, the first semiconductor film 14 that will become the channel region and the low-resistance second semiconductor film 17 that will become the ohmic contact layer have different film-forming conditions.
Therefore, in order to solve these conventional problems, the present invention involves recrystallization of the semiconductor layer in the channel region and formation of a low-resistance ohmic contact layer. A method for manufacturing a thin film transistor that simplifies the manufacturing method by requiring only one energy beam irradiation for configuration and using the same film-forming conditions for the semiconductor layer in the channel region, the semiconductor layer in the source region, and the semiconductor layer in the drain region. The purpose is to provide
［課題を解決するための手段］
上記課題を解決するため、本発明の薄膜トランジスタの
製造方法は、絶縁性基体上に第１半導体層を堆積し、フ
ォ） ＩＪソ技術によりソース領域とドレイン領域に前
記第、１半導体層を島状に残す工程と、第２半導体層を
堆積し、ソース領域とドレイン領域にある前記第１半導
体層上とチャンネル領域にフォトリソ技術により島状に
残す工程と、前記第１半導体層と前記第２半導体層が積
層したソース領域とドレイン領域に不純物を含有する酸
化ケイ素を島状にフォトリソ技術により残す工程と、レ
ーザ・ビームを照射してソース領域とドレイン領域に前
記酸化ケイ素中の前記不純物を前記第２半導体と第１半
導体層へ拡散し活性化してオーミック接触層を構成し、
チャンネル領域の第２半導体層を再結晶化する工程と、
ゲート絶縁膜を堆積する工程と、ゲート電極を構成し、
ソース領域とドレイン領域にコンタクト・ホールを形成
してソース電極とドレイン電極を製作する工程からなる
ことを特徴とする。[Means for Solving the Problems] In order to solve the above problems, the method for manufacturing a thin film transistor of the present invention includes depositing a first semiconductor layer on an insulating substrate, and depositing a first semiconductor layer on a source region and a drain region using an IJ method. a step of leaving the first semiconductor layer in an island shape; a step of depositing a second semiconductor layer and leaving it in an island shape on the first semiconductor layer in the source region and the drain region and in the channel region by photolithography; A step of leaving silicon oxide containing impurities in the form of islands in the source region and drain region where the first semiconductor layer and the second semiconductor layer are laminated by photolithography, and irradiating the source region and the drain region with a laser beam. Diffusing and activating the impurity in the silicon oxide into the second semiconductor and first semiconductor layer to form an ohmic contact layer;
recrystallizing the second semiconductor layer in the channel region;
The process of depositing a gate insulating film and configuring a gate electrode,
The method is characterized by a process of forming contact holes in the source and drain regions to fabricate the source and drain electrodes.
［実施例］
以下に本発明の実施例を図面にもとづいて説明する。第
１図（α）において、絶縁性基体１上に成膜した第１半
導体層２をソース領域４とドレイン領域５にフォトリソ
技術により島状に残す。次に、第１図（ｂ）に示すよう
に、第２半導体層３を積層し島状に残す。第１半導体層
２と第２半導体層６は、異なる成膜条件で成膜しても良
（、また、同じ成膜条件で同じ膜質をもつ膜を成膜して
も良い。次に、第１図ＣＣ）において、不純物を含有す
る酸化ケイ素６をソース領域４とドレイン領域５の上に
島状に残し、レーザ・ビーム７、を照射して第１半導体
層２と第２半導体層６を融解し、酸化ケイ素６中の不純
物をソース領域４上とドレイン領域５上の第１半導体層
２と第２半導体層５の中へ拡散し、活性化させる。また
、同時に、このレーザ・ビーム７の照射により、チャン
ネル領域６上の第２半導体層６を融解し、再結晶化する
ことにより大きな結晶粒径を有する再結晶半導体膜を得
ることができる。この結果、酸化ケイ素６を除去後、第
１図（ｄ）にみられるように、前工程での酸化ケイ素６
より拡散した不純物により構成した低抵抗なオーミック
接触層８と再結晶化したチャンネル領域６上の再結晶半
導体膜１６が構成される。オーミック接触層８と再結晶
半導体膜１６上にはゲート絶縁膜９を成膜する。次に、
第１図（Ｉｔ）でゲート電極１０を構成し、フォトリソ
技術によりゲート絶縁膜９にコンタクト・ホールを形成
後、そのコンタクト・ホールを埋めるようにソース電極
１１とドレイン電柵１２を構成して薄膜トランジスタが
完成する。[Examples] Examples of the present invention will be described below based on the drawings. In FIG. 1(α), the first semiconductor layer 2 formed on the insulating substrate 1 is left in the form of islands in the source region 4 and drain region 5 by photolithography. Next, as shown in FIG. 1(b), the second semiconductor layer 3 is stacked and left in the form of an island. The first semiconductor layer 2 and the second semiconductor layer 6 may be formed under different film formation conditions (or, films having the same film quality may be formed under the same film formation conditions. 1 CC), silicon oxide 6 containing impurities is left in an island shape on the source region 4 and drain region 5, and the first semiconductor layer 2 and the second semiconductor layer 6 are irradiated with a laser beam 7. It is melted, and the impurities in the silicon oxide 6 are diffused into the first semiconductor layer 2 and the second semiconductor layer 5 on the source region 4 and drain region 5, and activated. At the same time, the second semiconductor layer 6 on the channel region 6 is melted and recrystallized by the irradiation with the laser beam 7, thereby making it possible to obtain a recrystallized semiconductor film having a large crystal grain size. As a result, after removing the silicon oxide 6, as shown in FIG. 1(d), the silicon oxide 6 removed in the previous step is
A low-resistance ohmic contact layer 8 made of more diffused impurities and a recrystallized semiconductor film 16 on the recrystallized channel region 6 are constructed. A gate insulating film 9 is formed on the ohmic contact layer 8 and the recrystallized semiconductor film 16. next,
As shown in FIG. 1 (It), a gate electrode 10 is formed, a contact hole is formed in the gate insulating film 9 by photolithography, and a source electrode 11 and a drain electric fence 12 are formed so as to fill the contact hole to form a thin film transistor. is completed.
［発明の効果、コ。[Effect of invention, co.
本発明の薄膜トランジスタの製造方法は、以上説明した
ように、Ｎ膜）ランジスタのチャンネル領域の半導体層
の再結晶化と不純物を含有する低抵抗なオーミック接触
層゛の構成を一回のレーザ・ビームの照射により実現す
ることが可能で、工程が簡略化すると共に、半導体層の
再結晶化による薄膜トランジスタの高性能化も実現でき
る。また、低抵抗なオーミック接触層の構成がレーザ・
ビームによる拡散と活性化により可能なため、チャンネ
ル領域とソース領域及びドレイン領域の半導体層を同じ
成膜条件で同じ物性を有する膜として構成することも可
能で、製造方法を単純なものとすることが容易であると
いう効果を有する。As explained above, the method for manufacturing a thin film transistor of the present invention includes recrystallizing the semiconductor layer in the channel region of the N-film transistor and forming a low-resistance ohmic contact layer containing impurities using a single laser beam. This can be achieved by irradiation with irradiation, which simplifies the process and also improves the performance of thin film transistors by recrystallizing the semiconductor layer. In addition, the structure of the low-resistance ohmic contact layer
Since this is possible through diffusion and activation by a beam, it is also possible to configure the semiconductor layers of the channel region, source region, and drain region as films having the same physical properties under the same film formation conditions, simplifying the manufacturing method. This has the effect that it is easy to use.
第１図（α）〜（１）は、本発明の薄膜トランジスタの
製造方法の実施例の工程順を説明するための断面図。
第２図（α）〜（、ｃ）は、従来の薄膜トランジスタの
製造方法の工程順を説明するための断面図１・・・・・
・・・・絶縁性基体
２・・・・・・・・・第１半導体層
５・・・・・・・・・第２半導体層
４・・・・・・・・・ソース領域
５・・・・・・・・・ドレイン領域
６・・・・・・・・酸化ケイ素
７・・・・・・・・レーザ・ビーム
８・・・・・・・・・オーミック接触層９・・・・・・
・・・ゲート絶縁膜
０・・・・・・・・・ゲート電極
１・・・・・・・・・ソース電極
２・・・、・・・・・・ドレイン電極
６・・・・・・・・・絶縁基板
４・・・・・・・・・第１半導体膜
５・・・・・・・・・エネルギービーム６・・・・・・
・・・再結晶半導体膜
７・・・・・・・・・第２半導体膜
８・・・・・・・・・絶縁膜
１９・・・・・・・・・第３半導体膜
以上FIGS. 1(α) to 1(1) are cross-sectional views for explaining the process order of an embodiment of the method for manufacturing a thin film transistor of the present invention. FIGS. 2(α) to 2(c) are cross-sectional views 1 for explaining the process order of a conventional thin film transistor manufacturing method.
...Insulating base 2...First semiconductor layer 5...Second semiconductor layer 4...Source region 5... ......Drain region 6...Silicon oxide 7...Laser beam 8...Ohmic contact layer 9...・・・
...Gate insulating film 0...Gate electrode 1...Source electrode 2...Drain electrode 6... ...Insulating substrate 4...First semiconductor film 5...Energy beam 6...
. . . Recrystallized semiconductor film 7 . . . Second semiconductor film 8 . . . Insulating film 19 . . . Third semiconductor film or higher
Claims (1)
ソ技術によりソース領域とドレイン領域に前記第１半導
体層を島状に残す工程と、第２半導体層を堆積し、ソー
ス領域とドレイン領域にある前記第１半導体層上とチャ
ンネル領域にフォトリソ技術により島状に残す工程と、
前記第１半導体層と前記第２半導体層が積層したソース
領域とドレイン領域に不純物を含有する酸化ケイ素を島
状にフォトリソ技術により残す工程と、レーザ・ビーム
を照射してソース領域とドレイン領域に前記酸化ケイ素
中の前記不純物を前記第２半導体層と第１半導体層へ拡
散し活性化してオーミック接触層を構成し、チャンネル
領域の第２半導体層を再結晶化する工程と、ゲート絶縁
膜を堆積する工程と、ゲート電極を構成し、ソース領域
とドレイン領域にコンタクト・ホールを形成してソース
電極とドレイン電極を製作する工程からなることを特徴
とする薄膜トランジスタの製造方法。(1) A step of depositing a first semiconductor layer on an insulating substrate and leaving the first semiconductor layer in an island shape in the source region and drain region by photolithography, and depositing a second semiconductor layer and leaving the first semiconductor layer in the source region and drain region. a step of leaving an island shape on the first semiconductor layer in the region and the channel region by photolithography;
A step of leaving silicon oxide containing impurities in the form of islands in the source region and drain region where the first semiconductor layer and the second semiconductor layer are laminated by photolithography, and irradiating the source region and the drain region with a laser beam. Diffusing and activating the impurity in the silicon oxide into the second semiconductor layer and the first semiconductor layer to form an ohmic contact layer, recrystallizing the second semiconductor layer in the channel region, and forming a gate insulating film. 1. A method for manufacturing a thin film transistor, comprising a step of depositing a gate electrode, and a step of forming a source electrode and a drain electrode by forming a gate electrode and forming contact holes in a source region and a drain region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32490188A JPH02170543A (en) | 1988-12-23 | 1988-12-23 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32490188A JPH02170543A (en) | 1988-12-23 | 1988-12-23 | Manufacture of thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02170543A true JPH02170543A (en) | 1990-07-02 |
Family
ID=18170893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32490188A Pending JPH02170543A (en) | 1988-12-23 | 1988-12-23 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02170543A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04120738A (en) * | 1990-09-11 | 1992-04-21 | Semiconductor Energy Lab Co Ltd | Manufacture of thin-film transistor |
| WO2010091466A1 (en) * | 2009-02-11 | 2010-08-19 | Newsouth Innovations Pty Limited | Photovoltaic device structure and method |
-
1988
- 1988-12-23 JP JP32490188A patent/JPH02170543A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04120738A (en) * | 1990-09-11 | 1992-04-21 | Semiconductor Energy Lab Co Ltd | Manufacture of thin-film transistor |
| WO2010091466A1 (en) * | 2009-02-11 | 2010-08-19 | Newsouth Innovations Pty Limited | Photovoltaic device structure and method |
| AU2010213356B2 (en) * | 2009-02-11 | 2015-05-28 | Newsouth Innovations Pty Limited | Photovoltaic device structure and method |
| US9136126B2 (en) | 2009-02-11 | 2015-09-15 | Newsouth Innovations Pty Limited | Method of forming doped regions in a photovoltaic device |
| US10199523B2 (en) | 2009-02-11 | 2019-02-05 | Newsouth Innovations Pty Limited | Photovoltaic device structure and method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2001028448A (en) | Manufacture if thin-film transistor | |
| JPH02177443A (en) | Manufacture of thin film transistor | |
| JP2000058836A (en) | Manufacture of semiconductor device | |
| JPH02170543A (en) | Manufacture of thin film transistor | |
| JP3284899B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH0325949B2 (en) | ||
| JPS6269680A (en) | Manufacture of thin film transistor | |
| JPH0438140B2 (en) | ||
| JPH02208942A (en) | Manufacture of thin film transistor | |
| JPS5825221A (en) | Manufacture of semiconductor device | |
| JPH02864B2 (en) | ||
| JPS6342417B2 (en) | ||
| JPH0467336B2 (en) | ||
| JP3181901B2 (en) | Thin film transistor | |
| JPH02863B2 (en) | ||
| JP2587570B2 (en) | Polycrystalline silicon thin film transistor and method of manufacturing the same | |
| JP3291845B2 (en) | Crystal growing method and channel forming method for MOS transistor | |
| JPS6315471A (en) | Thin film transistor and manufacture thereof | |
| JPH05251465A (en) | Thin film transistor and manufacture of the same | |
| JPS60236257A (en) | Semiconductor device | |
| JPH02194561A (en) | Thin-film semiconductor device and manufacture thereof | |
| JPS5837952A (en) | Semiconductor device and manufacture thereof | |
| JPH1012892A (en) | Processing of semiconductor device thin film | |
| JPH0294624A (en) | Semiconductor device | |
| JPH08181317A (en) | Manufacture of semiconductor device |