JPH02156679A - Field effect transistor and manufacture thereof - Google Patents
Field effect transistor and manufacture thereofInfo
- Publication number
- JPH02156679A JPH02156679A JP63311547A JP31154788A JPH02156679A JP H02156679 A JPH02156679 A JP H02156679A JP 63311547 A JP63311547 A JP 63311547A JP 31154788 A JP31154788 A JP 31154788A JP H02156679 A JPH02156679 A JP H02156679A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- source
- diffusion
- channel
- path resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000009792 diffusion process Methods 0.000 claims abstract description 23
- 230000003071 parasitic effect Effects 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 6
- 230000003247 decreasing effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000004460 silage Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
A、産業上の利用分野
本発明は、電界効果トランジスタ及びその製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a field effect transistor and a method for manufacturing the same.
B0発明の概要
本発明の電界効果トランジスタは、ソース構造部をP−
層に拡散された第1及び第2のソース層と、前記第1の
ソース層下部に設けられた高濃度の深いP°拡散層と、
前記第1のソース層より前記P°拡散層内にかけて設け
られた第1のv17+¥と、この第1のV ’rl/l
に設けられたソース電極から構成し、ゲート構造部を、
前記第2のソース層より面記P−層下部にかけて設けら
れた第2のV溝と、この第2溝から前記ソース電極構造
部近傍にかけての上面に設けたゲート酸化膜と、このゲ
ート酸化膜上に設けられたゲート電極とより構成し、電
子電流経路抵抗を大ならしめると共にホール電流経路抵
抗を小ならしめるようにしたものである。B0 Summary of the Invention The field effect transistor of the present invention has a source structure of P-
first and second source layers diffused into the first and second source layers; a deep highly concentrated P° diffusion layer provided under the first source layer;
A first v17+¥ provided from the first source layer into the P° diffusion layer, and this first V'rl/l
The gate structure consists of a source electrode provided in the
a second V groove provided from the second source layer to the lower part of the P- layer; a gate oxide film provided on the upper surface from the second groove to the vicinity of the source electrode structure; and the gate oxide film. It is configured with a gate electrode provided above, and is designed to increase the electron current path resistance and reduce the hole current path resistance.
また、その製造方法は、P−層ト部より深くP゛拡散層
を形成した後、このP°拡散層上及び前記P層層に拡散
により第1及び第2のl°ソース層を形成し、この第1
及び第2のn°ソース層に第1及び第2のV溝を設ける
ようにしたものである。In addition, the manufacturing method includes forming a P' diffusion layer deeper than the top part of the P' layer, and then forming first and second l' source layers by diffusion on this P' diffusion layer and in the P layer. , this first
And the second n° source layer is provided with first and second V grooves.
C9従来の技術
従来の竪型MOS電界効果トランジスタ(以下1? E
Tという)は、第3図に示すように構成されており、
ゲート電極G1.:電圧を印加すことによって、酸化物
5iOzとの界面近傍に薄いP層の反転層を形成させ、
それにより電子e−が矢印方向に流れ、ゲート電圧を取
り去ると反転層が蓄積状態となり電子e−は流れなくな
る。これにより高速のスイッチングを行うことができる
。MOSFETは竪形にしたことによりチャネル形成密
度が上かり、電流容量が増す事によって電子用としての
用途か開けた。C9 Conventional technology Conventional vertical MOS field effect transistor (hereinafter referred to as 1?E
(referred to as T) is configured as shown in Figure 3,
Gate electrode G1. : By applying a voltage, a thin P layer inversion layer is formed near the interface with the oxide 5iOz,
As a result, electrons e- flow in the direction of the arrow, and when the gate voltage is removed, the inversion layer becomes in an accumulation state and electrons e- no longer flow. This allows high-speed switching to be performed. By making MOSFETs vertical, the channel formation density is increased, and the current capacity is increased, which opens the door to electronic applications.
最近更に消費電力を軽減するために、ON抵抗を下げ、
更に電流容量を上げる試みがなされた。Recently, in order to further reduce power consumption, the ON resistance has been lowered,
Attempts were made to further increase the current capacity.
第4図、第5図にバイポーラ型のMOSF’ETを示す
。これらは電流キャリアを電子eとポールhにすること
によってON抵抗を下げ、かつ、第5図はゲート位置を
低くして電流経路を短縮し更に抵抗を下げている。FIGS. 4 and 5 show a bipolar MOSF'ET. These reduce the ON resistance by using electrons e and poles h as current carriers, and in FIG. 5, the gate position is lowered to shorten the current path and further reduce the resistance.
D1発明が解決しようとする課題
ところが、このバイポーラ型の構造では、点線枠aで囲
まれている部分がサイリスタ構造(寄生サイリスク)と
なり、この寄生サイリスタが、成る印加電圧以上ではO
Nの状態になるため、ゲート信号によるターン−オフが
できなくなる。この現象はラッチアップと呼ばれる。D1 Problem to be Solved by the Invention However, in this bipolar structure, the part surrounded by the dotted line frame a becomes a thyristor structure (parasitic thyristor), and this parasitic thyristor becomes O
Since it is in the N state, it cannot be turned off by the gate signal. This phenomenon is called latch-up.
〈ラッチアップが起こらない条件〉
寄生サイリスタ部分は、第6図に示すようにnpn接合
とpnp接合の2つのトランジスタを組合せた構造とな
っており、各々の電流増幅率が次式(1)を満たす限り
はラッチアップは抑制でさる。<Conditions under which latch-up does not occur> As shown in Figure 6, the parasitic thyristor part has a structure in which two transistors, an npn junction and a pnp junction, are combined, and the current amplification factor of each is expressed by the following equation (1). As long as the conditions are met, latch-up can be suppressed.
apnp十αnpn < 1 ・・・・・・・・・
(1)ここで、αnpn= I c/ I E、 [v
:= I o+ T cこれを更に第7図で説明すると
、電子e−の経路抵抗Rsとポールh°の経路抵抗Rp
が並列に存在すると考えられ、次式(2)を満たす限り
ラブデアツブは起こらない。apnp ten αnpn < 1 ・・・・・・・・・
(1) Here, αnpn= I c/ I E, [v
:= I o+ Tc To further explain this with FIG. 7, the path resistance Rs of electron e- and the path resistance Rp of pole h°
are considered to exist in parallel, and as long as the following equation (2) is satisfied, love decomposition will not occur.
1h−Rp−■e−RN<Vb
ここで、■h;ホール電流、!e:電子電流■b;拡散
電位差
従って、上記式(1)、(2)を満たずためには、
1)Ihを小さくする。1h-Rp-■e-RN<Vb Here, ■h; Hall current,! e: Electron current ■b: Diffusion potential difference Therefore, in order to satisfy the above formulas (1) and (2), 1) Ih should be made small.
−言)Rpを小さくする。-) Reduce Rp.
1ii)RNを大きくする。1ii) Increase RN.
等の工夫が必要である。Efforts such as these are necessary.
本発明は バイポーラ型MO3FETにおいて、ラッチ
アップか起こらないための条件として前記)、1ii)
項を満たすことのできる半導体装置及びその製造方法を
提供するものである。The present invention provides conditions for preventing latch-up from occurring in bipolar MO3FETs) and 1ii).
The object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can satisfy the following conditions.
E8課題を解決するための手段
上記目的を達成するために、本発明の電界効果トランジ
スタは、P−層に拡散された第1及び第2のソース層と
、前記第1のソース層下部に設けられた高濃度の深いP
゛拡故層と、前記第1のソース層より前記P゛拡散層内
にかけて設けられた第1のV iKと、この第1のV
iRに設けられたソース電極からなるソース構造部と、
前記第2のソース層より前記P−層下部にかけて設けら
れた第2の■溝と、この第2溝から前記ソース電極構造
部近傍にかけての上面に設けたゲート酸化膜と、このゲ
ート酸化膜上に設けられたゲート電極とよりなるゲート
構造部とを備えてなるものである。Means for Solving Problem E8 In order to achieve the above object, the field effect transistor of the present invention includes first and second source layers diffused in the P- layer and provided below the first source layer. deep P with high concentration
a first V iK provided extending from the first source layer into the P diffusion layer;
a source structure consisting of a source electrode provided in iR;
a second trench provided from the second source layer to the lower part of the P- layer; a gate oxide film provided on the upper surface from the second trench to the vicinity of the source electrode structure; and a gate oxide film provided on the gate oxide film. The gate structure includes a gate electrode provided in the gate electrode and a gate structure section.
また、その製造方法は、P−層上部より深くP゛拡散層
を形成した後、このP°拡散層上及び前記P−層に拡散
により第1及び第2のn4ソ一ス層を形成し、この第1
及び第2のn°ソース層に第1及び第2の■溝を設ける
ようにしたものである。In addition, the manufacturing method includes forming a P' diffusion layer deeper than the upper part of the P- layer, and then forming first and second N4 source layers by diffusion on this P° diffusion layer and in the P- layer. , this first
In addition, first and second grooves are provided in the second n° source layer.
F8作用
電子電流は、第1のソース層よりP−層上部に形成され
る第1のnチャネル層、第2のソース層。The F8 action electron current flows through the first n-channel layer and the second source layer, which are formed above the P- layer from the first source layer.
p−層の第2の■溝側に形成される第2のnチャネル層
を経てドレイン電極の方に流れる。It flows toward the drain electrode via the second n-channel layer formed on the second groove side of the p- layer.
電子電流は第1.第2のnチャネル層を通るので電子電
流経路抵抗R1が大きくなる。The electron current is the first. Since the electron current passes through the second n-channel layer, the electron current path resistance R1 increases.
第1のnチャネル層は常時反転状態にあり、ソース、ド
レイン間の電流のOn−。ff制御は第2のnチャネル
により行われる。The first n-channel layer is always in an inverted state, and the current between the source and drain is On-. ff control is performed by the second n-channel.
ホール電流は、ドレイン側よりP−層、P°拡散層を通
ってソース電極へ流れるので、ポール電流経路抵抗RP
は小さくなる。Since the hole current flows from the drain side through the P− layer and the P° diffusion layer to the source electrode, the pole current path resistance RP
becomes smaller.
抵抗RNが大きくなり、抵抗Rpが小さくなるので、寄
生サイリスクによるラッチアップ現象が起きる電圧が高
くなる。Since the resistance RN becomes larger and the resistance Rp becomes smaller, the voltage at which the latch-up phenomenon due to parasitic silage occurs becomes higher.
G、実施例
本発明の実施例に係る電界効果トランジスタを製造方法
と共に説明する。G. Example A field effect transistor according to an example of the present invention will be described together with a manufacturing method.
P゛シリコン基基板上上n゛エピタキシヤル層2n−エ
ピタキシャル層3.及び下部濃度を高くしたP−エピタ
キシャル層4を順次設ける。P゛on silicon base substrate n゛epitaxial layer 2n-epitaxial layer 3. and a P-epitaxial layer 4 with a higher lower concentration.
I)−エピタキシャル層4のソース構造部分13に高濃
度で深いP゛拡散層5を設ける。次いでPエピタキシャ
ル層4のソース構造部分I3及びその両側のゲート電極
構造部分14に浅く第1.第2のn゛ソース層6.6.
を設け、各ソース層61゜6、部分にP−エピタキシャ
ル層4の深さに相当する深さの第1.第2のV溝7..
7.を設ける。I)-Providing a deep and highly doped P diffusion layer 5 in the source structure portion 13 of the epitaxial layer 4; Next, a shallow first . Second n source layer 6.6.
A first layer 61.6 is provided at a depth corresponding to the depth of the P-epitaxial layer 4 in each source layer 61.6. Second V groove7. ..
7. will be established.
第2のV溝72面及びその開口部に続くソース電極構造
部I3に接する位置までの両側上面を酸化してS i
Otゲート酸化膜8を設ける。そして、このゲート酸化
膜8.第1のV溝7I及びP゛シリコン基板lに夫々ソ
ース電極9.ゲート電極IO及びドレイン電極!■を設
け、ゲート電極n+をパッシベーション膜12で覆って
構成されている。S i
An Ot gate oxide film 8 is provided. Then, this gate oxide film 8. Source electrodes 9. are formed in the first V groove 7I and the P silicon substrate 1, respectively. Gate electrode IO and drain electrode! (2) and the gate electrode n+ is covered with a passivation film 12.
しかして、上記電界効果トランジスタは、高濃度P0拡
散層5を下に置く第1のn°ソース層6□及び低濃度P
−層を従える第2のn゛ソース層6が形成されて、第1
.第2のn°ソース層6..6゜はP−反転層(チャネ
ル)4′で結ばれる。このチャネル4′は常時ONの状
態となり、EFTのon−offはゲート部第2のチャ
ネル4#により行うものである。Therefore, the above field effect transistor has a first n° source layer 6□ with a high concentration P0 diffusion layer 5 below and a low concentration P0 diffusion layer 5.
- a second n' source layer 6 is formed which follows the first layer;
.. Second n° source layer 6. .. 6° are connected by the P-inversion layer (channel) 4'. This channel 4' is always on, and the EFT is turned on and off by the second channel 4# of the gate section.
次に上記電界効果トランジスタの動作を説明する。電子
電流は、n0ソ一ス層61−nチャネル4′〜n0ソご
ス層6.−nチャネル4″−n層3−n0層2−P°基
基板−ドレイン電極!+の経路で流れる。このように電
子電流は2本のnチャネル4′、4″経路をとるので、
前記iii )項の抵抗Rnが増加する。Next, the operation of the above field effect transistor will be explained. The electron current flows through the n0 source layer 61-n channel 4' to the n0 source layer 6. -n channel 4'' -n layer 3 -n0 layer 2 -P°substrate - drain electrode!
The resistance Rn in item iii) increases.
又ホール電流は、P゛基基板−n4層2−n層3−P−
層4−P゛層8−ソース電極9の経路で流れる。このた
め、20層5により前記11)項の抵抗Rpか低減する
。In addition, the Hall current is
It flows along the path of layer 4-P layer 8-source electrode 9. Therefore, the resistance Rp in the above item 11) is reduced by the 20 layer 5.
この結果、第2図のように本発明の電界効果トランジス
タ&は従来電界トランジスタbに比しラッチアップ現象
の起こる電圧VPを大巾に上げることができた。As a result, as shown in FIG. 2, the field effect transistor & of the present invention was able to greatly increase the voltage VP at which the latch-up phenomenon occurs, compared to the conventional field effect transistor b.
なお、上記実施例ではP′層4をエピタキシャル層とし
、ソース層6を拡散層としているが、P層4を拡散層と
し、ソース層6をイオン注入によるものとするなど、適
宜変更しうろことはいうまでもない。In the above embodiment, the P' layer 4 is an epitaxial layer and the source layer 6 is a diffusion layer, but it may be modified as appropriate, such as by using the P layer 4 as a diffusion layer and the source layer 6 by ion implantation. Needless to say.
H0発明の効果
本発明は、上述のとおり構成されているので、電子電流
経路抵抗が大きくなり、又、ホール電流経路抵抗が小さ
くなるので、寄生サイリスタによるラブチアツブ現象の
起る電圧を大巾に高くすることができる。H0 Effects of the Invention Since the present invention is configured as described above, the electron current path resistance is increased and the hole current path resistance is decreased, so that the voltage at which the love-throttle phenomenon caused by the parasitic thyristor occurs can be greatly increased. can do.
第1図は本発明の実施例を示す正断面図、第2図はラブ
チアツブ現象の起る電圧曲線図、第3図乃至第5図は夫
々異なる従来電圧効果トランジスタを示す正面図、第6
図は寄生サイリスタの構成図、第7図(a)は電子電流
及びホール電流経路説明図、第7図(b)は経路抵抗説
明図である。
4・・・P−エピタキシャル層、4′・・・第1のnチ
ャネル、4″・・・第2のnチャネル、5・・・P°°
散層、61・・・第1のn0ソ一ス層、6.・・・第2
のnソース層、8・・・ゲート酸化膜、13・・・ソー
ス措造部、14・・・ゲート構造部。
外2名
第1
図
一一一一/3
一一一72
1 、、、p+!板
2n“エピ層
3n−エピ層
4p−エピ層
4’−nチャネル
4 nチャネル 1
5p“拡散l11
6 n+ノース 1
6、−n+ソース
7□ ■溝
71・V溝
8 ゲート酸化膜
9 ノースN極
0−ゲート電極
1 ドレイノミ極
2 バッノベーノヨノ膜
(a)
(b)
第2図
第4図
第3図
第5図FIG. 1 is a front sectional view showing an embodiment of the present invention, FIG. 2 is a voltage curve diagram in which the love stub phenomenon occurs, FIGS. 3 to 5 are front views showing different conventional voltage effect transistors, and FIG.
The figure is a configuration diagram of a parasitic thyristor, FIG. 7(a) is an explanatory diagram of electron current and hole current paths, and FIG. 7(b) is an explanatory diagram of path resistance. 4...P-epitaxial layer, 4'...first n-channel, 4''...second n-channel, 5...P°°
diffused layer, 61...first n0 source layer, 6. ...Second
8... Gate oxide film, 13... Source structure part, 14... Gate structure part. Outside 2 people 1st Figure 1111/3 11172 1 ,,,p+! Plate 2n "epi layer 3n - epi layer 4p - epi layer 4' - n channel 4 n channel 1 5p" diffusion l11 6 n + north 1 6, -n + source 7 □ ■ Groove 71 / V groove 8 Gate oxide film 9 North N Pole 0 - Gate electrode 1 Drain pole 2 Banobenoyono film (a) (b) Fig. 2 Fig. 4 Fig. 3 Fig. 5
Claims (2)
、前記第1のソース層下部に設けられた高濃度の深いP
^+拡散層と、前記第1のソース層より前記P^+拡散
層内にかけて設けられた第1のV溝と、この第1のV溝
に設けられたソース電極からなるソース構造部と、 前記第2のソース層より前記P^−層下部にかけて設け
られた第2のV溝と、この第2溝から前記ソース電極構
造部近傍にかけての上面に設けたゲート酸化膜と、この
ゲート酸化膜上に設けられたゲート電極とよりなるゲー
ト構造部と、 を備えていることを特徴とする電界効果トランジスタ。(1) The first and second source layers diffused into the P^- layer, and the highly doped deep P layer provided below the first source layer.
a source structure consisting of a ^+ diffusion layer, a first V groove provided from the first source layer into the P^+ diffusion layer, and a source electrode provided in the first V groove; a second V groove provided from the second source layer to the lower part of the P^- layer; a gate oxide film provided on the upper surface from the second groove to the vicinity of the source electrode structure; and the gate oxide film. 1. A field effect transistor comprising: a gate structure comprising a gate electrode provided thereon;
、このP^+拡散層上及び前記P^−層に拡散により第
1及び第2のn^+ソース層を形成し、この第1及び第
2のn^+ソース層に第1及び第2のV溝を設けること
を特徴とする請求項(1)記載の電界効果トランジスタ
の製造方法。(2) After forming a P^+ diffusion layer deeper than the top of the P^- layer, first and second n^+ source layers are formed by diffusion on this P^+ diffusion layer and in the P^- layer. 2. The method of manufacturing a field effect transistor according to claim 1, wherein first and second V grooves are provided in the first and second n^+ source layers.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63311547A JPH02156679A (en) | 1988-12-09 | 1988-12-09 | Field effect transistor and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63311547A JPH02156679A (en) | 1988-12-09 | 1988-12-09 | Field effect transistor and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02156679A true JPH02156679A (en) | 1990-06-15 |
Family
ID=18018550
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63311547A Pending JPH02156679A (en) | 1988-12-09 | 1988-12-09 | Field effect transistor and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02156679A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0833387A1 (en) * | 1996-09-30 | 1998-04-01 | Siemens Aktiengesellschaft | Field effect controllable semiconductor device |
WO2012106833A1 (en) | 2011-02-12 | 2012-08-16 | Freescale Semiconductor, Inc. Are | Semiconductor device and related fabrication methods |
-
1988
- 1988-12-09 JP JP63311547A patent/JPH02156679A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0833387A1 (en) * | 1996-09-30 | 1998-04-01 | Siemens Aktiengesellschaft | Field effect controllable semiconductor device |
WO2012106833A1 (en) | 2011-02-12 | 2012-08-16 | Freescale Semiconductor, Inc. Are | Semiconductor device and related fabrication methods |
JP2014508408A (en) * | 2011-02-12 | 2014-04-03 | フリースケール セミコンダクター インコーポレイテッド | Semiconductor device and related manufacturing method |
TWI557807B (en) * | 2011-02-12 | 2016-11-11 | 飛思卡爾半導體公司 | Semiconductor device and related fabrication methods |
EP2673806A4 (en) * | 2011-02-12 | 2017-12-06 | NXP USA, Inc. | Semiconductor device and related fabrication methods |
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