JPH02145978A - Phase detector - Google Patents
Phase detectorInfo
- Publication number
- JPH02145978A JPH02145978A JP63300309A JP30030988A JPH02145978A JP H02145978 A JPH02145978 A JP H02145978A JP 63300309 A JP63300309 A JP 63300309A JP 30030988 A JP30030988 A JP 30030988A JP H02145978 A JPH02145978 A JP H02145978A
- Authority
- JP
- Japan
- Prior art keywords
- phase
- input signal
- signal
- phase difference
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000016507 interphase Effects 0.000 claims abstract description 8
- 230000015654 memory Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000018199 S phase Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- YQGOJNYOYNNSMM-UHFFFAOYSA-N eosin Chemical compound [Na+].OC(=O)C1=CC=CC=C1C1=C2C=C(Br)C(=O)C(Br)=C2OC2=C(Br)C(O)=C(Br)C=C21 YQGOJNYOYNNSMM-UHFFFAOYSA-N 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Landscapes
- Power Conversion In General (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Measuring Phase Differences (AREA)
Abstract
Description
【発明の詳細な説明】
【産業上の利用分野】
この発明は、多相交流信号の周波数変化や位相変化に対
して速い応答で追従する位相検出器に関するものである
。
〔従来の技術〕
第３図は例えば特公昭６０−３７７１１号公報に示され
た従来の位相検出器の原理図を示すものであり、具体的
にはサイリスタ位相制御電力変換器装置等に適用される
ものである。図において、１は位相差△θが出力される
位相比較器、２は前記位相比較器ｌの位相差信号を増幅
する制御増幅器、３は前記制御増幅器２の出力により、
出力パルス周波数が制御される電圧−周波数変換器、４
は前記周波数変換器の出力パルスを計数するカウンタ、
５は９０°位相の異なった２相正弦波データが書き込ま
れたリードオンリメモリ（ＲＯＭ）で、カウンタ４の計
数値θ、に応じた直交２相正弦波ｅ＋ｄ （ｅ＋ｑがリ
ードオンリメモリ５とディジタル−アナログ変換器６．
７より得られる。１１は、−ｆｉに良く使用される３相
信号ｅ ＊、 ６ ｓ、 ｅアより直交した２相正弦波
ｅ。ｄ 、 ｅｏｑを演算する３相−２相変換器である
。
次に動作について説明する。まず、３相−２相変換器１
１に供給される３相信号ｅ ＩＩ、 ｅ ＩＩ、 ｅ
Ｔをとする。
この３相信号に対して、該、３相−２相変換器１１にお
いて次の相変換を行い、直交した２相信号を得る。
また、リードオンリメモリ５には、予め次の単位振幅の
直交した２相正弦波データが書き込まれている。
これら２組、の２相信号ｅｏｄ 、 ｅｏｑ及びｅ＋ｄ
。
ｅｌｑの位相差△θ＝（θ。−θ１）を求める。
Ｅｏｓｉｎ （θ。−〇＋ ） ＝ＥｏｓｉｎθＯ・
ｃｏｓθ。
−Ｅｏｃｏｓθｏ穆ｓＬｎθ
・・・（４）
（４）式より、
Ｅ。
ここで、（５）式は、次の如く近似することができる。
すなわち、
（Ａ）、ｓｉｎ△θ→△θ
（Ｂ）、入力交流信号の振幅は、はぼ一定であり、Ｅｏ
は定数として見なせる。
従って、位相差△θは
△θ＝（ｅｏｑ−ｅ＋ｄ −ｅｏｄｅ＋Ｑ ）Ｅ。
・・・（６）
となり、２組の２相信号、ｅｏ（ｌｅｏｑ及びｅ＋ｄ’
ｅ＋ｑより位相差Δθが連続的に得られる。
この位相差信号を、比例積分系などの制御増幅器２にて
増幅する。この制御増幅器２の出力により、電圧−周波
数変換器３の出力パルス周波数が制御され、この出力パ
ルスがカウンタ４にて計数される。たとえば、位相差信
号が大きな時は、制御増幅器２が電圧−周波数変換器３
の出力パルス周波数を上昇するよう動作し、位相差△θ
は減少する。
このように、位相差△θが小さくなるように単位振幅の
２相正弦波ｅｎｄとｅｌｑの位相差θ１を制御して、入
力信号の位相θ。に追従したディジタルの位相信号θ１
が得られる。
〔発明が解決しようとする課題］
従来の位相検出器は以上のように構成されているので、
通常、多相交流としてよく使用される、９０°の位相差
がない３相あるいは６相の交流に対しては、これら多相
交流信号から９０’位相の異なった２相正弦波信号を生
成しなければならず、多相−２相変換器が不可欠である
という課題があった。
この発明は上記のような課題を解消するためになされた
もので、入力の多相交流信号より９０°位相の異なった
２相正弦波信号に変換せずに、多相交流信号をそのまま
入力信号として、この入力信号の周波数変化と位相変化
とに対して速やかに追従可能な位相検出器をハードウェ
ア量の増加を抑えて得ることを目的とする。
〔課題を解消するための手段〕
この発明に係る位相検出器は多相交流のうち相間位相差
が９０°に限定されない１８０°を除く任意の２相信号
である第１の２相交流入力信号を入力し、この第１の２
相交流入力信号と同一の相間位相差をもつ第２の２相交
流入力信号を発生する２相交流発生器を備えたものであ
る。
（作用］
この発明における位相検出器は多相交流信号のうち任意
の２相信号を変換せずに第１の２相交流入力信号として
第１の２相交流入力信号の位相と検出器出力位相との位
相差を、２相交流発生器が発生する第２の２相交流入力
信号を用いて、小さ（するように制御する。
〔発明の実施例〕
以下、この発明の一実施例を図について説明する。図中
第３図と同一の部分は同一の符号をもって図示した第１
図及び第２図において、５ａ。
５ｂはリードオンリメモリ、８．９は乗算機能を有する
ディジタル−アナログ変換器、１０は減算器、１２は２
相の正弦波の相間位相差αをディジタル値で設定するα
設定器、１３はディジタル減算器である。ここで、α設
定器１２、ディジタル減算器１３及びリードオンリメモ
リ５ａ、５ｂを総称して２相交流発生器２０と呼ぶ。
次に第１図及び第２図を参照しながら動作について説明
する。まず、第１図に示す原理図にもとづいて概略説明
をする。多相信号のなかの、例えばｅｌｌ、ｅｓ（第１
の２相交流入力信号）を用いて互いの位相を検出してい
る。そこで、前記、第１の２相交流入力信号ｅＲ，ｅｍ
は（７）式で表わすことができる。
但し、αはｅＲとｅｇの位相差である。
また、リードオンリメモリ５には、交流入力信号の２相
に対応した、次の単位振幅の正弦波データが予め書き込
まれているａ ｅ＋Ｒ＋ ｅ＋ｓを第２の２相交流入力
信号とするとｅＩ＊＋ｅｒｓはそこで、これら２組の第
１、第２の２相交流入力信号の位相差△θ＝（θ。−０
１）を求める。
ｅＩＩｅ＋５−ｅａｅ＋＊＝ＥａｃＯ３θ、 −ｃｏｓ
（θ１−α）−Ｅ、ｃｏｓ （θ０−α） ｃｏｓ
θ１＝−ｓｉｎ ａ ・Ｅｏ（ｓｉｎθｏ ’ｃｏｓθ
−ｓｉｎθ＋”ＣＯ８θ。）
＝ −５ｉｎ ａ−Ｅｏ−ｓｉｎ（θ０−θ、）・・・
（９）
（９）式より、
（１０）式において、従来例と同様に次の近似を用いる
。
（Ａ）、ｓｉ口△θ押△θと見なせる。
（Ｂ）、入力交流信号の振幅は、はぼ一定であり、Ｅｏ
は定数と見なせる。また、選択された２相の相間位相差
は一定とする。
よって、ｓｉｎαも一定値である。
従って、位相差△θは
ｓｉｎ α Ｅ。
・・・（１１）
となり、信号 ｅ ＊’ｅ ｓ’ｅ ｌ＊ ’ｅ ＋ｓ
より位相差△θが連続的に得られる。
但し、ｓｆｎα％ｏでなければならないのでα特１８０
＠ とする。
位相差△θを検出してからの動作は、従来例と同様なの
で、説明を省略する。
次に、第２図のブロック図にもとづいて動作について説
明する。
ｅ６とｅ＋ｓ、ｅｓとｅｌ、を入力として乗算機能を持
つディジタル−アナログ変換器８，９と減算器１０によ
り、前記（１１）式の位相差△θを求める演算が行なわ
れ、位相差ｓｉｎα・Ｅ０△θが求まる。この位相差信
号は制御増幅器２にて増幅され、電圧−周波数変換器３
の出力パルス周波数が制御される。この出力パルス周波
数はカウンタ４によって計数され、その計数値θ、に応
じて前記第２の２相交流入力信号ｅ＋ｓ’ｅ＋＋＋を発
生する２相交流発生器２０が作動する。すなわち、リー
ドオンリメモリ５ａはｅｒ＊＝ｃＯ８θ１を出力する。
また、α設定器１２は第１の２相交流入力信号ｅｌｌｅ
、の相間位相差αを設定し、減算器１３にて計数値θ１
をθ、−αとして、リードオンリメモリ５ｂに与える。
このリードオンリメモリ５ｂは、前記リードオンリメモ
リ５ａと同一のデータが書き込まれており、ｅＩｓ＝ｃ
ｏｓ （θ−α）を出力する。
このようにして２相交流発生器２０を構成することによ
り、第２の２相交流入力信号ｅＩ３・ｅ＋ｓとの相間位
相差αを、α設定器１２にて設定するだけで、他の部分
は回路変更なしに第１の２相交流入力信号ｅ、ｌｅ、を
、多相交流のうち相間位相差が１８０°を除（ものから
任意に選択して使用することができる。
〔発明の効果〕
以上のように、この発明によれば、２相交流発生器の出
力信号の相間位相差を、２相交流入力信号の相間位相差
に一致させることにより、２相交流入力信号の相間位相
差は９０°に限定されず、１８０°を除（任意の相間位
相差に選べるので、多相交流信号のうち相間位相差が１
８０°を除く任意の２相信号をそのまま２相交流入力信
号として用いることができ、多相−２相変換器等の付加
回路を削減できる効果がある。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase detector that follows frequency changes and phase changes of a multiphase alternating current signal with a fast response. [Prior Art] Fig. 3 shows a principle diagram of a conventional phase detector disclosed in, for example, Japanese Patent Publication No. 60-37711. Specifically, it is applied to a thyristor phase control power converter device, etc. It is something that In the figure, 1 is a phase comparator that outputs a phase difference Δθ, 2 is a control amplifier that amplifies the phase difference signal of the phase comparator l, and 3 is an output of the control amplifier 2.
a voltage-to-frequency converter whose output pulse frequency is controlled; 4;
is a counter that counts the output pulses of the frequency converter;
5 is a read-only memory (ROM) in which two-phase sine wave data with a 90° phase difference is written, and the orthogonal two-phase sine wave e+d (e+q is read-only memory 5 and -Analog converter6.
Obtained from 7. 11 is a two-phase sine wave e that is orthogonal to the three-phase signals e*, 6s, and e, which are often used for -fi. This is a three-phase to two-phase converter that calculates d and eoq. Next, the operation will be explained. First, 3-phase to 2-phase converter 1
1 three-phase signal e II, e II, e
Let T be. The three-phase to two-phase converter 11 performs the following phase conversion on this three-phase signal to obtain orthogonal two-phase signals. Further, the following orthogonal two-phase sine wave data of unit amplitude is written in advance in the read-only memory 5. These two sets of two-phase signals eod, eoq and e+d
. Find the phase difference Δθ=(θ.−θ1) of elq. Eosin (θ.-〇+) = EosinθO・
cos θ. −EocosθosLnθ (4) From equation (4), E. Here, equation (5) can be approximated as follows. That is, (A), sin△θ→△θ (B), the amplitude of the input AC signal is approximately constant, and Eo
can be regarded as a constant. Therefore, the phase difference Δθ is Δθ=(eoq−e+d−eode+Q)E. ...(6) Then, two sets of two-phase signals, eo(leoq and e+d'
The phase difference Δθ is continuously obtained from e+q. This phase difference signal is amplified by a control amplifier 2 such as a proportional-integral system. The output pulse frequency of the voltage-frequency converter 3 is controlled by the output of the control amplifier 2, and the output pulses are counted by a counter 4. For example, when the phase difference signal is large, the control amplifier 2 is connected to the voltage-frequency converter 3.
operates to increase the output pulse frequency, and the phase difference △θ
decreases. In this way, the phase difference θ1 between the unit amplitude two-phase sine waves end and elq is controlled so that the phase difference Δθ is small, and the phase θ of the input signal is adjusted. Digital phase signal θ1 following
is obtained. [Problem to be solved by the invention] Since the conventional phase detector is configured as described above,
Normally, for three-phase or six-phase AC without a 90° phase difference, which is often used as polyphase AC, two-phase sine wave signals with a 90' phase difference are generated from these polyphase AC signals. Therefore, there was a problem in that a polyphase-to-two-phase converter was indispensable. This invention was made to solve the above-mentioned problems, and it converts the input polyphase AC signal as it is into the input signal without converting it into a two-phase sine wave signal with a phase difference of 90 degrees from the input polyphase AC signal. An object of the present invention is to obtain a phase detector that can quickly follow the frequency change and phase change of this input signal while suppressing an increase in the amount of hardware. [Means for Solving the Problems] The phase detector according to the present invention receives a first two-phase AC input signal which is any two-phase signal other than 180° in which the inter-phase phase difference is not limited to 90° among polyphase AC. and enter this first 2
It is equipped with a two-phase AC generator that generates a second two-phase AC input signal having the same interphase phase difference as the phase AC input signal. (Function) The phase detector according to the present invention does not convert any two-phase signal among the multiphase AC signals, and uses the phase of the first two-phase AC input signal and the detector output phase as the first two-phase AC input signal. The second two-phase AC input signal generated by the two-phase AC generator is used to control the phase difference between the two-phase AC input signal to be small. In the figure, the same parts as in Fig. 3 are designated by the same reference numerals.
In the figure and FIG. 2, 5a. 5b is a read-only memory, 8.9 is a digital-to-analog converter with a multiplication function, 10 is a subtracter, and 12 is a 2
Set the interphase phase difference α of the phase sine wave with a digital value α
The setter 13 is a digital subtracter. Here, the α setter 12, the digital subtracter 13, and the read-only memories 5a and 5b are collectively referred to as a two-phase AC generator 20. Next, the operation will be explained with reference to FIGS. 1 and 2. First, a general explanation will be given based on the principle diagram shown in FIG. For example, ell, es (first
The two-phase AC input signal) is used to detect each other's phases. Therefore, the first two-phase AC input signal eR,em
can be expressed by equation (7). However, α is the phase difference between eR and eg. Further, in the read-only memory 5, sine wave data of the following unit amplitude corresponding to the two phases of the AC input signal is written in advance.If ae+R+e+s is the second two-phase AC input signal, eI*+ers Therefore, the phase difference between these two sets of first and second two-phase AC input signals Δθ=(θ.−0
Find 1). eIIe+5-eae+*=EacO3θ, -cos
(θ1-α)-E, cos (θ0-α) cos
θ1=-sin a ・Eo(sinθo 'cosθ
-sinθ+"CO8θ.) = -5in a-Eo-sin(θ0-θ,)...
(9) From equation (9), in equation (10), the following approximation is used as in the conventional example. (A), it can be regarded as si mouth △θ push △θ. (B), the amplitude of the input AC signal is approximately constant, and Eo
can be considered a constant. Further, it is assumed that the phase difference between the two selected phases is constant. Therefore, sin α is also a constant value. Therefore, the phase difference Δθ is sin αE. ...(11) The signal e *'e s'e l* 'e +s
Therefore, the phase difference Δθ can be continuously obtained. However, since it must be sfnα%o, α special 180
@. The operation after detecting the phase difference Δθ is the same as that of the conventional example, so the explanation will be omitted. Next, the operation will be explained based on the block diagram shown in FIG. Using e6 and e+s, es and el as inputs, the digital-to-analog converters 8 and 9 with multiplication functions and the subtracter 10 perform calculations to obtain the phase difference Δθ in equation (11), and the phase difference sinα・E0Δθ is found. This phase difference signal is amplified by a control amplifier 2, and a voltage-frequency converter 3
The output pulse frequency of is controlled. This output pulse frequency is counted by a counter 4, and a two-phase AC generator 20 that generates the second two-phase AC input signal e+s'e+++ is activated in accordance with the counted value θ. That is, the read-only memory 5a outputs er*=cO8θ1. Further, the α setting device 12 receives the first two-phase AC input signal elle
, and the subtracter 13 calculates the count value θ1.
are given to the read-only memory 5b as θ and −α. This read-only memory 5b is written with the same data as the read-only memory 5a, and eIs=c
Output os (θ−α). By configuring the two-phase AC generator 20 in this way, the phase difference α between the phases with the second two-phase AC input signal eI3/e+s is only set by the α setting device 12, and the other parts are Without changing the circuit, the first two-phase AC input signals e, le can be arbitrarily selected and used from polyphase AC with an inter-phase phase difference of 180°. [Effects of the Invention] As described above, according to the present invention, by matching the phase difference between the output signals of the two-phase AC generator with the phase difference between the two-phase AC input signals, the phase difference between the two-phase AC input signals can be reduced. It is not limited to 90°, but is divided by 180° (any phase difference between phases can be selected, so if the phase difference between phases is 1 in a multiphase AC signal)
Any two-phase signal other than 80° can be used as it is as a two-phase AC input signal, and there is an effect that additional circuits such as a polyphase-to-two-phase converter can be reduced.
第１図はこの発明の一実施例を示す位相検出器の原理図
、第２図は第１図の細部構成を示すブロック図、第３図
は従来の位相検出器を示す原理図である。
図において、１は位相比較器、２は制御増幅器、３は電
圧−周波数変換器、４はカウンタ、２０は２相交流発生
器である。
なお、図中、同一符号は同一、又は相当部分を示す。
特許出願人 三菱電機株式会社FIG. 1 is a principle diagram of a phase detector showing an embodiment of the present invention, FIG. 2 is a block diagram showing the detailed configuration of FIG. 1, and FIG. 3 is a principle diagram showing a conventional phase detector. In the figure, 1 is a phase comparator, 2 is a control amplifier, 3 is a voltage-frequency converter, 4 is a counter, and 20 is a two-phase AC generator. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant Mitsubishi Electric Corporation
Claims (1)
信号を第１の２相交流入力信号とする一方、前記第１の
２相交流入力信号と同じ相間位相差を有する他の２相交
流を第２の２相交流入力信号とし、前記第１の２相交流
入力信号と前記第２の２相交流入力信号との位相差を検
出する位相比較器と、 前記位相比較器によって検出された前記第１及び第２の
２相交流入力信号の位相差を増幅する制御増幅器と、 前記制御増幅器の出力信号に対応する周波数を発生する
電圧−周波数変換器と、 前記電圧−周波数変換器の出力周波数を計数するカウン
タと、 前記カウンタの計数値に応じて前記２相交流を発生する
２相交流発生器とを備えた位相検出器。[Scope of Claims] Any two-phase signal of polyphase alternating current except for an inter-phase phase difference of 180° is used as the first two-phase AC input signal; a phase comparator that uses another two-phase AC input signal having a phase difference as a second two-phase AC input signal and detects a phase difference between the first two-phase AC input signal and the second two-phase AC input signal; a control amplifier that amplifies the phase difference between the first and second two-phase AC input signals detected by the phase comparator; and a voltage-frequency converter that generates a frequency corresponding to the output signal of the control amplifier. A phase detector comprising: a counter that counts the output frequency of the voltage-frequency converter; and a two-phase AC generator that generates the two-phase AC according to the count value of the counter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63300309A JPH0783584B2 (en) | 1988-11-28 | 1988-11-28 | Phase detector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63300309A JPH0783584B2 (en) | 1988-11-28 | 1988-11-28 | Phase detector |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02145978A true JPH02145978A (en) | 1990-06-05 |
| JPH0783584B2 JPH0783584B2 (en) | 1995-09-06 |
Family
ID=17883227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63300309A Expired - Lifetime JPH0783584B2 (en) | 1988-11-28 | 1988-11-28 | Phase detector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0783584B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017223642A (en) * | 2016-06-14 | 2017-12-21 | アナログ・デヴァイシズ・グローバル | Method and apparatus for learning phase error or timing delay within current transducer, and power measurement apparatus including current transducer error correction |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6037711A (en) * | 1983-08-10 | 1985-02-27 | 三洋電機株式会社 | Method of producing film capacitor |
-
1988
- 1988-11-28 JP JP63300309A patent/JPH0783584B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6037711A (en) * | 1983-08-10 | 1985-02-27 | 三洋電機株式会社 | Method of producing film capacitor |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017223642A (en) * | 2016-06-14 | 2017-12-21 | アナログ・デヴァイシズ・グローバル | Method and apparatus for learning phase error or timing delay within current transducer, and power measurement apparatus including current transducer error correction |
| JP2020073904A (en) * | 2016-06-14 | 2020-05-14 | アナログ・デヴァイシズ・グローバル・アンリミテッド・カンパニー | Method and apparatus for learning phase error or timing delay within current transducer, and power measurement apparatus including current transducer error correction |
| CN111707863A (en) * | 2016-06-14 | 2020-09-25 | 亚德诺半导体集团 | Method and apparatus for learning phase errors of current transformers and power measurement devices including current transformer error correction |
| JP2021121802A (en) * | 2016-06-14 | 2021-08-26 | アナログ・デヴァイシズ・グローバル・アンリミテッド・カンパニー | Method and apparatus for learning phase error or timing delay within current transducer, and power measurement apparatus including current transducer error correction |
| CN111707863B (en) * | 2016-06-14 | 2023-03-24 | 亚德诺半导体国际无限责任公司 | Method and apparatus for learning phase errors of current transformers and power measurement devices including current transformer error correction |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0783584B2 (en) | 1995-09-06 |
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