JPH0213957B2 - - Google Patents

Info

Publication number
JPH0213957B2
JPH0213957B2 JP61005645A JP564586A JPH0213957B2 JP H0213957 B2 JPH0213957 B2 JP H0213957B2 JP 61005645 A JP61005645 A JP 61005645A JP 564586 A JP564586 A JP 564586A JP H0213957 B2 JPH0213957 B2 JP H0213957B2
Authority
JP
Japan
Prior art keywords
copper
substrate
sides
conductive
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61005645A
Other languages
Japanese (ja)
Other versions
JPS62163395A (en
Inventor
Sandai Iwasa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Chemical Laboratory Co Ltd
Original Assignee
Asahi Chemical Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Chemical Laboratory Co Ltd filed Critical Asahi Chemical Laboratory Co Ltd
Priority to JP61005645A priority Critical patent/JPS62163395A/en
Priority to US06/947,437 priority patent/US4735676A/en
Priority to FR878700274A priority patent/FR2593016B1/en
Priority to KR1019870000192A priority patent/KR900003152B1/en
Priority to GB8700717A priority patent/GB2186434B/en
Priority to DE19873700910 priority patent/DE3700910A1/en
Priority to NL8700078A priority patent/NL8700078A/en
Publication of JPS62163395A publication Critical patent/JPS62163395A/en
Publication of JPH0213957B2 publication Critical patent/JPH0213957B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095—Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/167—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0209—Inorganic, non-metallic particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09763—Printed component having superposed conductors, but integrated in one circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1423—Applying catalyst before etching, e.g. plating catalyst in holes before etching circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/428—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates having a metal pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4685—Manufacturing of cross-over conductors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Description

【発明の詳細な説明】 技術分野 本発明は、基板に導電回路を形成する方法に係
り、特に新規開発された銅めつき性の良好な銅導
電ペーストを有効に利用し、基板の両面に少なく
とも４層の導電回路を形成することができ、しか
も抵抗ペーストによる超薄型の抵抗回路又は誘電
体ペーストによる超薄型の蓄電回路を可能とし得
る画期的な方法に関する。Detailed Description of the Invention Technical Field The present invention relates to a method of forming a conductive circuit on a substrate, and in particular, effectively utilizes a newly developed copper conductive paste with good copper plating properties to form a conductive circuit on both sides of the substrate. The present invention relates to an innovative method that can form a four-layer conductive circuit and also enables an ultra-thin resistance circuit using resistance paste or an ultra-thin storage circuit using dielectric paste.

従来技術 従来、銅貼積層基板に抵抗回路又は蓄電回を形
成するには、リード線付又はチツプ型の抵抗器又
はコンデンサを銅箔回路に半田付けする方法が採
用されていた。このため完成品としての基板の厚
さが大きくなるばかりでなく、コンデンサの取付
けや半田付け作業に多くの工数がかかり、また抵
抗器やコンデンサ自体のコストもかなり高いた
め、抵抗回路又は蓄電回路を含むプリント配線基
板が高価となる欠点があつた。またこのような従
来例によると、プリント配線基板の実装密度が低
く、軽量化、製造工程の省力化も極めて困難であ
り、半田付け作業が不可欠のため、誤配線や抵抗
器又はコンデンサの挿入ミスが生ずるおそれがあ
つた。Prior Art Conventionally, in order to form a resistance circuit or a storage circuit on a copper-clad laminated board, a method has been adopted in which a lead wire-equipped or chip-type resistor or capacitor is soldered to a copper foil circuit. This not only increases the thickness of the finished board, but also requires a lot of man-hours to install and solder the capacitors, and the cost of the resistors and capacitors themselves is quite high. The drawback was that the printed wiring board involved was expensive. In addition, according to such conventional examples, the packaging density of the printed wiring board is low, making it extremely difficult to reduce weight and save labor in the manufacturing process, and soldering work is essential, resulting in incorrect wiring and incorrect insertion of resistors or capacitors. There was a risk that this would occur.

また従来、銅箔を用いたプリント基板において
は、そこに形成される導電回路がある程度以上複
雑となると、該導電回路のある部分と他の部分と
を電気的に接続する必要性が生ずるが、従来技術
ではプリント基板の片面に２層以上の導電回路を
工業的に形成することはできなかつたので、この
場合両面スルホール基板を用いていたが、該両面
スルホール基板を用いた場合でも、両面に合計２
層の導電回路を形成できるのが限度であつた。 Conventionally, in printed circuit boards using copper foil, when the conductive circuit formed there becomes complicated beyond a certain level, it becomes necessary to electrically connect one part of the conductive circuit to another part. With conventional technology, it was not possible to industrially form two or more conductive circuits on one side of a printed circuit board, so a double-sided through-hole board was used in this case. Total 2
There was a limit to the ability to form conductive circuits in layers.

なおセラミツクス基板を用いた場合には、従来
から片面に２層以上の導電回路を形成する提案が
なされているが、例えばハイブリツドICの場合
には導電回路及び端子に白金−パラジウム又は銀
−パラジウムの貴金属ペースト類を使用し、抵抗
体の主成分には酸化ルテニウム系のペースト類を
印刷し、高温焼成（700〜1000℃）して回路を形
成する方法が主流である。またアルミナグリーン
シートにタングステン（Ｗペースト）と絶縁ペー
ストを交互に印刷して回路を形成してできたもの
を1600℃前後で焼成して基板の片面に２層以上の
導電回路を形成することも提案されているが、こ
れらの高温焼成を必要とする方法では、各部を構
成する材料が限定され、また設備費も高くつく欠
点があり、電子機器の一般用プリント配線基板に
は使用し難い欠点があつた。 When using a ceramic substrate, proposals have been made to form two or more conductive circuits on one side. The mainstream method is to use noble metal pastes, print a ruthenium oxide paste as the main component of the resistor, and then bake it at a high temperature (700 to 1000 degrees Celsius) to form a circuit. It is also possible to form a circuit by alternately printing tungsten (W paste) and insulating paste on an alumina green sheet and firing it at around 1600℃ to form two or more conductive circuits on one side of the board. However, these methods, which require high-temperature firing, have the disadvantage that the materials that can be used for each part are limited and the equipment costs are high, making them difficult to use for general-purpose printed wiring boards for electronic devices. It was hot.

そこで上記した従来方法の欠点を改良するもの
として、例えばポリマ基板等の低温処理を対象と
したプリント基板の片面に２層以上の導電回路を
工業的に形成する技術の確立が望まれるが、その
ためには導電性及び金属めつき性、特に銅めつき
性が良好な安価な銅導電ペーストの開発が必要と
された。しかしながら、この銅導電ペーストによ
ると、ペーストを硬化させるための加熱（150℃
前後）が必要となるが、銅はその特性から銀等の
貴金属とは逆に極めて酸化し易いため、この加熱
によつてペースト中の銅粉末が酸化して電気抵抗
が大きくなると共に半田付性が悪化するという欠
点があり、実用化が困難とされていた。また加熱
硬化された銅導電ペーストに金属めつきを施すに
は、通常その表面をキヤタリスト（触媒）を用い
て活性化し、バインダとしての樹脂層から銅粉の
粒子を露出させ、いわゆるめつきの核を作る工程
が必要とされ、多くの工数がかかる欠点があつ
た。 Therefore, in order to improve the drawbacks of the conventional methods described above, it is desired to establish a technology for industrially forming two or more layers of conductive circuits on one side of a printed circuit board intended for low-temperature processing, such as a polymer board. Therefore, it was necessary to develop an inexpensive copper conductive paste with good conductivity and metal plating properties, especially copper plating properties. However, according to this copper conductive paste, heating to harden the paste (150℃
However, due to its characteristics, copper is extremely susceptible to oxidation, contrary to precious metals such as silver, so this heating oxidizes the copper powder in the paste, increasing electrical resistance and reducing solderability. However, it has been considered difficult to put it into practical use because of the disadvantage that it causes deterioration. In addition, in order to apply metal plating to heat-cured copper conductive paste, the surface is usually activated using a catalyst to expose the copper powder particles from the resin layer as a binder and remove the so-called plating core. The drawback was that it required a manufacturing process and took a lot of man-hours.

なお、実公昭55−42460には、片面に２層以上
の導電回路を形成するため、絶縁被膜層に高絶縁
性レジストポリブタジエンを用い、銅被膜で被覆
する下地回路に例えばフエノール樹脂20％、銅粉
63％及び溶剤17％からなる接着剤ペーストを用
い、該接着剤ペーストに無電解めつき法で20μｍ
まで肉付けを行い、銅被膜を被着させる考案が開
示されてはいるが、上記のような理由により、該
考案が工業的に実施された例はないのが現状であ
る。 In addition, in order to form two or more layers of conductive circuits on one side, in Utility Model Publication No. 55-42460, highly insulating resist polybutadiene is used for the insulating coating layer, and for example, 20% phenol resin and copper are used for the base circuit covered with the copper coating. powder
Using an adhesive paste consisting of 63% and 17% solvent, the adhesive paste was coated with a thickness of 20 μm by electroless plating.
Although an idea has been disclosed in which the copper coating is applied by adding flesh to the surface, for the reasons mentioned above, there is currently no example of this idea being implemented industrially.

本願出願人においては、上記のような欠点をす
べて除去し得る銅導電ペーストを開発すべく、多
年にわたり研究を行つて来たが、遂にこれを完成
し、その工業化に成功したものである。それは、
銅粉末と合成樹脂に加えて特殊添加剤として例え
ばアントラセンを微量添加したもので、(株)アサヒ
化学研究所製銅導電ペーストACP−020、ACP−
030及びACP−007Pとして実用化の段階に至らし
めたものである。ACP−020なる銅導電ペースト
は、銅粉末80重量％、合成樹脂20重量％を主成分
とし、導電性の極めて良好なものであるが、半田
付性がやや劣るものである。ACP−030なる銅導
電ペーストは、銅粉末85重量％、合成樹脂15重量
％を主成分とし、導電性はACP−020より若干劣
るが半田付性が良好なものである。またACP−
007Pなる銅導電ペーストは、このACP−030を改
良し、キヤタリストなしで金属めつき、例えば銅
の化学めつきをその硬化塗膜の上に施すことがで
きるようにしたもので、金属めつき性の非常に優
れたものである。 The applicant of the present application has been conducting research for many years in order to develop a copper conductive paste that can eliminate all of the above-mentioned drawbacks, and has finally completed this and succeeded in commercializing it. it is,
Copper conductive paste ACP-020, ACP- manufactured by Asahi Chemical Laboratory Co., Ltd. is made by adding a small amount of special additives such as anthracene in addition to copper powder and synthetic resin.
It has reached the stage of practical use as 030 and ACP-007P. The copper conductive paste called ACP-020 mainly consists of 80% by weight of copper powder and 20% by weight of synthetic resin, and has extremely good conductivity, but has somewhat poor solderability. The copper conductive paste called ACP-030 mainly contains 85% by weight of copper powder and 15% by weight of synthetic resin, and although its conductivity is slightly inferior to that of ACP-020, it has good solderability. Also ACP−
Copper conductive paste 007P is an improved version of ACP-030 that allows metal plating, such as copper chemical plating, to be applied on the cured coating without the need for catalysts, and has excellent metal plating properties. It is very good.

目 的 本発明は、上記した従来技術の欠点を除くと共
に、上記新開発された銅めつき性の良好な銅導電
ペーストを有効に用いるためになされたものであ
つて、その目的とするところは、銅貼積層基板に
形成された銅箔からなる第１層導電回路のうち第
２層導電回路と電気的に接続する必要がある部分
にのみ上記新開発された金属めつき性の良好な銅
導電ペーストを塗布して加熱硬化させ、その上に
銅の化学めつき等の金属めつきを施し、該銅導電
ペーストの導電性を銅箔と同程度に向上させて、
第２層導電回路となし、銅箔を用いたプリント基
板等の基板の片面に電気的に接続された少なくと
も２層の導電回路を形成することであり、またこ
れによつて両面に少なくとも４層の導電回路を形
成し得るようにし、両面スルホール基板における
導電回路の形成工程を飛躍的に簡略化し、また完
成品としてのプリント基板のコストを従来品の約
１／２に低減させることである。また他の目的は、
基板両面の耐めつきレジスト上に所定の電気抵抗
値を有する抵抗ペーストを塗布して加熱硬化さ
せ、該抵抗ペーストとその両側の第１層導電回路
又は第２層導電回路とを電気的に接続するように
導電性の良好な端子用導電ペーストを塗布して加
熱硬化させて基板の両面に抵抗回路を形成し、次
いでスルホール内周面を活性化処理して、ここに
無電解銅めつきを施し、基板両面の第１層導電回
路を電気的に接続し、基板の両面に抵抗回路を含
む少なくとも４層の導電回路を形成することによ
り、従来の抵抗器、その基板への挿入又は接着作
業及び半田付け作業を不要とすることであり、ま
たこれによつて超薄型の抵抗回路を提供すること
である。更に他の目的は、第１層導電回路又は第
２層導電回路の一部に蓄電作用を有する誘電体ペ
ーストを塗布して加熱硬化させ、該誘電体ペース
トと耐めつきレジストにより絶縁された第１層導
電回路又は第２層導電回路とを電気的に接続する
ように導電性の良好な端子用導電ペーストを塗布
して加熱硬化させて基板の両面に蓄電回路を形成
し、次いでスルホール内周面を活性化処理してこ
こに無電解銅めつきを施し、基板両面の第１層導
電回路を電気的に接続し、基板の両面に蓄電回路
を含む少なくとも４層の導電回路を形成すること
により、従来のコンデンサ、その基板への挿入又
は接着作業及び半田付け作業を不要とすることで
あり、またこれによつて超薄型の蓄電回路を形成
することである。また他の目的は、このように基
板の両面に抵抗回路又は蓄電回路を含む少なくと
も４層の導電回路を形成することにより、プリン
ト配線基板の実装密度の向上、軽量化及び製造工
程の省力化を図り、また誤配線や抵抗器やコンデ
ンサの挿入ミスのおそれをなくし、プリント配線
基板の抵抗回路及び蓄電回路の信頼性を向上さ
せ、コストの低減を図ることである。Purpose The present invention has been made to eliminate the drawbacks of the prior art described above and to effectively use the newly developed copper conductive paste with good copper plating properties. Of the first layer conductive circuit made of copper foil formed on the copper-clad laminated board, the above-mentioned newly developed copper with good metal plating properties is applied only to the part that needs to be electrically connected to the second layer conductive circuit. A conductive paste is applied and cured by heating, and metal plating such as copper chemical plating is applied thereon to improve the conductivity of the copper conductive paste to the same level as copper foil.
A second layer of conductive circuit is to form at least two layers of conductive circuit electrically connected to one side of a board such as a printed circuit board using copper foil, and thereby to form at least four layers of conductive circuit on both sides. The purpose of the present invention is to dramatically simplify the process of forming a conductive circuit on a double-sided through-hole board, and to reduce the cost of a finished printed circuit board to about 1/2 of that of a conventional product. In addition, other purposes are
A resistance paste having a predetermined electrical resistance value is applied onto the resist-resistant resist on both sides of the substrate and cured by heating, and the resistance paste and the first layer conductive circuit or the second layer conductive circuit on both sides are electrically connected. A conductive paste for terminals with good conductivity is applied and cured by heating to form a resistance circuit on both sides of the board.Then, the inner peripheral surface of the through hole is activated and electroless copper plating is applied thereto. The conventional resistor, its insertion or gluing operation into the substrate, by electrically connecting the first layer conductive circuits on both sides of the substrate and forming at least four layers of conductive circuits including resistive circuits on both sides of the substrate. Another object of the present invention is to eliminate the need for soldering work, and thereby provide an ultra-thin resistor circuit. Still another object is to apply a dielectric paste having a charge storage function to a part of the first layer conductive circuit or the second layer conductive circuit and heat it to harden it, and to apply a dielectric paste having a charge storage function to a part of the first layer conductive circuit or the second layer conductive circuit, and to heat and harden the dielectric paste, and to form a second layer insulated by the dielectric paste and the plating resist. A conductive paste for terminals with good conductivity is applied and cured by heating to electrically connect the first-layer conductive circuit or the second-layer conductive circuit to form power storage circuits on both sides of the board, and then the inner periphery of the through-hole is coated. Activating the surface and applying electroless copper plating thereon, electrically connecting the first layer conductive circuits on both sides of the substrate, and forming at least four layers of conductive circuits including power storage circuits on both sides of the substrate. This eliminates the need for conventional capacitors, the work of inserting or gluing them onto a board, and the work of soldering, and thereby forms an ultra-thin power storage circuit. Another purpose is to improve the mounting density of printed wiring boards, reduce weight, and save labor in the manufacturing process by forming at least four layers of conductive circuits, including resistor circuits or storage circuits, on both sides of the board. The purpose of the present invention is to eliminate the risk of incorrect wiring or incorrect insertion of resistors or capacitors, improve the reliability of the resistance circuits and power storage circuits of printed wiring boards, and reduce costs.

構 成 要するに本発明（第１発明）は、両面銅貼積層
基板にスルホールの穴あけ加工を施してキヤタリ
スト処理を行い、次いで前記基板を水洗、乾燥
し、該基板の両面の銅箔にエツチング加工を施し
て銅箔による複数の第１層導電回路を該基板の両
面に形成し、該第１層導電回路の部分を残して前
記基板の両面に耐めつきレジストを塗布して加熱
硬化させ、前記基板の両面の前記複数の第１層導
電回路の一部を電気的に互いに接続するように、
多孔質海綿状の微粉末からなる銅粉とバインダと
してのエポキシ樹脂とを混合したものに酸化防止
用の添加剤としてアントラセン、アントラセンカ
ルボン酸、アントラジン及びアントラニル酸より
選ばれたいずれか１種のものを添加してなる銅め
つき性の良好な銅導電ペーストを塗布して加熱硬
化させ、この状態で前記基板にめつき前処理を施
して後、前記銅導電ペーストの表面に化学銅めつ
きを施し、該銅めつき層と該銅導電ペーストとに
より第２層導電回路を前記基板の両面に形成し、
次いで前記スルホール及びその周囲の前記第１層
導電回路の部分を残して耐めつきレジストを塗布
して加熱硬化させ、前記スルホール内周面を対象
とした活性化処理を施して後、該スルホール内周
面に無電解銅めつきを施し、前記基板の両面の前
記第１層導電回路を該銅めつき層で接続し、該基
板の両面に少なくとも４層の導電回路を形成する
ことを特徴とするものである。Structure In short, the present invention (first invention) involves drilling through-holes in a double-sided copper-clad laminate board, performing catalyst processing, washing the board with water, drying it, and etching the copper foils on both sides of the board. A plurality of first-layer conductive circuits made of copper foil are formed on both sides of the substrate, and a plating resist is applied to both sides of the substrate, leaving the first-layer conductive circuits, and cured by heating. so as to electrically connect parts of the plurality of first layer conductive circuits on both sides of the substrate to each other,
A mixture of copper powder consisting of porous spongy fine powder and epoxy resin as a binder, and one selected from anthracene, anthracenecarboxylic acid, anthrazine and anthranilic acid as an antioxidant additive. Copper conductive paste with good copper plating properties is applied and cured by heating, and in this state, the substrate is subjected to plating pretreatment, and then chemical copper plating is applied to the surface of the copper conductive paste. applying the copper plating layer and the copper conductive paste to form a second layer conductive circuit on both sides of the substrate,
Next, a plating resist is applied to the through hole and the first layer conductive circuit around it, and is cured by heating. After performing an activation treatment targeting the inner circumferential surface of the through hole, the inside of the through hole is Electroless copper plating is applied to the peripheral surface, the first layer conductive circuits on both sides of the substrate are connected by the copper plating layer, and at least four layers of conductive circuits are formed on both sides of the substrate. It is something to do.

また本発明（第２発明）は、両面銅貼積層基板
にスルホールの穴あけ加工を施してキヤタリスト
処理を行い、次いで前記基板を水洗、乾燥し、該
基板の両面の銅箔にエツチング加工を施して銅箔
による複数の第１層導電回路を該基板の両面に形
成し、該第１層導電回路の部分を残して前記基板
の両面に耐めつきレジストを塗布して加熱硬化さ
せ、前記基板の両面の前記複数の第１層導電回路
の一部を互いに電気的に接続するように、多孔質
海綿状の微粉末からなる銅粉とバインダとしての
エポキシ樹脂とを混合したものに酸化防止用の添
加剤としてアントラセン、アントラセンカルボン
酸、アントラジン及びアントラニル酸より選ばれ
たいずれか１種のものを添加してなる銅めつき性
の良好な銅導電ペーストを塗布して加熱硬化さ
せ、この状態で前記基板にめつき前処理を施して
後、前記銅導電ペーストの表面に化学銅めつきを
施し、該銅めつき層と該銅導電ペーストとにより
第２層導電回路を前記基板の両面に形成し、次い
で前記基板両面の耐めつきレジスト上に所定の電
気抵抗値を有する抵抗ペーストを塗布して加熱硬
化させ、該抵抗ペーストとその両側の前記第１層
導電回路又は第２層導電回路とを電気的に接続す
るように導電性の良好な端子用導電ペーストを塗
布して加熱硬化させて前記基板の両面に抵抗回路
を形成し、次いで前記スルホール及びその周囲の
前記第１層導電回路の部分を残して耐めつきレジ
ストを塗布して加熱硬化させ、前記スルホール内
周面を対象とした活性化処理を施して後、該スル
ホール内周面に無電解銅めつきを施し、前記基板
の両面の前記第１層導電回路を該銅めつき層で電
気的に接続し、該基板の両面に前記抵抗回路を含
む少なくとも４層の導電回路を形成することを特
徴とするものである。 The present invention (second invention) also provides a double-sided copper-clad laminated board that is subjected to catalyst processing by drilling through holes, then washing and drying the board, and etching the copper foils on both sides of the board. A plurality of first-layer conductive circuits made of copper foil are formed on both sides of the substrate, and a plating resist is applied to both sides of the substrate, leaving the first-layer conductive circuits, and cured by heating. A mixture of copper powder made of porous spongy fine powder and epoxy resin as a binder is added with anti-oxidation so as to electrically connect parts of the plurality of first layer conductive circuits on both sides to each other. Copper conductive paste with good copper plating properties containing one selected from anthracene, anthracenecarboxylic acid, anthrazine, and anthranilic acid as an additive is applied and cured by heating, and in this state, the above-mentioned After performing plating pretreatment on the substrate, chemical copper plating is applied to the surface of the copper conductive paste, and a second layer conductive circuit is formed on both sides of the substrate by the copper plating layer and the copper conductive paste. Then, a resistance paste having a predetermined electrical resistance value is applied onto the resist-plating resist on both sides of the substrate and cured by heating, thereby bonding the resistance paste and the first layer conductive circuit or the second layer conductive circuit on both sides thereof. A conductive paste for terminals with good conductivity is applied and cured by heating to form a resistive circuit on both sides of the substrate for electrical connection, and then the through hole and the portion of the first layer conductive circuit around the through hole are formed. After applying a plating-resistant resist and curing it by heating, and performing an activation treatment targeting the inner circumferential surface of the through hole, electroless copper plating is applied to the inner circumferential surface of the through hole, and both sides of the substrate are coated with a plating resist. The first layer conductive circuit is electrically connected by the copper plating layer, and at least four layers of conductive circuits including the resistance circuit are formed on both sides of the substrate.

また本発明（第３発明）は、両面銅貼積層基板
にスルホールの穴あけ加工を施してキヤタリスト
処理を行い、次いで前記基板を水洗、乾燥し、該
基板の両面の銅箔にエツチング加工を施して銅箔
による複数の第１層導電回路を該基板の両面に形
成し、該第１層導電回路の部分を残して前記基板
の両面に耐めつきレジストを塗布して加熱硬化さ
せ、前記基板の両面の前記複数の第１層導電回路
の一部を互いに電気的に接続するように、多孔質
海綿状の微粉末からなる銅粉とバインダとしての
エポキシ樹脂とを混合したものに酸化防止用の添
加剤としてアントラセン、アントラセンカルボン
酸、アントラジン及びアントラニル酸より選ばれ
たいずれか１種のものを添加してなる銅めつき性
の良好な銅導電ペーストを塗布して加熱硬化さ
せ、この状態で前記基板にめつき前処理を施して
後、前記銅導電ペーストの表面に化学銅めつきを
施し、該銅めつき層と該銅導電ペーストとにより
第２層導電回路を前記基板の両面に形成し、次い
で前記第１層導電回路又は第２層導電回路の一部
に蓄電作用を有する誘電体ペーストを塗布して加
熱硬化させ、該誘電体ペーストと前記耐めつきレ
ジストとにより絶縁された前記第１層導電回路又
は第２層導電回路とを電気的に接続するように導
電性の良好な端子用導電ペーストを塗布して加熱
硬化させて前記基板の両面に蓄電回路を形成し、
次いで前記スルホール及びその周囲の前記第１層
導電回路の部分を残して耐めつきレジストを塗布
して加熱硬化させ、前記スルホール内周面を対象
とした活性化処理を施して後、該スルホール内周
面に無電解銅めつきを施し、前記基板の両面の前
記第１層導電回路を該銅めつき層で電気的に接続
し、該基板の両面に前記蓄電回路を含む少なくと
も４層の導電回路を形成することを特徴とするも
のである。 The present invention (third invention) also provides a double-sided copper-clad laminated board that is subjected to catalyst processing by drilling through-holes, then washed and dried with water, and etched the copper foils on both sides of the board. A plurality of first-layer conductive circuits made of copper foil are formed on both sides of the substrate, and a plating resist is applied to both sides of the substrate, leaving the first-layer conductive circuits, and cured by heating. A mixture of copper powder made of porous spongy fine powder and epoxy resin as a binder is added with anti-oxidation so as to electrically connect parts of the plurality of first layer conductive circuits on both sides to each other. Copper conductive paste with good copper plating properties containing one selected from anthracene, anthracenecarboxylic acid, anthrazine, and anthranilic acid as an additive is applied and cured by heating, and in this state, the above-mentioned After performing plating pretreatment on the substrate, chemical copper plating is applied to the surface of the copper conductive paste, and a second layer conductive circuit is formed on both sides of the substrate by the copper plating layer and the copper conductive paste. Next, a dielectric paste having a charge storage effect is applied to a part of the first layer conductive circuit or the second layer conductive circuit and cured by heating. Applying a terminal conductive paste with good conductivity so as to electrically connect the first layer conductive circuit or the second layer conductive circuit and curing it by heating to form a storage circuit on both sides of the substrate,
Next, a plating resist is applied to the through hole and the first layer conductive circuit around it, and is cured by heating. After performing an activation treatment targeting the inner circumferential surface of the through hole, the inside of the through hole is Electroless copper plating is applied to the peripheral surface, the first layer conductive circuits on both sides of the substrate are electrically connected by the copper plating layer, and at least four conductive layers including the power storage circuit are formed on both sides of the substrate. It is characterized by forming a circuit.

また本発明（第３発明）は、両面銅貼積層基板
にスルホールの穴あけ加工を施してキヤタリスト
処理を行い、次いで前記基板を水洗、乾燥し、該
基板の両面の銅箔にエツチング加工を施して銅箔
による複数の第１層導電回路を該基板の両面に形
成し、該第１層導電回路の部分を残して前記基板
の両面に耐めつきレジストを塗布して加熱硬化さ
せ、前記基板の両面の前記複数の第１層導電回路
の一部を互いに電気的に接続するように銅めつき
性の良好な銅導電ペーストを塗布して加熱硬化さ
せ、この状態で前記基板にめつき前処理を施して
後、前記銅導電ペーストの表面に化学銅めつきを
施し、該銅めつき層と該銅導電ペーストとにより
第２層導電回路を前記基板の両面に形成し、次い
で前記第１層導電回路又は第２層導電回路の一部
に蓄電作用を有する誘電体ペーストを塗布して加
熱硬化させ、該誘電体ペーストと前記耐めつきレ
ジストにより絶縁された前記第１層導電回路又は
第２層導電回路とを電気的に接続するように導電
性の良好な端子用導電ペーストを塗布して加熱硬
化させて前記基板の両面に蓄電回路を形成し、次
いで前記スルホール及びその周囲の前記第１層導
電回路の部分を残して耐めつきレジストを塗布し
て加熱硬化させ、前記スルホール内周面を対象と
した活性化処理を施して後、該スルホール内周面
に無電解銅めつきを施し、前記基板の両面の前記
第１層導電回路を該銅めつき層で電気的に接続
し、該基板の両面に前記蓄電回路を含む少なくと
も４層の導電回路を形成することを特徴とするも
のである。 The present invention (third invention) also provides a double-sided copper-clad laminated board that is subjected to catalyst processing by drilling through-holes, then washed and dried with water, and etched the copper foils on both sides of the board. A plurality of first-layer conductive circuits made of copper foil are formed on both sides of the substrate, and a plating resist is applied to both sides of the substrate, leaving the first-layer conductive circuits, and cured by heating. A copper conductive paste with good copper plating properties is applied and cured by heating so as to electrically connect parts of the plurality of first layer conductive circuits on both sides to each other, and in this state, the substrate is subjected to plating pretreatment. After applying chemical copper plating to the surface of the copper conductive paste, a second layer conductive circuit is formed on both sides of the substrate by the copper plating layer and the copper conductive paste, and then the first layer conductive circuit is formed on both sides of the substrate. A dielectric paste having a charge storage effect is applied to a part of the conductive circuit or the second layer conductive circuit and cured by heating, and the first layer conductive circuit or the second layer is insulated by the dielectric paste and the plating resist. A conductive paste for terminals having good conductivity is coated and cured by heating so as to electrically connect the layered conductive circuit, and a power storage circuit is formed on both sides of the substrate. A plating-resistant resist is applied, leaving the layer conductive circuit portion, and cured by heating. After performing an activation treatment targeting the inner peripheral surface of the through hole, electroless copper plating is applied to the inner peripheral surface of the through hole. , wherein the first layer conductive circuits on both sides of the substrate are electrically connected by the copper plating layer, and at least four layers of conductive circuits including the power storage circuit are formed on both sides of the substrate. It is.

以下本発明を図面に示す実施例に基いて説明す
る。まず第１図から第１１図により特定発明の方
法について説明すると、最初に第１図に示すよう
に、ポリマ基板等の基板１の両面に銅箔８を貼り
つけて両面銅貼積層基板３を形成する。次に第２
図に示すように、両面銅貼積層基板３にスルホー
ル４の穴あけ加工を施して、次いで第３図に示す
ように、キヤタリスト処理を行い、両面銅貼積層
基板３の両面及びスルホール４の内周面４ａに黒
点で示すような金属微粒子５を付着させる。この
キヤタリスト処理は、塩化パラジウム（PdCl2）、
塩化錫（SnCl2）の触媒液又はパラジウムのみの
アルカリ性触媒液などで、両面銅貼積層基板３の
面を処理し、上記したようにその表面にパラジウ
ム等の金属微粒子５を付着させ、これを核として
無電解銅めつきにおける銅を析出させる処理であ
る。この場合パラジウムと銅は共に金属であり、
両物質の間に界面を作るためのエネルギーはほと
んど必要がなく、両物質の原子配列の周期が略一
致（共に面心立方格子で、格子定数もパラジウム
と銅で3.8898Å、3.6150Åとかなり近い）してい
るので、コロイド状パラジウムの上に銅が次々と
析出することになり、このような金属微粒子５の
上に銅めつきを施すことができるのである。 The present invention will be explained below based on embodiments shown in the drawings. First, the method of the specified invention will be explained with reference to FIGS. 1 to 11. First, as shown in FIG. Form. Then the second
As shown in the figure, through-holes 4 are drilled in the double-sided copper-clad laminated board 3, and then, as shown in FIG. Fine metal particles 5 as shown by black dots are attached to the surface 4a. This catalyst treatment consists of palladium chloride (PdCl 2 ),
The surface of the double-sided copper-laminated substrate 3 is treated with a catalytic solution of tin chloride (SnCl 2 ) or an alkaline catalytic solution containing only palladium, and fine metal particles 5 such as palladium are attached to the surface as described above. This is a process in which copper is deposited as a nucleus in electroless copper plating. In this case palladium and copper are both metals,
Almost no energy is required to create an interface between the two materials, and the periods of the atomic arrangement of both materials are almost the same (both are face-centered cubic lattices, and the lattice constants are also quite similar, 3.8898 Å and 3.6150 Å for palladium and copper. ), copper is deposited one after another on the colloidal palladium, making it possible to perform copper plating on such fine metal particles 5.

なお本明細書においては、上記のようなキヤタ
リスト処理を施してから化学銅めつきを行う方法
を「無電解銅めつき」と称し、銅導電ペーストの
上にキヤタリスト処理なしで化学銅めつきを施す
方法を「化学銅めつき」と称して区別することに
する。 In this specification, the method of performing chemical copper plating after the catalyst treatment as described above is referred to as "electroless copper plating," and refers to the method of chemical copper plating on copper conductive paste without catalyst treatment. The method of applying copper plating will be referred to as ``chemical copper plating.''

このようにしてキヤタリスト処理が終了した
後、第４図に示すように両面銅貼積層基板３を水
洗して乾燥し、銅箔８の表面についた金属微粒子
５を洗い落とし、スルホール４の内周面４ａに付
着した金属微粒子５だけを残して、第５図に示す
ように第１層導電回路C1を形成しない部分３ａ
を残して耐エツチングレジスト７を両面銅貼積層
基板３の銅箔に塗布してエツチング加工を施し、
銅箔８による複数の第１層導電回路C1を基板１
の両面に形成する。この場合スルホール４の周囲
には必ず第１層導電回路C1が形成されるように
する。 After the catalyst processing is completed in this way, the double-sided copper-clad laminated board 3 is washed with water and dried, as shown in FIG. The part 3a that does not form the first layer conductive circuit C1 is left as shown in FIG.
An etching-resistant resist 7 is applied to the copper foil of the double-sided copper-clad laminated board 3, leaving .
A plurality of first layer conductive circuits C 1 made of copper foil 8 are connected to the substrate 1.
Form on both sides. In this case, the first layer conductive circuit C 1 is always formed around the through hole 4 .

次に、両面銅貼積層基板３の両面のうち第１層
導電回路C1を形成しない部分３ａに第７図に示
すように、耐めつきレジスト６（例えば(株)アサヒ
化学研究所製耐めつきレジストCR−2001）を塗
布し、例えば150℃で30分間加熱して硬化させる。
そして第８図に示すように、両面銅貼積層基板３
の両面の複数の第１層導電回路C1の一部を互い
に電気的に接続するように、銅めつき性の良好な
銅導電ペースト９（例えば(株)アサヒ化学研究所製
銅導電ペーストACP−007P）をスクリーン印刷
により塗布して、温度150℃にて30乃至60分間加
熱して硬化させる。 Next, as shown in FIG . 7, a plating resist 6 (for example, a plating resist manufactured by Asahi Chemical Laboratory Co., Ltd.) is applied to a portion 3a of both sides of the double-sided copper-clad laminate board 3 where the first layer conductive circuit C1 is not formed. Plating resist CR-2001) is applied and cured by heating, for example, at 150°C for 30 minutes.
Then, as shown in FIG.
A copper conductive paste 9 with good copper plating properties (for example, copper conductive paste ACP manufactured by Asahi Chemical Research Institute Co., Ltd.) is used to electrically connect parts of the plurality of first layer conductive circuits C 1 on both sides of the -007P) is applied by screen printing and cured by heating at a temperature of 150°C for 30 to 60 minutes.

そしてこの状態で両面銅貼積層基板３にめつき
前処理を施す。このめつき前処理は、例えばカ性
ソーダ（NaOH）の４乃至５重量％の水溶液で
数分間洗浄し、塩酸（HCl）５乃至10重量％の水
溶液で数分間表面処理を行う。この表面処理によ
つて銅導電ペースト９の表面にはそのバインダの
間から銅粉の粒子が多数表面に現われ、銅めつき
を行うための核が容易に形成される。従つて通常
の無電解銅めつきにおけるようなキヤタリスト処
理は不要である。 In this state, the double-sided copper-clad laminate board 3 is subjected to plating pretreatment. This pre-plating treatment includes, for example, cleaning for several minutes with a 4 to 5% by weight aqueous solution of caustic soda (NaOH), and surface treatment for several minutes with a 5 to 10% by weight aqueous solution of hydrochloric acid (HCl). By this surface treatment, many particles of copper powder appear between the binders on the surface of the copper conductive paste 9, and nuclei for copper plating are easily formed. Therefore, catalyst treatment as in ordinary electroless copper plating is not necessary.

次に、両面銅貼積層基板３を化学銅めつき浴に
浸して銅導電ペースト９の表面に、第９図に示す
ように化学銅めつきを施し、この結果銅めつき層
１０が形成され、該銅めつき層によつて第２層導
電回路C2が形成され、該第２層導電回路C2は第
１層導電回路C1と電気的に接続される。この化
学銅めつき浴はPH11乃至13、温度65乃至75℃で銅
めつき層１０の厚さは5μｍ以上とする。この場
合のめつき速度は毎時1.5乃至3μｍである。 Next, the double-sided copper laminated board 3 is immersed in a chemical copper plating bath to apply chemical copper plating to the surface of the copper conductive paste 9 as shown in FIG. 9, and as a result, a copper plating layer 10 is formed. A second layer conductive circuit C2 is formed by the copper plating layer, and the second layer conductive circuit C2 is electrically connected to the first layer conductive circuit C1 . This chemical copper plating bath has a pH of 11 to 13, a temperature of 65 to 75°C, and a thickness of the copper plating layer 10 of 5 μm or more. The plating speed in this case is 1.5 to 3 μm per hour.

次いで第１０図に示すように、スルホール４及
びその周囲の第１層導電回路C1の部分を残して
耐めつきレジスト６を塗布して加熱硬化させ、ス
ルホール４の内周面４ａを対象とした活性化処理
を施して後、第１１図に示すように、両面銅貼積
層基板の両面の第１層導電回路C1を銅めつき層
１０で接続し、両面銅貼積層基板３の両面に少な
くとも４層の導電回路C1，C2を形成する。即ち
両面銅貼積層基板３の両面の第１層導電回路C1
はスルホール４の内周面４ａに形成された銅めつ
き層１０により電気的に接続される。 Next, as shown in FIG. 10, a plating resist 6 is applied and heated to cure the through hole 4 and the first layer conductive circuit C 1 around it, leaving the through hole 4 and the first layer conductive circuit C 1 around it. After carrying out the activation treatment, as shown in FIG. At least four layers of conductive circuits C 1 and C 2 are formed. That is, the first layer conductive circuit C 1 on both sides of the double-sided copper-clad laminate board 3
are electrically connected by a copper plating layer 10 formed on the inner peripheral surface 4a of the through hole 4.

このようにして銅めつき層１０と銅導電ペース
ト９とにより第２層導電回路C2を両面銅貼積層
基板３の両面に形成することができ、該基板の両
面に少なくとも４層の導電回路C1，C2が形成さ
れ、第１１図に示すようなプリント配線基板１２
が完成する。 In this way, the second layer conductive circuit C2 can be formed on both sides of the double-sided copper-clad laminated board 3 using the copper plating layer 10 and the copper conductive paste 9, and at least four layers of conductive circuits are formed on both sides of the board. C 1 and C 2 are formed, and a printed wiring board 12 as shown in FIG.
is completed.

以上のようにして、本発明（特定発明）によれ
ば、サブトラクテイブ法及びアデイテイブ法を組
み合わせて用いることによつて、両面銅貼積層基
板３の両面に少なくとも４層の導電回路C1，C2
を容易に形成することができるものである。 As described above, according to the present invention (specific invention), at least four layers of conductive circuits C 1 , C 2 are formed on both sides of the double-sided copper-clad laminate board 3 by using a combination of the subtractive method and the additive method.
can be easily formed.

次に、第１図から第９図及び第１２図から第１
５図により、第２発明の方法について説明する
と、第９図に示すように、両面銅貼積層基板３の
両面に第１層導電回路C1及び第２層導電回路C2
を形成するまでの工程は特定発明と全く同一であ
るので、これについては説明は省略し、第１２図
から第１５図に示す抵抗回路１３の形成工程につ
いて説明する。第１２図において、両面銅貼積層
基板３の両面の耐めつきレジスト６上に所定の電
気抵抗値を有する抵抗ペースト１４を塗布してこ
れを加熱硬化させ、次に第１３図に示すように、
該抵抗ペースト１４とその両側の第１層導電回路
C1とを電気的に接続するように、導電性の良好
な端子用導電ペースト１５（例えば銀ペースト）
を塗布して加熱硬化させて両面銅貼積層基板３の
両面に抵抗回路１３を形成し、該基板の両面に該
抵抗回路１３を含む少なくとも４層の導電回路
C1，C2を形成するものである。 Next, from Fig. 1 to Fig. 9 and Fig. 12 to Fig. 1
The method of the second invention will be explained with reference to FIG . 5. As shown in FIG .
Since the steps up to the formation of the resistor circuit 13 are exactly the same as those of the specific invention, the explanation thereof will be omitted, and the steps of forming the resistor circuit 13 shown in FIGS. 12 to 15 will be explained. In FIG. 12, a resistive paste 14 having a predetermined electrical resistance value is applied onto the plating resist 6 on both sides of the double-sided copper-clad laminate board 3 and cured by heating, and then as shown in FIG. ,
The resistor paste 14 and the first layer conductive circuit on both sides thereof
Conductive paste 15 for terminals with good conductivity (for example, silver paste) to electrically connect C 1
is coated and heated to cure to form resistance circuits 13 on both sides of the double-sided copper-clad laminated board 3, and at least four layers of conductive circuits including the resistance circuits 13 are formed on both sides of the board.
It forms C 1 and C 2 .

次いで第１４図に示すように、スルホール４及
びその周囲の第１層導電回路C1の部分を残して
耐めつきレジスト６を第１０図と同様に塗布して
加熱硬化させ、スルホール４の内周面４ａを対象
とした活性化処理を施して後、第１５図に示すよ
うに、スルホール４の内周面４ａに無電解銅めつ
きを施し、ここに銅めつき層１０を形成して両面
銅貼積層基板３の両面の第１層導電回路C1を該
銅めつき層１０で接続し、両面銅貼積層基板３の
両面に抵抗回路１３を含む少なくとも４層の導電
回路C1，C2を形成し、第１５図に示すようなプ
リント配線基板２２が完成する。このようにして
第２発明によれば、抵抗回路１３を含む少なくと
も４層の導電回路C1，C2が両面銅貼積層基板３
の両面にサブトラクテイブ法及びアデイテイブ法
の組み合わせによつて形成される。 Next, as shown in FIG. 14, a plating resist 6 is applied in the same manner as in FIG. 10, leaving the through hole 4 and the first layer conductive circuit C 1 around it, and hardened by heating to fill the inside of the through hole 4. After performing the activation treatment targeting the peripheral surface 4a, as shown in FIG. 15, electroless copper plating is applied to the inner peripheral surface 4a of the through hole 4, and a copper plating layer 10 is formed thereon. The first layer conductive circuits C 1 on both sides of the double-sided copper-clad laminated board 3 are connected by the copper plating layer 10, and at least four layers of conductive circuits C 1 including resistance circuits 13 are formed on both sides of the double-sided copper-clad laminated board 3. C 2 is formed, and a printed wiring board 22 as shown in FIG. 15 is completed. In this way, according to the second invention, at least four layers of conductive circuits C 1 and C 2 including the resistance circuit 13 are connected to the double-sided copper-clad laminated board 3.
It is formed on both sides by a combination of subtractive and additive methods.

次に、第１図から第９図及び第１６図から第１
９図により第３発明の方法について説明すると、
第２発明の場合と同様に第１図から第９図までの
第１層導電回路C1及び第２層導電回路C2を形成
する工程は全く同一であるので、これについての
説明は省略し、第１６図から第１９図に示す蓄電
回路１６の形成工程について説明する。まず第１
６図に示すように、第１層導電回路C1又は第２
層導電回路C2の一部（第１６図に示すものは第
１層導電回路C1のみ）に蓄電作用を有する誘電
体ペースト１８を塗布してこれを加熱硬化させ、
第１７図に示すように、該誘電体ペースト１８と
耐めつきレジスト６により絶縁された隣接の第１
層導電回路C1とを電気的に接続するように、導
電性の良好な端子用導電ペースト１９（例えば銀
ペースト）を塗布して加熱硬化させ、両面銅貼積
層基板３の両面に蓄電回路１６を形成し、次いで
第１８図に示すようにスルホール４及びその周囲
の第１層導電回路C1の部分を残して耐めつきレ
ジスト６を塗布して加熱硬化させ、スルホール４
の内周面４ａを対象とした活性化処理を施して
後、第１９図に示すように、スルホール４の内周
面４ａに無電解銅めつきを施し、両面銅貼積層基
板３の両面の第１層導電回路C1を銅めつき層１
０で電気的に接続し、両面銅貼積層基板３の両面
に蓄電回路１６を含む少なくとも４層の導電回路
C1，C2を形成するものである。 Next, from Fig. 1 to Fig. 9 and Fig. 16 to Fig. 1
The method of the third invention will be explained with reference to Figure 9.
As in the case of the second invention, the steps of forming the first layer conductive circuit C 1 and the second layer conductive circuit C 2 from FIGS. 1 to 9 are exactly the same, so a description thereof will be omitted. , the formation process of the power storage circuit 16 shown in FIGS. 16 to 19 will be explained. First of all
As shown in Figure 6, the first layer conductive circuit C1 or the second layer
A dielectric paste 18 having a charge storage function is applied to a part of the layered conductive circuit C2 (the one shown in FIG. 16 is only the first layered conductive circuit C1 ), and this is heated and cured.
As shown in FIG.
A terminal conductive paste 19 (for example, silver paste) with good conductivity is applied and cured by heating so as to electrically connect the layer conductive circuit C 1 to the power storage circuit 16 on both sides of the double-sided copper-laminated board 3. Then, as shown in FIG. 18, a plating resist 6 is applied and heated to cure the through hole 4 and the first layer conductive circuit C 1 around it, leaving the through hole 4 and the first layer conductive circuit C 1 around it.
After performing the activation treatment targeting the inner peripheral surface 4a of the through hole 4, electroless copper plating is applied to the inner peripheral surface 4a of the through hole 4, as shown in FIG. 1st layer conductive circuit C 1 with copper plating layer 1
At least four layers of conductive circuits electrically connected at 0 and including storage circuits 16 on both sides of the double-sided copper-laminated board 3
It forms C 1 and C 2 .

なお上記において、端子用導電ペースト１９は
図中耐めつきレジスト６の右側の第１層導電回路
C1にのみ接続したが、これは第２層導電回路C2
にも接続してよいことは明らかである。 In the above, the terminal conductive paste 19 is used as the first layer conductive circuit on the right side of the plating resist 6 in the figure.
Although only connected to C 1 , this is the second layer conductive circuit C 2
It is clear that you can also connect to

以上のように本発明（第２発明）によればサブ
トラクテイブ法及びアデイテイブ法の組合せによ
つて両面銅貼積層基板３の両面に蓄電回路１６を
含む少なくとも４層の導電回路C1，C2を形成す
ることができ、第１９図に示すようなプリント配
線基板３２が完成する。 As described above, according to the present invention (second invention), at least four layers of conductive circuits C 1 and C 2 including the storage circuit 16 are formed on both sides of the double-sided copper-clad laminated board 3 by a combination of subtractive and additive methods. A printed wiring board 32 as shown in FIG. 19 is completed.

なお、上記実施例においては、両面銅貼積層基
板３の片面に２層の導電回路C1，C2を形成する
ものとして説明したが、これは２層に限定される
ものではなく、耐めつきレジスト６の上に更に上
記の工程を繰り返すことにより片面に３層以上、
両面に合計６層以上の導電回路を形成できること
は明らかである。 In the above embodiment, the two-layer conductive circuits C 1 and C 2 are formed on one side of the double-sided copper-clad laminated board 3, but this is not limited to two layers, and By repeating the above steps on top of the resist resist 6, three or more layers are formed on one side.
It is clear that a total of six or more conductive circuit layers can be formed on both sides.

次に、本発明に用いる上記銅導電ペースト、抵
抗ペースト、誘電体ペースト及び耐めつきレジス
トについて詳細に説明する。 Next, the copper conductive paste, resistance paste, dielectric paste, and plating resist used in the present invention will be explained in detail.

まず銅導電ペーストの一例たる(株)アサヒ化学研
究所製ACP−007Pなる銅めつき性の良好な銅導
電ペーストについて説明する。一般に銅は酸化さ
れ易い金属であり、特に粉末においては表面積が
大きいためより酸化し易い。従つて非酸化性貴金
属粉末を用いる貴金属ペーストと異なり、銅粒子
の酸化膜の除去と再酸化防止とができるペースト
組成物の設計が必要となる。銅化学めつきがし易
くて、しかも基材に対する接着性が高い銅導電ペ
ーストを設計するにはその構成成分である銅粉
末、バインダ、酸化防止用の特殊添加剤（例えば
アントラセン、アントラセンカルボン酸、アント
ラジン、アントラニル酸が有効）、分散剤及び溶
剤等の材料選択と適切な分散混練技術とが重要な
ポイントである。 First, a copper conductive paste with good copper plating properties called ACP-007P manufactured by Asahi Chemical Research Institute, Ltd., which is an example of a copper conductive paste, will be explained. Generally, copper is a metal that is easily oxidized, and in particular, copper is more easily oxidized in powder form because it has a large surface area. Therefore, unlike noble metal pastes that use non-oxidizing noble metal powders, it is necessary to design a paste composition that can remove the oxide film on copper particles and prevent re-oxidation. In order to design a copper conductive paste that is easy to chemically plate with copper and has high adhesion to the base material, the components such as copper powder, binder, and special additives for anti-oxidation (such as anthracene, anthracene carboxylic acid, The important points are the selection of materials such as anthrazine and anthranilic acid), dispersants and solvents, and appropriate dispersion and kneading techniques.

銅粉末はその製法によつて粒子の形状や粒径が
異なり、電解法（電気分解によつて粉末状に銅を
析出させる方法）では樹枝状で純度の高い粉末
が、還元性（酸化物を還元性ガスで還元させて作
る方法）では、海綿状の多孔質な微粒子が提供さ
れる。そして上記した本発明の導電回路を形成す
るためには銅導電ペーストは次のような特性を備
えていなければならない。 Copper powder differs in particle shape and particle size depending on its manufacturing method, and in the electrolytic method (a method in which copper is deposited in powder form by electrolysis), the dendritic and highly pure powder has a reducing property (oxidation In the method (method of production by reduction with a reducing gas), spongy porous fine particles are provided. In order to form the above-described conductive circuit of the present invention, the copper conductive paste must have the following characteristics.

(1) スクリーン印刷性がよく、フアインパターン
が形成できること。(1) Good screen printability and ability to form fine patterns.

(2) 基板との密着性に優れていること。(2) Excellent adhesion to the substrate.

(3) 化学銅めつきの高温アルカリ浴に耐えるこ
と。(3) To withstand the high temperature alkaline bath of chemical copper plating.

(4) 銅めつきとよく密着すること。(4) Good adhesion to copper plating.

(5) 経時変化による粘度変化が少なく、安定した
印刷性が得られること。(5) Stable printability with little viscosity change over time.

このような要求を満たすため上記銅導電ペース
トは、銅紛末としては、電気分解によつて析出す
る樹枝状粉を多く含み、純度の高い電解銅粉と、
金属酸化物から還元して作つた多孔質海綿状の微
粉末等を使用している。またこれらの銅粉をフレ
ーク状に加工した粉末（粉砕粉）も使用される。 In order to meet such requirements, the copper conductive paste contains high-purity electrolytic copper powder, which contains a large amount of dendritic powder precipitated by electrolysis.
It uses porous spongy fine powder made by reducing metal oxides. Powders obtained by processing these copper powders into flakes (pulverized powders) are also used.

銅粉末のペースト中への含率を高めるために
は、粒径や形状の異なる粒子を、最密充填するよ
うに配合することが必要となる。 In order to increase the content of copper powder in the paste, it is necessary to mix particles with different particle sizes and shapes in a close-packed manner.

次に銅導電ペーストのバインダについて説明す
ると、バインダは、多量の粉末の分散ベヒクルと
して、また基板への強力な接着剤として働く必要
があり、同時に化学銅めつきのアルカリ浴に十分
耐えるものでなければならない。 Next, regarding the binder in the copper conductive paste, the binder must act as a dispersion vehicle for large quantities of powder, as a strong adhesive to the substrate, and at the same time must be sufficiently resistant to the alkaline bath of chemical copper plating. It won't happen.

そこでバインダとしては、銅粉末含率が大き
く、銅箔及びガラスエポキシ基板への密着性及び
めつきの析出性が極めて良好で、更にめつき膜の
密着性が極めて良好なエポキシ樹脂を配合したも
のを用いる。 Therefore, we selected a binder containing an epoxy resin that has a high copper powder content, has very good adhesion to copper foil and glass epoxy substrates, and has very good plating precipitation, and also has very good adhesion to the plating film. use

次に上記(株)アサヒ化学研究所製銅導電ペースト
ACP−007Pに析出した銅めつきの特性について
その一例を説明すると、色調、形状は赤褐色かつ
ペースト状であり、粘度は25℃において300乃至
500psであり、銅箔上及び樹脂基板上の接着性は
何れもテープテストに合格するものであり、銅め
つき後めつきと銅導電ペーストとの接着性はテー
プテスト合格であり、半田付性は拡がり率が96％
以上で、引張り強度（３×３mm2）は3.0Kg以上で
ある。 Next, the above-mentioned copper conductive paste made by Asahi Chemical Laboratory Co., Ltd.
An example of the characteristics of copper plating deposited on ACP-007P is that the color and shape are reddish brown and paste-like, and the viscosity is 300 to 300 at 25℃.
500 ps, the adhesion on copper foil and resin board both passed the tape test, and the adhesion between plating after copper plating and copper conductive paste passed the tape test, and the solderability has a spread rate of 96%
With the above, the tensile strength (3×3 mm 2 ) is 3.0 Kg or more.

なお、上記銅導電ペーストの構成成分及び導電
特性等についての詳細は本願出願人の出願である
特願昭55−6609（特開昭56−103260）及び特願昭
60−216041に詳細に説明されているのでその説明
は省略する。 Further, details regarding the constituent components and conductive properties of the above-mentioned copper conductive paste can be found in Japanese Patent Application No. 55-6609 (Japanese Unexamined Patent Publication No. 56-103260) filed by the present applicant.
60-216041, so the explanation will be omitted.

次に本発明に用いる抵抗ペーストについて説明
すると、抵抗ペーストの材料組成には導電材料と
して高純度精製カーボン、グラフアイト等の微粉
末が用いられ、結合剤としてエポキシ、フエノー
ル、メラミン、アクリル等の熱硬化性樹脂が使用
される。更に抵抗ペーストの粘度調整用として揮
発性の遅い高沸点溶剤を使用する。 Next, to explain the resistance paste used in the present invention, the material composition of the resistance paste includes fine powders such as highly purified carbon and graphite as conductive materials, and heat-resistant materials such as epoxy, phenol, melamine, and acrylic as binders. A curable resin is used. Furthermore, a slow volatile high boiling point solvent is used to adjust the viscosity of the resistance paste.

抵抗ペーストの製造に際しては夫々の成分に対
して数多くの特性が要求される。例えば機能性粉
体の特性としては、粒子が細かく均一なこと、純
度が高く高品質なこと、抵抗値のバラツキが少な
いこと及び粉体の配合樹脂とのなじみがよいこと
である。 When manufacturing a resistive paste, a number of properties are required for each component. For example, the characteristics of a functional powder include fine and uniform particles, high purity and high quality, little variation in resistance, and good compatibility with the blended resin of the powder.

次にポリマとしての特性は、粉体との相溶性が
よいこと、常温放置しても膜張りを起こさないこ
と、常温放置しても抵抗値が変動しないこと、常
温で硬化せず加熱により速かに硬化すること、硬
化膜は温度、湿度により体積変化を起こしにくい
こと、若干のフレキシビリテーを有し、基材との
密着性に優れていること、耐熱性、耐湿性に優れ
ていること及びアンダコート、オーバコート剤と
の層間密着性に優れていることである。 Next, the properties of the polymer are that it has good compatibility with powder, does not form a film even when left at room temperature, does not change its resistance value even when left at room temperature, and does not harden at room temperature and is quickly heated when heated. The cured film is hard to change in volume due to temperature and humidity, has some flexibility, has excellent adhesion to the base material, and has excellent heat resistance and moisture resistance. Also, it has excellent interlayer adhesion with undercoat and overcoat agents.

次に溶剤特性としては、連続印刷に対しての安
定性に優れていること（版の目詰りや乳剤膜を侵
さないこと）、常温での蒸発速度が遅く水分を吸
着しないこと、常温±10℃前後で粘度が急激に変
化しないこと及び常温又は加熱時での蒸気は刺激
臭や毒性がないことである。 Next, the solvent properties are that it has excellent stability for continuous printing (does not clog the plate or attack the emulsion film), has a slow evaporation rate at room temperature and does not adsorb moisture, and has a temperature of ±10% at room temperature. The viscosity does not change rapidly around ℃, and the steam at room temperature or when heated has no irritating odor or toxicity.

このような諸条件を満たす抵抗ペーストとし
て、例えば(株)アサヒ化学研究所製抵抗ペースト
TU−1Kは、半田付け後の抵抗変化率については
半田付け温度240℃と260℃の２点で0.5％程度の
非常にわずかな変化率であり、実用に際しても信
頼性に優れたものである。またこのTU−1Kなる
抵抗ペーストは、示差熱分析曲線についても、半
田付け温度までに急激な吸熱、発熱反応を示さな
いので、そのための抵抗体の体積変化が極めて小
さいものと推定される。 As a resistance paste that satisfies these conditions, for example, resistance paste manufactured by Asahi Chemical Research Institute Co., Ltd.
The resistance change rate of TU-1K after soldering is very small, about 0.5% at the two soldering temperatures of 240°C and 260°C, and it has excellent reliability even in practical use. . Also, the differential thermal analysis curve of this TU-1K resistor paste shows no rapid endothermic or exothermic reactions up to the soldering temperature, so it is presumed that the volume change of the resistor due to this is extremely small.

次に、誘電体ペーストについて説明すると、本
発明で用いる誘電体ペーストは、チツプコンデン
サの規格のうち、種類１及び種類２に対応し得る
ものとして開発されたもので、その静電容量は
100乃至1000pFである。その製法は、チタン酸バ
リウム（BaTiO3）を焼いてフレーク状又は板状
にして、これを粉砕して粒径２乃至10μｍの粉体
として、これをバインダに50重量％以上で混合
し、有機剤を混合して３本ロールで練合分散させ
てペースト状とする。バインダとしては、フエノ
ール、エポキシ、メラミン等の樹脂を用い、溶剤
としては、ブチルカルビトールを主成分とし、そ
の他カルビトール又はブチルセルソール等を用い
る。 Next, to explain the dielectric paste, the dielectric paste used in the present invention was developed to be compatible with Type 1 and Type 2 of the chip capacitor standards, and its capacitance is
It is 100 to 1000 pF. Its manufacturing method involves baking barium titanate (BaTiO 3 ) into flakes or plates, pulverizing this into powder with a particle size of 2 to 10 μm, mixing it with a binder at 50% by weight or more, and adding organic The ingredients are mixed and kneaded and dispersed using three rolls to form a paste. As the binder, a resin such as phenol, epoxy, or melamine is used, and as the solvent, butyl carbitol is used as the main component, and carbitol, butyl cellulol, etc. are used as the solvent.

次に、耐めつきレジストについて説明すると、
本発明では(株)アサヒ化学研究所製CR−2001なる
耐めつきレジストを用いるが、この耐めつきレジ
ストは、多層配線基板回路を形成しようとすると
き、第１層導電回路に第２層導電回路を接続して
は不都合な場合、第１層導電回路の上に耐めつき
レジストを印刷法により被覆するが、絶縁性が良
好であると同時に、特に耐アルカリ性に優れた性
質が要求される。化学銅めつき浴と同じPH12のア
ルカリ浴中、70℃にて４時間以上の酸性を持つ耐
めつきレジストとして開発されたのがこのCR−
2001なる耐めつきレジストである。 Next, I will explain about the resistant resist.
In the present invention, a plating resist called CR-2001 manufactured by Asahi Chemical Research Institute Co., Ltd. is used. If it is inconvenient to connect a conductive circuit, a plating resist is coated on the first layer conductive circuit by a printing method, but at the same time it requires good insulation properties and particularly excellent alkali resistance. Ru. CR- was developed as a plating resist that can withstand acidity for more than 4 hours at 70℃ in an alkaline bath with a pH of 12, which is the same as a chemical copper plating bath.
2001 is a durable resist.

これは銅導電ペーストACP−007Pと同様な、
エポキシ樹脂を主成分とするペーストで、180メ
ツシユのポリエステルスクリーンを用いて印刷
し、150℃にて30分間加熱して硬化させる。耐薬
品性、耐電圧性から15乃至30μｍ程度の厚膜が好
ましい。その主な特長は以下のようである。即
ち、基材に対する密着力が強く、また銅箔に対す
る接着性に優れており、耐アルカリ性（PH12）に
長時間浸しても硬化膜が劣化せず、ハードナは毒
性の弱いアルカリ性であるので使用上安全であ
る。またこの耐めつきレジストの使用方法は、塗
布方法についはスクリーン印刷により、混合比率
を主剤100ｇに対して硬化剤が10ｇである。また
硬化条件は、温度範囲が150乃至200℃、設定時間
が30乃至15分である。 This is similar to copper conductive paste ACP-007P.
A paste whose main component is epoxy resin, printed using a 180-mesh polyester screen, and cured by heating at 150℃ for 30 minutes. A thick film of about 15 to 30 μm is preferable from the viewpoint of chemical resistance and voltage resistance. Its main features are as follows. In other words, it has strong adhesion to the base material and excellent adhesion to copper foil, and the cured film does not deteriorate even if immersed in alkali-resistant (PH12) for a long time. It's safe. The coating method for this anti-plating resist is screen printing, and the mixing ratio is 100 g of the main agent and 10 g of the curing agent. The curing conditions include a temperature range of 150 to 200°C and a set time of 30 to 15 minutes.

また主な特性としては色調、形状は緑色かつイ
ンク状であり、密着性（クロスカツト）は100／
100（銅箔面）、表面硬度（エンピツ使用）は8H以
上、耐溶剤性（トリクロルエチレン中）は15秒以
上、半田耐熱性（260℃）は５サイクル以上、表
面絶縁抵抗値５×1013Ω以上、体積抵抗値は１×
1014Ω-cm、耐電圧（15μｍ）は3.5kV以上、誘電
正接（1MHz）は0.03以下である。 The main characteristics are that the color and shape are green and ink-like, and the adhesion (cross cut) is 100/
100 (copper foil surface), surface hardness (using pencil) is 8H or more, solvent resistance (in trichlorethylene) is 15 seconds or more, soldering heat resistance (260℃) is 5 cycles or more, surface insulation resistance value is 5 x 10 13 Ω or more, volume resistance value is 1×
10 14 Ω - cm, withstand voltage (15μm) is 3.5kV or more, and dielectric loss tangent (1MHz) is 0.03 or less.

効 果 本発明は、上記のように構成されるものである
から、両面銅貼積層基板に形成された銅箔からな
る第１層導電回路のうち第２層導電回路と電気的
に接続する必要がある部分にのみ上記新開発され
た銅めつき性の良好な銅導電ペーストを塗布して
加熱硬化させ、その上に銅の化学めつきを施し、
該銅導電ペーストの導電性を銅箔と同程度に向上
させて、第２層導電回路となし、銅箔を用いたプ
リント基板等の基板の片面に電気的に接続された
少なくとも２層の導電回路を形成することがで
き、この結果両面に少なくとも４層の導電回路を
形成することができるので、両面スルホール基板
における導電回路の形成工程を飛躍的に簡略化す
ることができ、また完成品としてのプリント配線
基板のコストを従来品の約２分の１に低減させる
ことができる効果がある。Effects Since the present invention is configured as described above, there is no need to electrically connect the first layer conductive circuit made of copper foil formed on the double-sided copper-clad laminated board with the second layer conductive circuit. The newly developed copper conductive paste with good copper plating properties is applied only to certain areas and cured by heating, and then chemical copper plating is applied on top of it.
The conductivity of the copper conductive paste is improved to the same level as that of copper foil to form a second layer conductive circuit, and at least two conductive layers are electrically connected to one side of a substrate such as a printed circuit board using copper foil. As a result, it is possible to form at least four layers of conductive circuits on both sides, which dramatically simplifies the process of forming conductive circuits on double-sided through-hole boards. This has the effect of reducing the cost of the printed wiring board to approximately one-half of that of conventional products.

また基板両面の耐めつきレジスト上に所定の電
気抵抗値を有する抵抗ペーストを塗布して加熱硬
化させ、該抵抗ペーストとその両面の第１層導電
回路又は第２層導電回路とを電気的に接続するよ
うに導電性の良好な端子用導電ペーストを塗布し
て加熱硬化させて基板の両面に抵抗回路を形成
し、次いでスルホール内周面を活性化処理してこ
こに無電解銅めつきを施し、基板両面の第１層導
電回路を電気的に接続し、基板の両面に抵抗回路
を含む少なくとも４層の導電回路を形成すること
ができるので、従来の抵抗器、その基板への挿入
又は接着作業及び半田付作業を不要とすることが
できる効果があり、またこの結果超薄型の抵抗回
路を提供することができる効果が得られる。 In addition, a resistance paste having a predetermined electrical resistance value is coated on the resistant resist on both sides of the substrate and cured by heating, and the resistance paste and the first layer conductive circuit or the second layer conductive circuit on both sides are electrically connected. A conductive paste for terminals with good conductivity is applied for connection and cured by heating to form a resistance circuit on both sides of the board.Then, the inner peripheral surface of the through hole is activated and electroless copper plating is applied thereto. It is possible to electrically connect the first layer conductive circuits on both sides of the substrate and form at least four layers of conductive circuits including resistance circuits on both sides of the substrate. This has the advantage that bonding work and soldering work are not required, and as a result, an ultra-thin resistance circuit can be provided.

更には第１層導電回路又は第２層導電回路の一
部に蓄電作用を有する誘電体ペーストを塗布して
加熱硬化させ、該誘電体ペーストと耐めつきレジ
ストにより絶縁された第１層導電回路又は第２層
導電回路とを電気的に接続するように導電性の良
好な端子用導電ペーストを塗布して加熱硬化させ
て基板の両面に蓄電回路を形成し、次いでスルホ
ール内周面を活性化処理してここに無電解銅めつ
きを施し、基板両面の第１層導電回路を電気的に
接続し、基板の両面に蓄電回路を含む少なくとも
４層の導電回路を形成することができるので、従
来のコンデンサ、その基板への挿入又は接着作業
及び半田付作業を不要とすることができる効果が
あり、またこの結果超薄型の蓄電回路を形成する
ことができるという効果が得られる。またこのよ
うに基板の両面に抵抗回路又は蓄電回路を含む少
なくとも４層の導電回路を形成することにより、
プリント配線基板の実装密度の向上、軽量化及び
製造工程の省力化を図ることができ、また誤配線
や抵抗器やコンデンサの挿入ミスのおそれをなく
し、プリント配線基板の抵抗回路及び蓄電回路の
信頼性を大幅に向上させ、コストの低減を達成す
ることができる効果が得られる。 Further, a dielectric paste having a power storage function is applied to a part of the first layer conductive circuit or the second layer conductive circuit and cured by heating, and the first layer conductive circuit is insulated by the dielectric paste and a plating resist. Alternatively, a conductive paste for terminals with good conductivity is applied to electrically connect with the second layer conductive circuit and cured by heating to form a power storage circuit on both sides of the substrate, and then the inner peripheral surface of the through hole is activated. It is possible to process and apply electroless copper plating to electrically connect the first layer conductive circuits on both sides of the substrate to form at least four layers of conductive circuits including power storage circuits on both sides of the substrate. This has the effect of eliminating the need for conventional capacitors, the work of inserting or adhering them to a substrate, and the work of soldering, and as a result, an ultra-thin power storage circuit can be formed. Furthermore, by forming at least four layers of conductive circuits including resistance circuits or storage circuits on both sides of the substrate,
It is possible to improve the mounting density of the printed wiring board, reduce weight, and save labor in the manufacturing process.It also eliminates the risk of incorrect wiring or incorrect insertion of resistors and capacitors, and improves the reliability of the resistance circuit and power storage circuit of the printed wiring board. The effect is that performance can be significantly improved and costs can be reduced.

実施例 １ 紙フエノール基板にACP−007Pなる銅導電ペ
ーストを直接印刷して150℃にて所定時間加熱し
て硬化させた後、アルカリ、酸処理を行い、その
表面に化学銅めつきを施した場合において、化学
銅めつきの厚さが6μｍとなり、これに測定用端
子にリード線（錫めつき線0.5mmφ）を半田付け
した（３秒以内）。この場合、銅導電ペーストの
硬化時間が30分では半田引張り強度（Kg／３×３
mm2）は5.1Kgであり、また硬化時間が60分では5.9
Kgであつた。Example 1 A copper conductive paste called ACP-007P was directly printed on a paper phenol substrate, heated at 150°C for a predetermined period of time to harden it, and then treated with alkali and acid, and chemical copper plating was applied to the surface. In this case, the thickness of the chemical copper plating was 6 μm, and a lead wire (tinned wire 0.5 mmφ) was soldered to the measurement terminal (within 3 seconds). In this case, if the curing time of the copper conductive paste is 30 minutes, the solder tensile strength (Kg/3×3
mm 2 ) is 5.1Kg, and 5.9 at a curing time of 60 minutes.
It was Kg.

次に同様な条件で基板にガラスエポキシ基板を
用いた場合には、硬化時間が30分では引張り強度
は5.9Kg、硬化時間が60分では6.2Kgであつた。 Next, when a glass epoxy substrate was used as the substrate under similar conditions, the tensile strength was 5.9 Kg when the curing time was 30 minutes, and 6.2 Kg when the curing time was 60 minutes.

実施例 ２ フエノール基板にCR−2001なる耐めつきレジ
ストを印刷し、150℃にて30分間加熱して硬化さ
せ、次にACP−007Pなる銅導電ペーストを印刷
し、150℃にて所定時間加熱して硬化させた後、
アルカリ、酸処理を行い、化学銅めつきを行つ
た。化学銅めつきの厚さは6μｍであり、測定用
端子にリード線（錫めつき線0.5mmφ）を半田付
けした（３秒以内）。この場合の半田引張り強度
（Kg／３×３mm2）は銅導電ペーストの硬化時間が
30分では5.9Kg、硬化時間が60分では6.1Kgであつ
た。Example 2 A plating resist called CR-2001 was printed on a phenol substrate and cured by heating at 150°C for 30 minutes. Next, a copper conductive paste called ACP-007P was printed and heated at 150°C for a predetermined time. After curing,
Alkali and acid treatments were performed and chemical copper plating was performed. The thickness of the chemical copper plating was 6 μm, and a lead wire (tinned wire 0.5 mmφ) was soldered to the measurement terminal (within 3 seconds). In this case, the solder tensile strength (Kg/3×3mm 2 ) is determined by the curing time of the copper conductive paste.
When the curing time was 30 minutes, the weight was 5.9Kg, and when the curing time was 60 minutes, the weight was 6.1Kg.

同様な条件において、ガラスエポキシ基板を用
いた場合には、硬化時間が30分の場合に半田引張
り強度は6.1Kg、硬化時間が60分の場合には6.9Kg
であつた。 Under similar conditions, when using a glass epoxy substrate, the solder tensile strength was 6.1 Kg when the curing time was 30 minutes, and 6.9 Kg when the curing time was 60 minutes.
It was hot.

【図面の簡単な説明】[Brief explanation of drawings]

第１図から第１１図は特定発明の実施例（第１
図から第９図は第２発明及び第３発明に共通の実
施例）に係り、第１図は両面銅貼積層基板の縦断
面図、第２図は第１図に示すものにスルホールの
穴あけ加工を施した状態を示す縦断面図、第３図
は第２図に示すものにキヤタリスト処理が施され
た状態を示す縦断面図、第４図は第３図に示すも
のを水洗、乾燥した状態を示す縦断面図、第５図
は第４図に示すものに耐エツチングレジストが塗
布された状態を示す縦断面図、第６図は第５図に
示すものにエツチング加工を施して第１層導電回
路が形成された状態を示す縦断面図、第７図は第
６図に示すものに耐めつきレジストが塗布された
状態を示す縦断面図、第８図は第７図に示すもの
に銅導電ペーストが塗布された状態を示す縦断面
図、第９図は第８図に示すものに化学銅めつきが
施された状態を示す縦断面図、第１０図は第９図
に示すものに耐めつきレジストが塗布された状態
を示す縦断面図、第１１図はスルホールの内周面
に無電解銅めつきが施されて完成した状態を示す
プリント配線基板の縦断面図、第１２図から第１
５図は第２発明の実施例に係り、第１２図は第９
図に示すものに抵抗ペーストが塗布された状態を
示す縦断面図、第１３図は第１２図に示すものに
端子用導電ペーストが塗布された状態を示す縦断
面図、第１４図は第１３図に示すものに耐めつき
レジストが塗布された状態を示す縦断面図、第１
５図はスルホールの内周面に無電解銅めつきが施
されて完成したプリント配線基板の縦断面図、第
１６図から第１９図は第３発明の実施例に係り、
第１６図は第１９図に示すものに誘電体ペースト
が塗布された状態を示す縦断面図、第１７図は第
１６図に示すものに端子用導電ペーストが塗布さ
れた状態を示す縦断面図、第１８図は第１７図に
示すものに耐めつきレジストが塗布された状態を
示す縦断面図、第１９図はスルホールの内周面に
無電解銅めつきが施されて完成したプリント配線
基板の縦断面図である。 １は基板、３は両面銅貼積層基板、３ａは第１
層導電回路を形成しない部分、４はスルホール、
４ａは内周面、６は耐めつきレジスト、８は銅
箔、９は銅導電ペースト、１０は銅めつき層、１
３は抵抗回路、１４は抵抗ペースト、１５は端子
用導電ペースト、１６は蓄電回路、１８は誘電体
ペースト、１９は端子用導電ペースト、C1は第
１層導電回路、C2第２層導電回路である。 1 to 11 are embodiments of the specified invention (first embodiment).
Figures 9 to 9 relate to embodiments common to the second and third inventions, Figure 1 is a longitudinal cross-sectional view of a double-sided copper-clad laminated board, and Figure 2 is a through-hole drilled in the one shown in Figure 1. Figure 3 is a longitudinal cross-sectional view showing the processed state, Figure 3 is a vertical cross-sectional view showing the catalyst treatment applied to the product shown in Figure 2, and Figure 4 is the product shown in Figure 3 washed with water and dried. FIG. 5 is a vertical cross-sectional view showing the state shown in FIG. 4 with etching-resistant resist applied, and FIG. 6 is a vertical cross-sectional view showing the state shown in FIG. 5 after etching. A vertical cross-sectional view showing a state in which a layered conductive circuit is formed, FIG. 7 is a vertical cross-sectional view showing a state in which a plating resist is applied to the structure shown in FIG. 6, and FIG. 8 is a longitudinal cross-sectional view showing the structure shown in FIG. 9 is a vertical sectional view showing the state in which the copper conductive paste is applied to the material shown in FIG. 8, and FIG. FIG. 11 is a vertical cross-sectional view showing a state in which a plating-resistant resist is applied to a printed wiring board; FIG. 1st from figure 12
5 relates to the embodiment of the second invention, and FIG. 12 relates to the embodiment of the 9th invention.
13 is a vertical sectional view showing the state shown in FIG. 12 with conductive paste for terminals applied, and FIG. 14 is a longitudinal sectional view showing the state shown in FIG. Vertical cross-sectional view showing the state in which a resistant resist is applied to the item shown in the figure, No. 1
FIG. 5 is a vertical cross-sectional view of a completed printed wiring board with electroless copper plating applied to the inner peripheral surface of the through hole, and FIGS. 16 to 19 relate to an embodiment of the third invention.
FIG. 16 is a vertical cross-sectional view showing the state shown in FIG. 19 with dielectric paste applied, and FIG. 17 is a vertical cross-sectional view showing the state shown in FIG. 16 with conductive paste for terminals applied. , Fig. 18 is a vertical cross-sectional view showing the state shown in Fig. 17 with a plating resist applied, and Fig. 19 is a completed printed wiring with electroless copper plating applied to the inner peripheral surface of the through hole. FIG. 3 is a longitudinal cross-sectional view of the substrate. 1 is a substrate, 3 is a double-sided copper-clad laminated board, and 3a is a first
A portion that does not form a layer conductive circuit, 4 is a through hole,
4a is an inner peripheral surface, 6 is a plating resist, 8 is a copper foil, 9 is a copper conductive paste, 10 is a copper plating layer, 1
3 is a resistance circuit, 14 is a resistance paste, 15 is a conductive paste for terminals, 16 is a storage circuit, 18 is a dielectric paste, 19 is a conductive paste for terminals, C 1 is a first layer conductive circuit, C 2 is a second layer conductive It is a circuit.

Claims (1)

【特許請求の範囲】 １ 両面銅貼積層基板にスルホールの穴あけ加工
を施してキヤタリスト処理を行い、次いで前記基
板を水洗、乾燥し、該基板の両面の銅箔にエツチ
ング加工を施して銅箔による複数の第１層導電回
路を該基板の両面に形成し、該第１層導電回路の
部分を残して前記基板の両面に耐めつきレジスト
を塗布して加熱硬化させ、前記基板の両面の前記
複数の第１層導電回路の一部を電気的に互いに接
続するように、多孔質海綿状の微粉末からなる銅
粉とバインダとしてのエポキシ樹脂とを混合した
ものに酸化防止用の添加剤としてアントラセン、
アントラセンカルボン酸、アントラジン及びアン
トラニル酸より選ばれたいずれか１種のものを添
加してなる銅めつき性の良好な銅導電ペーストを
塗布して加熱硬化させ、この状態で前記基板にめ
つき前処理を施して後、前記銅導電ペーストの表
面に化学銅めつきを施し、該銅めつき層と該銅導
電ペーストとにより第２層導電回路を前記基板の
両面に形成し、次いで前記スルホール及びその周
囲の前記第１層導電回路の部分を残して耐めつき
レジストを塗布して加熱硬化させ、前記スルホー
ル内周面を対象とした活性化処理を施して後、該
スルホール内周面に無電解銅めつきを施し、前記
基板の両面の前記第１層導電回路を該銅めつき層
で接続し、該基板の両面に少なくとも４層の導電
回路を形成することを特徴とする基板に導電回路
を形成する方法。 ２ 両面銅貼積層基板にスルホールの穴あけ加工
を施してキヤタリスト処理を行い、次いで前記基
板を水洗、乾燥し、該基板の両面の銅箔にエツチ
ング加工を施して銅箔による複数の第１層導電回
路を該基板の両面に形成し、該第１層導電回路の
部分を残して前記基板の両面に耐めつきレジスト
を塗布して加熱硬化させ、前記基板の両面の前記
複数の第１層導電回路の一部を互いに電気的に接
続するように、多孔質海綿状の微粉末からなる銅
粉とバインダとしてのエポキシ樹脂とを混合した
ものに酸化防止用の添加剤としてアントラセン、
アントラセンカルボン酸、アントラジン及びアン
トラニル酸より選ばれたいずれか１種のものを添
加してなる銅めつき性の良好な銅導電ペーストを
塗布して加熱硬化させ、この状態で前記基板にめ
つき前処理を施して後、前記銅導電ペーストの表
面に化学銅めつきを施し、該銅めつき層と該銅導
電ペーストとにより第２層導電回路を前記基板の
両面に形成し、次いで前記基板両面の耐めつきレ
ジスト上に所定の電気抵抗値を有する抵抗ペース
トを塗布して加熱硬化させ、該抵抗ペーストとそ
の両側の前記第１層導電回路又は第２層導電回路
とを電気的に接続するように導電性の良好な端子
用導電ペーストを塗布して加熱硬化させて前記基
板の両面に抵抗回路を形成し、次いで前記スルホ
ール及びその周囲の前記第１層導電回路の部分を
残して耐めつきレジストを塗布して加熱硬化さ
せ、前記スルホール内周面を対象とした活性化処
理を施して後、該スルホール内周面に無電解銅め
つきを施し、前記基板の両面の前記第１層導電回
路を該銅めつき層で電気的に接続し、該基板の両
面に前記抵抗回路を含む少なくとも４層の導電回
路を形成することを特徴とする基板に導電回路を
形成する方法。 ３ 両面銅貼積層基板にスルホールの穴あけ加工
を施してキヤタリスト処理を行い、次いで前記基
板を水洗、乾燥し、該基板の両面の銅箔にエツチ
ング加工を施して銅箔による複数の第１層導電回
路を該基板の両面に形成し、該第１層導電回路の
部分を残して前記基板の両面に耐めつきレジスト
を塗布して加熱硬化させ、前記基板の両面の前記
複数の第１層導電回路の一部を互いに電気的に接
続するように、多孔質海綿状の微粉末からなる銅
粉とバインダとしてのエポキシ樹脂とを混合した
ものに酸化防止用の添加剤としてアントラセン、
アントラセンカルボン酸、アントラジン及びアン
トラニル酸より選ばれたいずれか１種のものを添
加してなる銅めつき性の良好な銅導電ペーストを
塗布して加熱硬化させ、この状態で前記基板にめ
つき前処理を施して後、前記銅導電ペーストの表
面に化学銅めつきを施し、該銅めつき層と該銅導
電ペーストとにより第２層導電回路を前記基板の
両面に形成し、次いで前記第１層導電回路又は第
２層導電回路の一部に蓄電作用を有する誘電体ペ
ーストを塗布して加熱硬化させ、該誘電体ペース
トと前記耐めつきレジストとにより絶縁された前
記第１層導電回路又は第２層導電回路とを電気的
に接続するように導電性の良好な端子用導電ペー
ストを塗布して加熱硬化させて前記基板の両面に
蓄電回路を形成し、次いで前記スルホール及びそ
の周囲の前記第１層導電回路の部分を残して耐め
つきレジストを塗布して加熱硬化させ、前記スル
ホール内周面を対象とした活性化処理を施して
後、該スルホール内周面に無電解銅めつきを施
し、前記基板の両面の前記第１層導電回路を該銅
めつき層で電気的に接続し、該基板の両面に前記
蓄電回路を含む少なくとも４層の導電回路を形成
することを特徴とする基板に導電回路を形成する
方法。[Claims] 1. A double-sided copper-clad laminated board is subjected to a catalyst treatment by drilling through-holes, then the board is washed with water and dried, and the copper foil on both sides of the board is etched. A plurality of first-layer conductive circuits are formed on both sides of the substrate, and a plating resist is applied to both sides of the substrate, leaving a portion of the first-layer conductive circuits, and cured by heating. An antioxidant additive is added to a mixture of porous spongy fine powder copper powder and epoxy resin as a binder so as to electrically connect parts of the plurality of first layer conductive circuits to each other. anthracene,
Copper conductive paste with good copper plating properties, which is made by adding any one selected from anthracenecarboxylic acid, anthrazine, and anthranilic acid, is applied and cured by heating, and in this state, before plating on the substrate. After the treatment, chemical copper plating is applied to the surface of the copper conductive paste, a second layer conductive circuit is formed on both sides of the substrate by the copper plating layer and the copper conductive paste, and then the through-holes and A plating-resistant resist is applied and heated to cure the first layer conductive circuit portion around it, and an activation treatment is applied to the inner circumferential surface of the through hole. A conductive substrate, characterized in that electrolytic copper plating is applied, the first layer conductive circuits on both sides of the substrate are connected by the copper plating layer, and at least four layers of conductive circuits are formed on both sides of the substrate. How to form circuits. 2. A double-sided copper-clad laminated board is subjected to a catalyst treatment by drilling through-holes, then the board is washed with water and dried, and the copper foils on both sides of the board are etched to form a plurality of first conductive layers made of copper foil. A circuit is formed on both sides of the substrate, and a resistant resist is applied to both sides of the substrate, leaving a portion of the first layer conductive circuit, and cured by heating, thereby forming the plurality of first conductive layers on both sides of the substrate. In order to electrically connect parts of the circuit to each other, anthracene and anthracene are added as antioxidant additives to a mixture of porous spongy fine powder of copper powder and epoxy resin as a binder.
Copper conductive paste with good copper plating properties, which is made by adding any one selected from anthracenecarboxylic acid, anthrazine, and anthranilic acid, is applied and cured by heating, and in this state, before plating on the substrate. After the treatment, chemical copper plating is applied to the surface of the copper conductive paste, a second layer conductive circuit is formed on both sides of the substrate by the copper plating layer and the copper conductive paste, and then a second layer conductive circuit is formed on both sides of the substrate. A resistance paste having a predetermined electrical resistance value is applied onto the plating resist and cured by heating, and the resistance paste is electrically connected to the first layer conductive circuit or the second layer conductive circuit on both sides thereof. A conductive paste for terminals with good conductivity is applied and cured by heating to form a resistive circuit on both sides of the substrate, and then the through hole and the portion of the first layer conductive circuit around it are left to form a resistive paste. After applying a resist and heating and curing it and performing an activation treatment targeting the inner circumferential surface of the through hole, electroless copper plating is applied to the inner circumferential surface of the through hole, and the first layer on both sides of the substrate is A method for forming a conductive circuit on a substrate, comprising electrically connecting the conductive circuit with the copper plating layer, and forming at least four layers of conductive circuits including the resistance circuit on both sides of the substrate. 3. A double-sided copper-clad laminated board is subjected to through-hole drilling and catalyst processing, then the board is washed with water and dried, and the copper foils on both sides of the board are etched to form a plurality of first conductive layers made of copper foil. A circuit is formed on both sides of the substrate, and a resistant resist is applied to both sides of the substrate, leaving a portion of the first layer conductive circuit, and cured by heating. To electrically connect parts of the circuit to each other, anthracene and anthracene are added as antioxidant additives to a mixture of porous spongy fine copper powder and epoxy resin as a binder.
Copper conductive paste with good copper plating properties, which is made by adding any one selected from anthracenecarboxylic acid, anthrazine, and anthranilic acid, is applied and cured by heating, and in this state, before plating on the substrate. After the treatment, chemical copper plating is applied to the surface of the copper conductive paste, a second layer conductive circuit is formed on both sides of the substrate by the copper plating layer and the copper conductive paste, and then the first conductive circuit is formed on both sides of the substrate. A layer conductive circuit or a part of the second layer conductive circuit is coated with a dielectric paste having a charge storage function and cured by heating, and the first layer conductive circuit is insulated by the dielectric paste and the plating resist. A conductive paste for terminals having good conductivity is coated and cured by heating to electrically connect the second layer conductive circuit, and a power storage circuit is formed on both sides of the substrate. A plating-resistant resist is applied leaving the first layer conductive circuit portion and cured by heating, and an activation treatment is applied to the inner circumferential surface of the through-hole, followed by electroless copper plating on the inner circumferential surface of the through-hole. The first layer conductive circuits on both sides of the substrate are electrically connected by the copper plating layer, and at least four layers of conductive circuits including the power storage circuit are formed on both sides of the substrate. A method of forming conductive circuits on a substrate.
JP61005645A 1986-01-14 1986-01-14 Method of forming conductive circuit on board Granted JPS62163395A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP61005645A JPS62163395A (en) 1986-01-14 1986-01-14 Method of forming conductive circuit on board
US06/947,437 US4735676A (en) 1986-01-14 1986-12-29 Method for forming electric circuits on a base board
FR878700274A FR2593016B1 (en) 1986-01-14 1987-01-13 METHOD FOR FORMING ELECTRICAL CIRCUITS ON A BASE BOARD
KR1019870000192A KR900003152B1 (en) 1986-01-14 1987-01-13 Method for forming capacitive circuit on circuit board
GB8700717A GB2186434B (en) 1986-01-14 1987-01-13 A method for forming electric circuits on a base board
DE19873700910 DE3700910A1 (en) 1986-01-14 1987-01-14 METHOD FOR BUILDING ELECTRICAL CIRCUITS ON A BASE PLATE
NL8700078A NL8700078A (en) 1986-01-14 1987-01-14 METHOD FOR APPLYING ELECTRICAL SWITCHES TO A BASE PLATE

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61005645A JPS62163395A (en) 1986-01-14 1986-01-14 Method of forming conductive circuit on board

Publications (2)

Publication Number Publication Date
JPS62163395A JPS62163395A (en) 1987-07-20
JPH0213957B2 true JPH0213957B2 (en) 1990-04-05

Family

ID=11616866

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61005645A Granted JPS62163395A (en) 1986-01-14 1986-01-14 Method of forming conductive circuit on board

Country Status (2)

Country Link
JP (1) JPS62163395A (en)
GB (1) GB2186434B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10259918B4 (en) 2002-12-20 2005-06-23 Rheinmetall Landsysteme Gmbh Mine protection device, in particular for wheeled vehicles

Also Published As

Publication number Publication date
GB2186434A (en) 1987-08-12
JPS62163395A (en) 1987-07-20
GB2186434B (en) 1990-02-14
GB8700717D0 (en) 1987-02-18

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