JPH02130947A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02130947A
JPH02130947A JP28598488A JP28598488A JPH02130947A JP H02130947 A JPH02130947 A JP H02130947A JP 28598488 A JP28598488 A JP 28598488A JP 28598488 A JP28598488 A JP 28598488A JP H02130947 A JPH02130947 A JP H02130947A
Authority
JP
Japan
Prior art keywords
marking
semiconductor element
thin wire
semiconductor device
sealing resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28598488A
Other languages
Japanese (ja)
Inventor
Hisao Masuda
桝田　久雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP28598488A priority Critical patent/JPH02130947A/en
Publication of JPH02130947A publication Critical patent/JPH02130947A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent the heat generated at the time of marking from being transmitted to a metal thin wire, and eliminate the problems of characteristics deterioration, exposure and melting by performing marking on a resin seal surface opposite to the ordinary marking surface, i.e., the surface on which connection electrodes of a semiconductor element are present. CONSTITUTION:Leads 3 are arranged on the surface of a semiconductor element 1 fixed on a die pad 4 so as to keep an interval. Electrodes 6 formed on the surface of the semiconductor element are connected with the leads 3 by using metal thin wires 2 respectively. While outer end of the lead 3 is exposed, the whole part is sealed with resin 5, and a mark is formed on this sealed body by using laser. The mark which is usually arranged on the surface of the element 1 is disposed on the rear of the element 1, i.e., the die pad 4 side. By this set-up, the heat of mark forming laser is not transmitted to the metal thin wire 2, so that the thin wire is not melted even in the case of an element wherein the hanging-down of the thin wire is in the range within 50mum.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置のマーキングに関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to marking of semiconductor devices.

〔従来の技術〕[Conventional technology]

第２図は従来の半導体装置のパッケージ構造の一例を示
すもので、第３図は第２図のＩ−１線断面図、第４図は
第３図の一部の拡大図である。これらの図において、１
は半導体素子、２は金属細線、３はリード、４はダイパ
ッド、５は封止樹脂、６は半導体素子の結線用の電極、
Ａは実装面、Ｂはマーキング面、Ｉは封止樹脂表面と金
属ａｔ、ｍの最大高さ部分との距離である。FIG. 2 shows an example of a conventional package structure of a semiconductor device, FIG. 3 is a sectional view taken along line I-1 in FIG. 2, and FIG. 4 is an enlarged view of a part of FIG. 3. In these figures, 1
is a semiconductor element, 2 is a thin metal wire, 3 is a lead, 4 is a die pad, 5 is a sealing resin, 6 is an electrode for connecting the semiconductor element,
A is the mounting surface, B is the marking surface, and I is the distance between the sealing resin surface and the maximum height portion of the metals at and m.

次に従来のマーキングについて述べる。マーキングは特
別な場合を除いて、一般には第３図のマーキング面Ｂな
る封止樹脂表面（半導体素子の表面側）に、入熱によっ
て封止樹脂を融解、燃焼または昇華等をさせることによ
り行われている。Next, conventional marking will be described. Except for special cases, marking is generally performed by melting, burning, or sublimating the sealing resin by heat input on the sealing resin surface (the surface side of the semiconductor element), which is the marking surface B in Figure 3. It is being said.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

以上のようにマーキングを行った場合（以後代表例とし
てレーザーマーキングと記す）、例えば図中の斜線部Ｃ
にレーザーマーキングされると、次に示すような問題が
発生する。When marking is performed as described above (hereinafter referred to as laser marking as a typical example), for example, the shaded area C in the figure
When laser marking is applied to a material, the following problems occur.

（ａ）ｊが５０μべ以下になると、レーザーマーク時の
熱により、金属細線の特性が劣化する。(a) When j is less than 50μ, the characteristics of the thin metal wire deteriorate due to heat during laser marking.

（ｂＢが２０μ札以下になると、レーザーマーク時の熱
により金属細線が部分的に融解したり、表面部の封止樹
脂が昇華等により除かれるなめ、金属細線の露出等が発
生する。(If bB is less than 20μ, the thin metal wire will partially melt due to the heat during laser marking, or the sealing resin on the surface will be removed by sublimation, etc., resulting in exposure of the thin metal wire.

上記のように、一般的に行われるように第３図マーキン
グ面Ｂにレーザーマークをすると、上記のように１が５
０μ八以下では、半導体装置に品質、信頼性上の問題が
発生する。As mentioned above, if a laser mark is made on marking surface B in Fig. 3 as is generally done, 1 becomes 5 as shown above.
If it is less than 0 μ8, quality and reliability problems will occur in the semiconductor device.

この発明は以上のような問題点を解消するためになされ
たもので、マーキングによる品質、信頼性上の劣化をな
くすことを目的とする。This invention was made to solve the above-mentioned problems, and aims to eliminate deterioration in quality and reliability due to marking.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置は、マーキングを行う封止樹
脂面を、従来一般に行っていた面と反対の面、つまり半
導体素子の結線用電極のある側と反対側の封止樹脂表面
に施したものである。In the semiconductor device according to the present invention, marking is applied to the sealing resin surface on the opposite side to the conventionally used surface, that is, on the side opposite to the side on which the wiring electrodes of the semiconductor element are located. It is.

〔作用〕 この発明においては、マーキングを、半導体素子の結線
用電極のある側と反対側の封止樹脂表面に行ったため、
マーキングによる熱によって金属細線に熱があまり伝わ
らず、特性の劣化、露出、融解等の問題がなくなる。[Function] In this invention, since the marking was performed on the surface of the sealing resin on the side opposite to the side where the wiring electrode of the semiconductor element is located,
The heat generated by marking does not transfer much heat to the thin metal wire, eliminating problems such as deterioration of characteristics, exposure, and melting.

〔実ＩＩｉ例〕[Real example IIi]

以下、この発明の一実施例を図について説明する。第１
図は第３図に対応する図であり、レーザーマーキングを
行う封止樹脂面Ｂを上下変更したものである。なお部品
名については第３図に対応するものであるので説明を省
略する。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure corresponds to FIG. 3, and the sealing resin surface B on which laser marking is performed has been changed vertically. Note that the names of the parts correspond to those shown in FIG. 3, so explanations thereof will be omitted.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明では、マーキングを行う封止樹脂
面を半導体素子の結線用電極のある側（金属細線の結線
がしである側）と反対側の面にしたため、Ｉが５０μ属
以下であっても、金属細線にマーキング時の熱があまり
伝わらず、熱による金属細線の特性の劣化、マーキング
による封止樹脂の昇華等による金属細線の露出、熱によ
る金属ｌ１ｌｌ線の融解等の問題が皆無となり、品質、
信頼性の向上に大いに寄与する効果がある。As described above, in this invention, since the sealing resin surface to be marked is the opposite side to the side where the wiring electrode of the semiconductor element is located (the side where the thin metal wire is connected), I is 50μ or less. Even if there is, the heat during marking is not transferred to the thin metal wire very well, resulting in problems such as deterioration of the characteristics of the thin metal wire due to heat, exposure of the thin metal wire due to sublimation of the sealing resin due to marking, and melting of the metal wire due to heat. There will be no quality,
This has the effect of greatly contributing to improving reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の一実施例を示す断面図、第２図は一
般的な半導体装置のパッケージ構造を示す一部切欠の斜
視図、第３図は従来例による第２図のＩ−１線の断面図
、第４図は第３図の一部の拡大図である。 図中、ｌは半導体素子、２は金属細線、３はリード、４
はダイパッド、５は封止樹脂、６は電極、Ｂはマーキン
グ面である。 なお、図中同一符号は同−又は相当部分を示す。FIG. 1 is a sectional view showing an embodiment of the present invention, FIG. 2 is a partially cutaway perspective view showing the package structure of a general semiconductor device, and FIG. 3 is a conventional example shown at I-1 in FIG. The line cross-sectional view, FIG. 4, is an enlarged view of a portion of FIG. 3. In the figure, l is a semiconductor element, 2 is a thin metal wire, 3 is a lead, 4
5 is a die pad, 5 is a sealing resin, 6 is an electrode, and B is a marking surface. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 樹脂封止された半導体装置で、内蔵された半導体素子の
結線用電極のある面側の封止樹脂の表面と、半導体素子
の結線用電極とインナーリードを結線する金属細線の最
大高さ部分との距離が５０μｍ以内の半導体装置におい
て、入熱により封止樹脂を融解、燃焼、または昇華等を
させることによるマーキングを、半導体素子の結線用電
極のある面と反対面側の樹脂表面に施したことを特徴と
する半導体装置。In a resin-sealed semiconductor device, the surface of the sealing resin on the side where the wiring electrode of the built-in semiconductor element is located, and the maximum height part of the thin metal wire that connects the wiring electrode of the semiconductor element and the inner lead. In a semiconductor device where the distance between the two is within 50 μm, a marking is applied to the resin surface on the side opposite to the side where the wiring electrode of the semiconductor element is located by melting, burning, or sublimating the sealing resin by heat input. A semiconductor device characterized by:
JP28598488A 1988-11-11 1988-11-11 Semiconductor device Pending JPH02130947A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28598488A JPH02130947A (en) 1988-11-11 1988-11-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28598488A JPH02130947A (en) 1988-11-11 1988-11-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02130947A true JPH02130947A (en) 1990-05-18

Family

ID=17698512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28598488A Pending JPH02130947A (en) 1988-11-11 1988-11-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02130947A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0498446A2 (en) * 1991-02-08 1992-08-12 Kabushiki Kaisha Toshiba Multichip packaged semiconductor device and method for manufacturing the same
US7186945B2 (en) * 2003-10-15 2007-03-06 National Starch And Chemical Investment Holding Corporation Sprayable adhesive material for laser marking semiconductor wafers and dies
CN104467669A (en) * 2013-09-25 2015-03-25 株式会社大真空 Lead type electronic component
JP2015088731A (en) * 2013-09-25 2015-05-07 株式会社大真空 Lead type electronic equipment

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0498446A2 (en) * 1991-02-08 1992-08-12 Kabushiki Kaisha Toshiba Multichip packaged semiconductor device and method for manufacturing the same
US7186945B2 (en) * 2003-10-15 2007-03-06 National Starch And Chemical Investment Holding Corporation Sprayable adhesive material for laser marking semiconductor wafers and dies
CN104467669A (en) * 2013-09-25 2015-03-25 株式会社大真空 Lead type electronic component
JP2015088731A (en) * 2013-09-25 2015-05-07 株式会社大真空 Lead type electronic equipment
CN104467669B (en) * 2013-09-25 2018-09-28 株式会社大真空 Lead-type electronic-part

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