JPH04176156A - Semiconductor device lead frame - Google Patents
Semiconductor device lead frameInfo
- Publication number
- JPH04176156A JPH04176156A JP30348090A JP30348090A JPH04176156A JP H04176156 A JPH04176156 A JP H04176156A JP 30348090 A JP30348090 A JP 30348090A JP 30348090 A JP30348090 A JP 30348090A JP H04176156 A JPH04176156 A JP H04176156A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- lead frame
- leads
- semiconductor device
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 abstract description 2
- 239000003292 glue Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置用り一トフレームに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a frame for semiconductor devices.
従来、この種の半導体装置用リードフレーム（以下リー
ドフレームと記す）は、第２図（ａ）。Conventionally, this type of lead frame for semiconductor devices (hereinafter referred to as lead frame) is shown in FIG. 2(a).
（ｂ）に示すように、半導体素子搭載部４と、この半導
体素子搭載部４に搭載される半導体素子の電極とボンデ
インクワイヤ等にて接続される内部リート１１と、この
内部リード１１に接続する外部リード２と、内部リード
１］と外部リード２の中間に位置しこれらを連結し封止
時に樹脂の外部への流れを防止するタムバー３等によっ
て構成され一枚の板から形成されるため、半導体素子搭
載部４と内部リード１１と外部リード２とダムバー３の
板厚は、全て同じ厚さてあった。As shown in (b), the semiconductor element mounting part 4, the internal lead 11 connected to the electrode of the semiconductor element mounted on the semiconductor element mounting part 4 with a bonded ink wire, etc., and the internal lead 11 connected to the semiconductor element mounting part 4. The external lead 2 is located between the internal lead 1 and the external lead 2, and the tom bar 3 connects them and prevents the resin from flowing to the outside during sealing. The thickness of the semiconductor element mounting portion 4, the internal lead 11, the external lead 2, and the dam bar 3 were all the same.
リードフレームの外部リードは、強度を保つため、一定
量以上の板厚が必要である。また、リードフレームの製
造方法として、一般に、プレス加工法とエツチング加工
法とか用いられているが、共に、板厚の８０％程度の内
部リード間隔しか実現できない。The external leads of a lead frame must have a certain thickness or more in order to maintain strength. Furthermore, press working methods and etching methods are generally used as methods for manufacturing lead frames, but both can only achieve an internal lead spacing of about 80% of the plate thickness.
上述した従来のリードフレームは、板厚が一様であるた
め、内部リードピッヂのファイン化が板厚によって制限
されるという欠点がある。Since the conventional lead frame described above has a uniform plate thickness, there is a drawback that refinement of the internal lead pidge is limited by the plate thickness.
本発明の目的は、内部リートピッチのファイン化か可能
なリードフレームを提供することにある。An object of the present invention is to provide a lead frame that allows finer internal lead pitch.
本発明は、半導体装置用リードフレームにおいて、内部
リードの板厚が外部リードの板厚よりも薄く形成されて
いる。The present invention provides a lead frame for a semiconductor device in which the thickness of the internal leads is thinner than the thickness of the external leads.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）、（ｂ）は本発明の一実施例の平面図及び
Ａ−Ａ′線断面図である。FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line A-A' of an embodiment of the present invention.
第１図（ａ）、（ｂ）に示すように、内部リード１の厚
板は、外部リード２．ダムバー３．半導体素子搭載部４
の板厚よりも薄く形成されている。As shown in FIGS. 1(a) and 1(b), the thick plate of the internal lead 1 is connected to the external lead 2. Dam bar 3. Semiconductor element mounting section 4
It is formed thinner than the plate thickness of.
内部リード１は、リードフレーム加工時に、予め、板材
の内部リート１に対応する部分をハーフエツヂング等に
より薄くしておくことにより形成される。The internal leads 1 are formed by thinning a portion of a plate material corresponding to the internal leads 1 in advance by half etching or the like during lead frame processing.
このように、内部リード１の板厚を薄くすることにより
、ファインピッチ化が容易に行なえるようになる。By reducing the thickness of the internal leads 1 in this way, finer pitch can be easily achieved.
以上説明したように本発明のり−１へフレームは、内部
リートの板厚を外部リードの板厚よりも薄くすることに
より、同一外部リード板厚を有するり一ドフレームに比
して、内部リードのファイン化が容易にてきる効果があ
る。As explained above, the glue frame of the present invention has a thinner inner lead than the outer lead by making the inner lead thinner than the glue frame with the same outer lead thickness. This has the effect of making it easier to refine.
第１図（ａ＞、（ｂ）は本発明の一実施例の平面図及び
Ａ−Ａ’線断面図、第２図（ａ）。
（ｂ）は従来のリードフレームの一例の平面図及びＢ−
Ｂ’線断面図である。
１．１１・・・内部リード、２・・・外部リード、３・
ダムバー、４ 半導体素子搭載部。FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along line A-A' of an embodiment of the present invention, and FIG. 2(a) is a plan view and an example of a conventional lead frame. B-
It is a sectional view taken along the line B'. 1.11...Internal lead, 2...External lead, 3.
Dam bar, 4 Semiconductor element mounting part.
Claims (1)
板厚が外部リードの板厚よりも薄いことを特徴とするリ
ードフレーム。A lead frame for semiconductor devices, characterized in that the thickness of the internal leads is thinner than the thickness of the external leads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30348090A JPH04176156A (en) | 1990-11-08 | 1990-11-08 | Semiconductor device lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30348090A JPH04176156A (en) | 1990-11-08 | 1990-11-08 | Semiconductor device lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04176156A true JPH04176156A (en) | 1992-06-23 |
Family
ID=17921463
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30348090A Pending JPH04176156A (en) | 1990-11-08 | 1990-11-08 | Semiconductor device lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04176156A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996005612A1 (en) * | 1994-08-09 | 1996-02-22 | National Semiconductor Corporation | A fine pitch lead frame and method for manufacturing same |
| KR20010037247A (en) * | 1999-10-15 | 2001-05-07 | 마이클 디. 오브라이언 | Semiconductor package |
-
1990
- 1990-11-08 JP JP30348090A patent/JPH04176156A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996005612A1 (en) * | 1994-08-09 | 1996-02-22 | National Semiconductor Corporation | A fine pitch lead frame and method for manufacturing same |
| KR20010037247A (en) * | 1999-10-15 | 2001-05-07 | 마이클 디. 오브라이언 | Semiconductor package |
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