JPH02129937A - Pin grid array semiconductor device - Google Patents
Pin grid array semiconductor deviceInfo
- Publication number
- JPH02129937A JPH02129937A JP28444288A JP28444288A JPH02129937A JP H02129937 A JPH02129937 A JP H02129937A JP 28444288 A JP28444288 A JP 28444288A JP 28444288 A JP28444288 A JP 28444288A JP H02129937 A JPH02129937 A JP H02129937A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- pga
- type semiconductor
- semiconductor element
- tape
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 89
- 239000011347 resin Substances 0.000 claims abstract description 31
- 229920005989 resin Polymers 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims description 34
- 238000007789 sealing Methods 0.000 abstract description 19
- 238000000034 method Methods 0.000 abstract description 15
- 238000000465 moulding Methods 0.000 abstract description 6
- 238000005516 engineering process Methods 0.000 abstract description 2
- 239000002184 metal Substances 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000007767 bonding agent Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＴＡＢ （テープオートメイテッドポンディン
グ）法によって半導体素子とピングリッドアレイ基板の
配線パターンが接続されたピングリッドアレイ型半導体
装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pin grid array type semiconductor device in which a semiconductor element and a wiring pattern of a pin grid array substrate are connected by a TAB (tape automated bonding) method.
従来のピングリッドアレイ （以下、単にＰＧＡという
。）型半導体装置は第３図および第４図に示すように構
成されている。A conventional pin grid array (hereinafter simply referred to as PGA) type semiconductor device is constructed as shown in FIGS. 3 and 4.
第３図番主ワイヤ−ボンディング法によって半導体素子
とＰＧＡ基板の配線パターンとが接続された従来のＰＧ
Ａ型半導体装置を示す断面図、第４図はＴＡＢ法によっ
て半導体素子とＰＧＡ基板の配線パターンとが接続され
た従来のＰＧＡ型半導体装置を示す断面図を示す。これ
らの図において、１はＰＧＡ基板で、このＰＧＡ基板１
はガラスエポキシ基板からなり、その上面には配線パタ
ーン１ａが形成され、上面の略々中央部には後述する半
導体素子がボンディングされる座ぐり部１ｂが形成され
ている。また、このＰＧＡ基板１の側部には前記配線パ
ターンｌａと接続されかつ信号入出力用ビン２が装着さ
れるスルーホール１ｃが設けられている。３は半導体素
子で、この半導体素子３は上部ポンディングパッド（図
示せず）上に突起電極３ａが設けられ、前記ＰＧＡ基板
１の座ぐり部１ｂ内にグイポンド材４を介して接合され
ている。５ａは前記半導体素子３の突起電極３ａと前記
配線パターン１ａとを接続するための金属細線、５ｂは
ＴＡＢ法によってキャリアテープ（図示せず）上に形成
されたリードで、このリード５ｂのインナーリード部は
前記半導体素子３の突起電極３ａに加熱圧着されており
、アウターリード部は前記ＰＧＡ基板１の配線パターン
１ａに加熱圧着されている。６は前記配線パターン１ａ
を保護するための絶縁性コーテイング材、７は半導体素
子３を保護するための封止樹脂、８はこの封止樹脂７で
半導体素子３を保護するために封止樹脂７を十分厚く形
成するためのダムで、このダム８は前記座ぐり部１ｂの
周囲を囲むようにＰＧＡ基板１上に立設されており、こ
のダム８で囲まれた部位に封止樹脂７を滴下することに
よって半導体素子３が封止されることになる。Figure 3: Conventional PG in which the semiconductor element and the wiring pattern of the PGA board are connected by the main wire bonding method
FIG. 4 is a sectional view showing a conventional PGA type semiconductor device in which a semiconductor element and a wiring pattern of a PGA substrate are connected by the TAB method. In these figures, 1 is a PGA board, and this PGA board 1
is made of a glass epoxy substrate, a wiring pattern 1a is formed on the upper surface thereof, and a counterbore portion 1b to which a semiconductor element to be described later is bonded is formed approximately in the center of the upper surface. Furthermore, a through hole 1c is provided on the side of the PGA board 1, which is connected to the wiring pattern la and into which the signal input/output bin 2 is mounted. Reference numeral 3 denotes a semiconductor element, and this semiconductor element 3 has a protruding electrode 3a provided on an upper bonding pad (not shown), and is bonded to the counterbore 1b of the PGA substrate 1 via a bonding material 4. . 5a is a thin metal wire for connecting the protruding electrode 3a of the semiconductor element 3 and the wiring pattern 1a, 5b is a lead formed on a carrier tape (not shown) by the TAB method, and the inner lead of this lead 5b is The outer lead portion is heat-pressed to the protruding electrode 3a of the semiconductor element 3, and the outer lead portion is heat-pressed to the wiring pattern 1a of the PGA substrate 1. 6 is the wiring pattern 1a
7 is a sealing resin for protecting the semiconductor element 3; 8 is for forming the sealing resin 7 sufficiently thick to protect the semiconductor element 3 with this sealing resin 7; This dam 8 is erected on the PGA substrate 1 so as to surround the counterbore portion 1b, and by dropping the sealing resin 7 into the area surrounded by the dam 8, the semiconductor element is sealed. 3 will be sealed.
９は耐湿性を向上させるためのキャンプで、このキャッ
プ９は金属、あるいは、耐湿、耐熱性を有するプラスチ
ックによって形成され、ＰＧＡ基板基板側面および上面
全面を覆うように形成されており、接着剤１０によって
ＰＧＡ基板１に固着されている。また、前記キャップ９
は第３図および第４図に示すようにＰＧＡ基板基板側面
全面を覆うものの他に半導体素子３の上部のみを覆うよ
うに構成されたものもある。Reference numeral 9 denotes a cap for improving moisture resistance. This cap 9 is made of metal or moisture-resistant and heat-resistant plastic, and is formed to cover the entire side surface and top surface of the PGA substrate. It is fixed to the PGA board 1 by. In addition, the cap 9
As shown in FIGS. 3 and 4, there is one that covers the entire side surface of the PGA substrate, and another that covers only the upper part of the semiconductor element 3.
次に、従来のＰＧＡ型半導体装置の組立て方法について
説明する。第３図に示すワイヤボンディング法によって
半導体素子３とＰＧＡ１板１の配線パターン１ａとが接
続されたＰＧＡ型半導体装置を組み立てるには、先ず、
ＰＧＡ基板１の座ぐり部１ｂに半導体装置３をグイボン
ディングし、この半導体素子３の突起電極３ａとＰＧＡ
基板１の配線パターン１ａとを金属細線５ａによって接
続する。半導体素子３が座ぐり部１ｂ内に挿入されるこ
とによって、半導体素子３の上面と配線パターン１ａボ
ンデイング面との高低差が小さくなるため、金属細線５
ａが半導体素子３のエツジ部に接触し短絡するのを防止
することができる。そして、絶縁性コーテイング材６が
塗布されたＰＧＡ基板１上にダム８を立設し、このダム
８によって囲まれた範囲内に封止樹脂を滴下する。しか
る後、このように滴下して使用される封止樹脂７は耐湿
性が低いためにＰＧＡ基板１の上面全面および側面にキ
ャップ９を接着して組立てが終了する。また、第４図に
示すＴＡＢ法によって半導体素子３とＰＧＡ基板１の配
線パターン１ａとが接続されたＰＧＡ型半導体装置を組
み立てるには、予め、ＴＡＢ法によってリード５ｂのイ
ンナーリード部と半導体素子３の突起電極３ａとを接続
し、半導体素子３を前記リード５ｂを介してキャリアテ
ープ（図示せず）に保持させる。そして、前記リード５
ｂのアウターリード部を切断することによって半導体素
子３をキャリアテープから分断させる。このようにして
ＴＡＢ法によってリード５ｂがボンディングされた半導
体素子３をＰＧＡ基板１の座ぐり部１ｂ内にグイボンデ
ィングし、リード５ｂのアウターリード部をＰＧＡ基板
１上の配線パターンｌａに位置決めする。位置決め後、
アウターリード部と配線パターン１ａとを加熱・圧着等
により接続させる。しかる後、前記ワイヤボンディング
法によって半導体素子３とＰＧＡ基板１の配線パターン
１ａとが接続されたＰＧＡ型半導体装置の組み立て方法
と同様にして樹脂封止され、キャップ９を接着すること
によって組み立てが終了する。Next, a method for assembling a conventional PGA type semiconductor device will be described. To assemble the PGA type semiconductor device in which the semiconductor element 3 and the wiring pattern 1a of the PGA board 1 are connected by the wire bonding method shown in FIG.
The semiconductor device 3 is bonded to the counterbore portion 1b of the PGA substrate 1, and the protruding electrode 3a of the semiconductor element 3 and the PGA
The wiring pattern 1a of the substrate 1 is connected by a thin metal wire 5a. By inserting the semiconductor element 3 into the counterbore portion 1b, the height difference between the upper surface of the semiconductor element 3 and the bonding surface of the wiring pattern 1a becomes smaller, so that the fine metal wire 5
A can be prevented from contacting the edge portion of the semiconductor element 3 and causing a short circuit. Then, a dam 8 is set upright on the PGA substrate 1 coated with the insulating coating material 6, and a sealing resin is dropped within the area surrounded by the dam 8. Thereafter, since the sealing resin 7 used by dripping in this way has low moisture resistance, a cap 9 is adhered to the entire upper surface and side surfaces of the PGA substrate 1, and the assembly is completed. Furthermore, in order to assemble a PGA type semiconductor device in which the semiconductor element 3 and the wiring pattern 1a of the PGA substrate 1 are connected by the TAB method shown in FIG. The semiconductor element 3 is held on a carrier tape (not shown) via the leads 5b. And the lead 5
By cutting the outer lead portion b, the semiconductor element 3 is separated from the carrier tape. The semiconductor element 3 with the leads 5b bonded thereto by the TAB method is firmly bonded into the counterbore portion 1b of the PGA substrate 1, and the outer lead portion of the lead 5b is positioned on the wiring pattern la on the PGA substrate 1. After positioning,
The outer lead portion and the wiring pattern 1a are connected by heating, pressure bonding, or the like. Thereafter, the semiconductor element 3 and the wiring pattern 1a of the PGA substrate 1 are sealed with resin in the same manner as in the assembly method of a PGA type semiconductor device in which the wiring pattern 1a of the PGA substrate 1 is connected by the wire bonding method, and the assembly is completed by gluing the cap 9. do.
しかるに、従来のＰＧＡ型半導体装置においては、ＰＧ
Ａ基板１に座ぐり部１ｂを形成しなければならずＰＧＡ
基板１を製造するにあたりコストが嵩み、また、ダム８
やキャップ９等の部品が必要となるために製造プロセス
が複雑になるという問題があった。さらにまた、プラス
チックモールドタイプの半導体装置に較べて、封止樹脂
の材質が異なり、しかも、ＰＧＡ基板１には座ぐり部１
ｂが形成されていることにより、信鯨性上、特に耐湿性
が劣るという問題もあった。However, in conventional PGA type semiconductor devices, PG
A counterbore portion 1b must be formed on the A substrate 1.
The cost of manufacturing the substrate 1 increases, and the dam 8
There is a problem in that the manufacturing process becomes complicated because parts such as the cap 9 and the cap 9 are required. Furthermore, compared to a plastic mold type semiconductor device, the material of the sealing resin is different, and the PGA substrate 1 has a counterbore portion 1.
Due to the formation of b, there was also a problem in that reliability, especially moisture resistance, was poor.
本発明に係るＰＧＡ型半導体装置は、モールド樹脂でパ
ッケージが形成されたテープキャリアパッケージ型半導
体装置をピングリッドアレイ基板上に表面実装したもの
である。A PGA type semiconductor device according to the present invention is a tape carrier package type semiconductor device whose package is formed of molded resin and is surface mounted on a pin grid array substrate.
ＰＧＡ基板に半導体素子挿入用の座ぐり部が不要になり
、ＰＧＡ基板を容易に製造することができ、また、半導
体素子は封止樹脂をモールド成形することにより封止さ
れているため、高耐湿性を得るための部材数を減らすこ
とができるから、簡車な構造で耐湿性の高いＰＧＡ型半
導体装置が得られる。There is no need for a counterbore on the PGA board for inserting the semiconductor element, making it easier to manufacture the PGA board. Also, since the semiconductor element is sealed by molding the sealing resin, it has high moisture resistance. Since the number of components required to obtain the desired performance can be reduced, a PGA type semiconductor device with a compact structure and high moisture resistance can be obtained.
以下、本発明の一実施例を第１図および第２図によって
詳細に説明する。Hereinafter, one embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.
第１図は本発明に係るＰＧＡ型半導体装置を示す断面図
、第２図はモールド樹脂でパッケージが形成されたテー
プキャリアパッケージ型半導体装置を示す断面図である
。これらの図において前記第３図および第４図で説明し
たものと同一もしくは同等部材については同一符号を付
し、ここにおいて詳細な説明は省略する。これらの図に
おいて、１１はテープキャリアパッケージ型半導体装置
で、このテープキャリアパッケージ型半導体装置１１は
、ＴＡＢ法によりリード１２が接続された半導体素子３
を、封止樹脂１３をモールド成形することによって封止
して形成されている。１４はＴＡＢ法に使用されるキャ
リアテープで、このキャリアテープ１４上にリード１２
が形成されている。１５は半導体素子３の裏面電位を取
る場合に使用される金属キャップで、この金属キャップ
１５は、内側底部に半田等のろう材もしくは導電性接着
剤からなるグイボンド剤１６を介して半導体素子３が接
合され、開口縁部に形成されたフランジ部を前記キャリ
アテープ１４に接着させることによってキャリアテープ
１４に対して固定されている。また、この金属キャップ
１５は、図示しない接続手段によって前記リード１２に
接続され、半導体素子３の裏面電極（図示せず）とり−
ド１２とが接続されるように構成されている。FIG. 1 is a sectional view showing a PGA type semiconductor device according to the present invention, and FIG. 2 is a sectional view showing a tape carrier package type semiconductor device in which a package is formed of mold resin. In these figures, the same or equivalent members as those explained in FIGS. 3 and 4 are designated by the same reference numerals, and detailed explanation thereof will be omitted. In these figures, reference numeral 11 denotes a tape carrier package type semiconductor device, and this tape carrier package type semiconductor device 11 includes a semiconductor element 3 to which leads 12 are connected by the TAB method.
are sealed by molding a sealing resin 13. 14 is a carrier tape used in the TAB method, and a lead 12 is placed on this carrier tape 14.
is formed. Reference numeral 15 denotes a metal cap used to obtain the backside potential of the semiconductor element 3. This metal cap 15 has a bonding agent 16 made of a brazing material such as solder or a conductive adhesive on the inside bottom to which the semiconductor element 3 is attached. It is fixed to the carrier tape 14 by adhering the flange portion formed at the edge of the opening to the carrier tape 14. Further, this metal cap 15 is connected to the lead 12 by a connecting means (not shown), and is connected to the back electrode (not shown) of the semiconductor element 3.
It is configured such that it is connected to the card 12.
１７はＰＧＡ基板ｌの配線パターン１ｂにテープキャリ
アパッケージ型半導体装置１１のアウターリード１２ｂ
を接合するための半田等の導電性接合剤である。17 is an outer lead 12b of the tape carrier package type semiconductor device 11 on the wiring pattern 1b of the PGA board l.
It is a conductive bonding agent such as solder for bonding.
このテープキャリアパッケージ型半導体装置１１を組み
立てるには、先ず、キャリアテープ１４上にリード１２
を形成し、このリード１２のインナーリード部１２ａと
半導体素子３の突起電極３ａとを位置合わせした後、加
熱されたボンディングツール（図示せず）によって加熱
圧着させる。この際、半導体素子３は前記キャリアテー
プ１４によって保持されることになる。そして、半導体
素子３の裏面電位を取ることが必要な場合には、半導体
素子３を金属キャップ１５内に挿入させて半導体素子３
の裏面と金属キャップ１５の内側底面とをダイボンド剤
１６によって接着させる。次いで、半導体素子３をキャ
リアテープ１４ごとモールド金型（図示せず）内に型締
めし、トランスファーモールド法等によって封止樹脂１
３で封止する。なお、この際、半導体素子３の封止構造
は、第２図に示すような半導体素子３および金属キャン
プ１５を含む全体が覆われる構造の他に、半導体素子３
の上面側のみが封止樹脂１３で覆われる構造としてもよ
い。また、前記金属キャンプ１５を使用しない場合には
半導体素子３の全面を封止樹脂１３で覆うように封止さ
れる。To assemble this tape carrier package type semiconductor device 11, first, the leads 12 are placed on the carrier tape 14.
After aligning the inner lead portions 12a of the leads 12 and the protruding electrodes 3a of the semiconductor element 3, they are bonded under heat and pressure using a heated bonding tool (not shown). At this time, the semiconductor element 3 is held by the carrier tape 14. When it is necessary to take the backside potential of the semiconductor element 3, the semiconductor element 3 is inserted into the metal cap 15, and the semiconductor element 3 is inserted into the metal cap 15.
The back surface of the metal cap 15 and the inner bottom surface of the metal cap 15 are bonded together using a die bonding agent 16. Next, the semiconductor element 3 is clamped together with the carrier tape 14 in a mold (not shown), and the sealing resin 1 is sealed by a transfer molding method or the like.
Seal with 3. At this time, the sealing structure of the semiconductor element 3 is not only a structure in which the entire semiconductor element 3 and the metal camp 15 are covered as shown in FIG.
It is also possible to have a structure in which only the upper surface side of is covered with the sealing resin 13. Further, when the metal camp 15 is not used, the entire surface of the semiconductor element 3 is sealed with a sealing resin 13.
封止樹脂１３が硬化し樹脂パッケージが形成された後、
キャリアテープごと前記樹脂パッケージをモールド金型
から離型させる。次いで、リード１２のアウターリード
部１２ｂを切断することにより樹脂パッケージをキャリ
アテープ１４から分断させ、このアウターリード部１２
ｂを所定形状にリードフォミングしてテープキャリアパ
ッケージ型半導体装置１１が完成される。本発明に係る
ＰＧＡ型半導体装置は、以上のようにして形成されたテ
ープキャリアパッケージ型半導体装置１１を第１図に示
すようにＰＧＡ基板１上に表面実装して得られる。すな
わち、ＰＧＡ基板１上の配線パターン１ａに前記テープ
キャリアパッケージ型半導体装置１１のアウターリード
部１２ｂを位置決めし、これらを半田等の導電性接合剤
１７で接合してＰＧＡ型半導体装置が完成されることに
なる。After the sealing resin 13 is cured and a resin package is formed,
The resin package together with the carrier tape is released from the mold. Next, the resin package is separated from the carrier tape 14 by cutting the outer lead portion 12b of the lead 12, and the outer lead portion 12b is separated from the carrier tape 14.
The tape carrier package type semiconductor device 11 is completed by lead forming b into a predetermined shape. The PGA type semiconductor device according to the present invention is obtained by surface mounting the tape carrier package type semiconductor device 11 formed as described above on a PGA substrate 1 as shown in FIG. That is, the outer lead portion 12b of the tape carrier package type semiconductor device 11 is positioned on the wiring pattern 1a on the PGA substrate 1, and these are bonded with a conductive bonding agent 17 such as solder to complete the PGA type semiconductor device. It turns out.
したがって、ＰＧＡ基板１に半導体素子挿入用の座ぐり
部１ｂが不要になり、ＰＧＡ基板１を容易に製造するこ
とができる。また、半導体素子３は封止樹脂１３をモー
ルド成形することにより封止されているため、高耐湿性
を得るための部材（ダム８、キャンプ９等）数を減らす
ことができるから、簡単な構造で耐湿性の高いＰＧＡ型
半導体装置が得られる。なお、耐湿性は通常のプラスチ
ックパッケージ型半導体装置と同等であり、従来のＰＧ
Ａ型半導体装置に較べて良い結果が得られた。Therefore, the counterbore portion 1b for inserting the semiconductor element into the PGA substrate 1 is not required, and the PGA substrate 1 can be manufactured easily. Furthermore, since the semiconductor element 3 is sealed by molding the sealing resin 13, the number of components (dam 8, camp 9, etc.) required to obtain high moisture resistance can be reduced, resulting in a simple structure. A PGA type semiconductor device with high moisture resistance can be obtained. The moisture resistance is the same as that of ordinary plastic packaged semiconductor devices, and
Good results were obtained compared to the A-type semiconductor device.
一般に、テープキャリアパッケージ型半導体装置は、ア
ウターリードのピッチが０．２〜０．２５鶴であり、通
常のプラスチックパッケージ型半導体装置のリードのピ
ンチは０．５ ｔｍ以上であるために、通常のプラスチ
ックパッケージ型半導体装置に較べてリードのピッチが
非常に小さく取り扱い性が悪いが、本発明に示すように
テープキャリアパッケージ１１をＰＧＡ基板１上に搭載
することによって取り扱い性が改善され使い易くなり、
実装後に手直しするようなことが減り、不良率が低減さ
れる。In general, tape carrier package type semiconductor devices have an outer lead pitch of 0.2 to 0.25 tm, and a normal plastic package type semiconductor device has a lead pinch of 0.5 tm or more. Compared to a plastic package type semiconductor device, the pitch of the leads is very small, making it difficult to handle, but by mounting the tape carrier package 11 on the PGA substrate 1 as shown in the present invention, the handling is improved and the device becomes easier to use.
This reduces the number of adjustments that need to be made after mounting, and reduces the defective rate.
なお、本実施例ではＰＧＡ基板１上にテープキャリアパ
ッケージ型半導体装置１１を一個実装した例を示したが
、本発明はこのような限定にとられれることなく、ＰＧ
Ａ基板１上にテープキャリアパッケージ型半導体装置１
１を複数個実装してもよく、さらに、チップコンデンサ
、チップ抵抗等のチップ部品を同時に実装してもよい。Although this embodiment shows an example in which one tape carrier package type semiconductor device 11 is mounted on the PGA substrate 1, the present invention is not limited to such a limitation.
Tape carrier package type semiconductor device 1 on A substrate 1
1 may be mounted, and furthermore, chip components such as a chip capacitor and a chip resistor may be mounted at the same time.
以上説明したように本発明によれば、モールド樹脂でパ
ッケージが形成されたテープキャリアパッケージ型半導
体装置をピングリッドアレイ基板上に表面実装したため
、ＰＧＡ基板に半導体素子挿入用の座ぐり部が不要にな
り、ＰＧＡ基板を容易に製造することができ、ＰＧＡ基
板の製造コストを低く抑えることができる。また１、半
導体素子は封止樹脂をモールド成形することにより封止
されているため、高耐湿性を得るための部材数を減らす
ことができ構造が簡略化される。したがって、高密度実
装が可能でしかも耐湿性の高いＰＧＡ型半導体装置を安
価に得ることができる。As explained above, according to the present invention, a tape carrier package type semiconductor device whose package is formed with molded resin is surface mounted on a pin grid array substrate, thereby eliminating the need for a counterbore for inserting a semiconductor element in a PGA substrate. Therefore, the PGA substrate can be easily manufactured, and the manufacturing cost of the PGA substrate can be kept low. In addition, 1. Since the semiconductor element is sealed by molding a sealing resin, the number of members required to obtain high moisture resistance can be reduced and the structure can be simplified. Therefore, a PGA type semiconductor device that can be mounted at high density and has high moisture resistance can be obtained at low cost.
第１図は本発明に係るＰＧＡ型半導体装置を示す断面図
、第２図はモールド樹脂でパッケージが形成された本発
明に係るテープキャリアパッケージ型半導体装置を示す
断面図、第３図はワイヤーボンディング法によって半導
体素子とＰＧＡ基板の配線パターンとが接続された従来
のＰＧＡ型半導体装置を示す断面図、第４図はＴＡＢ法
によって半導体素子とＰＧＡ基板の配線パターンとが接
続された従来のＰＧＡ型半導体装置を示す断面図である
。
１・・・・ピングリッドアレイ基板、３・・・・半導体
素子、１１・・・・テープキャリアパッケージ型半導体
装置、１３・・・・封止樹脂。
第１ 図FIG. 1 is a cross-sectional view showing a PGA type semiconductor device according to the present invention, FIG. 2 is a cross-sectional view showing a tape carrier package type semiconductor device according to the present invention in which a package is formed of molded resin, and FIG. 3 is a wire bonding FIG. 4 is a cross-sectional view showing a conventional PGA type semiconductor device in which a semiconductor element and a wiring pattern on a PGA substrate are connected by the TAB method. FIG. 2 is a cross-sectional view showing a semiconductor device. DESCRIPTION OF SYMBOLS 1... Pin grid array board, 3... Semiconductor element, 11... Tape carrier package type semiconductor device, 13... Sealing resin. Figure 1
Claims (1)
パッケージ型半導体装置をピングリッドアレイ基板上に
表面実装したことを特徴とするピングリッドアレイ型半
導体装置。A pin grid array type semiconductor device characterized in that a tape carrier package type semiconductor device whose package is formed of molded resin is surface mounted on a pin grid array substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28444288A JPH02129937A (en) | 1988-11-09 | 1988-11-09 | Pin grid array semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28444288A JPH02129937A (en) | 1988-11-09 | 1988-11-09 | Pin grid array semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02129937A true JPH02129937A (en) | 1990-05-18 |
Family
ID=17678597
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28444288A Pending JPH02129937A (en) | 1988-11-09 | 1988-11-09 | Pin grid array semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02129937A (en) |
-
1988
- 1988-11-09 JP JP28444288A patent/JPH02129937A/en active Pending
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