JPH02128474U - - Google Patents
Info
- Publication number
- JPH02128474U JPH02128474U JP3675489U JP3675489U JPH02128474U JP H02128474 U JPH02128474 U JP H02128474U JP 3675489 U JP3675489 U JP 3675489U JP 3675489 U JP3675489 U JP 3675489U JP H02128474 U JPH02128474 U JP H02128474U
- Authority
- JP
- Japan
- Prior art keywords
- supplied
- switch circuit
- video signal
- signal
- image memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 1
Landscapes
- Studio Circuits (AREA)
Description
第１図はこの考案の一実施例の構成図、第２図
はワイプタイミング発生器の構成図、第３図はそ
の動作説明のための図、第４図は実施例における
ワイプ画面を示す図、第５図は従来例におけるワ
イプ画面を示す図である。
１……撮像素子、２……ＡＧＣアンプ、３……
プロセス回路、４，７……レベル検出器、６……
アイリス、１１，２０……Ａ／Ｄ変換器、１２，
２２……デイジタル処理回路、１３……メモリ制
御回路、１４……コントローラ、１５……ワイプ
タイミング発生器、１６……キーボード、１７…
…ワイプ用の操作スイツチ、１８，２４……Ｄ／
Ａ変換器、１９……ＶＴＲ、２１……色復調回路
、２３……色変調回路、２５……ＶＴＲ制御回路
、２６……記録用の操作スイツチ、２７……エン
コーダ。
Fig. 1 is a block diagram of an embodiment of this invention, Fig. 2 is a block diagram of a wipe timing generator, Fig. 3 is a diagram for explaining its operation, and Fig. 4 is a diagram showing a wipe screen in the embodiment. , FIG. 5 is a diagram showing a wipe screen in a conventional example. 1...Image sensor, 2...AGC amplifier, 3...
Process circuit, 4, 7... Level detector, 6...
Iris, 11, 20...A/D converter, 12,
22... Digital processing circuit, 13... Memory control circuit, 14... Controller, 15... Wipe timing generator, 16... Keyboard, 17...
...Wipe operation switch, 18, 24...D/
A converter, 19...VTR, 21...color demodulation circuit, 23...color modulation circuit, 25...VTR control circuit, 26...recording operation switch, 27...encoder.
Claims (1)
スイツチ回路の出力信号が画像メモリに書き込み
信号として供給され、この画像メモリより読み出
される出力映像信号が上記スイツチ回路に供給さ
れ、 上記スイツチ回路にはワイプタイミング発生器
よりタイミング信号が供給され、上記入力映像信
号の選択期間が水平方向または垂直方向に順次長
くされることを特徴とする映像信号処理装置。[Claims for Utility Model Registration] An input video signal is supplied to a switch circuit, an output signal from this switch circuit is supplied to an image memory as a write signal, and an output video signal read from this image memory is supplied to the switch circuit. . A video signal processing device, wherein a timing signal is supplied from a wipe timing generator to the switch circuit, and a selection period of the input video signal is sequentially lengthened in a horizontal direction or a vertical direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3675489U JPH02128474U (en) | 1989-03-30 | 1989-03-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3675489U JPH02128474U (en) | 1989-03-30 | 1989-03-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02128474U true JPH02128474U (en) | 1990-10-23 |
Family
ID=31543264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3675489U Pending JPH02128474U (en) | 1989-03-30 | 1989-03-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02128474U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6462086A (en) * | 1987-09-02 | 1989-03-08 | Canon Kk | Pattern switching device |
-
1989
- 1989-03-30 JP JP3675489U patent/JPH02128474U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6462086A (en) * | 1987-09-02 | 1989-03-08 | Canon Kk | Pattern switching device |