JPH02137169U - - Google Patents
Info
- Publication number
- JPH02137169U JPH02137169U JP4489089U JP4489089U JPH02137169U JP H02137169 U JPH02137169 U JP H02137169U JP 4489089 U JP4489089 U JP 4489089U JP 4489089 U JP4489089 U JP 4489089U JP H02137169 U JPH02137169 U JP H02137169U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- video
- circuit
- date
- video signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000003780 insertion Methods 0.000 claims 3
- 230000037431 insertion Effects 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Landscapes
- Television Signal Processing For Recording (AREA)
- Studio Circuits (AREA)
Description
第１図はこの考案の一実施例を示す構成図、第
２図〜第４図はその説明のための図である。
１……撮像素子、２……ＡＧＣランプ、３……
プロセス回路、４，７……レベル検出器、６……
アイリス、１１……エンコーダ、１２，２６……
Ａ／Ｄ変換器、１３，２８……フイールドメモリ
、１４……メモリ制御回路、１５……コントロー
ラ、１６……キーボード、１７，１８，１９……
操作キー、２０，３０……Ｄ／Ａ変換器、２１，
３１……切換スイツチ、２２……加算器、２３…
…ＶＴＲ、２４……日付回路、２５……接続スイ
ツチ、３２……ＶＴＲ制御回路、３４……電子ビ
ユーフアインダ。
FIG. 1 is a block diagram showing one embodiment of this invention, and FIGS. 2 to 4 are diagrams for explaining the same. 1...Image sensor, 2...AGC lamp, 3...
Process circuit, 4, 7... Level detector, 6...
Iris, 11... Encoder, 12, 26...
A/D converter, 13, 28... Field memory, 14... Memory control circuit, 15... Controller, 16... Keyboard, 17, 18, 19...
Operation key, 20, 30...D/A converter, 21,
31...Selector switch, 22...Adder, 23...
...VTR, 24...Date circuit, 25...Connection switch, 32...VTR control circuit, 34...Electronic viewfinder.
Claims (1)
面用の映像信号を形成する画像メモリを有してな
る信号処理回路と、 日付表示信号を形成する日付回路と、 上記ビデオカメラからの映像信号に上記信号処
理回路からの子画面用の映像信号を挿入する第１
の挿入回路と、 この第１の挿入回路の出力信号に上記日付回路
からの日付表示信号を挿入する第２の挿入回路と
、 上記信号処理回路からの子画面用の映像信号の
出力タイミングおよび上記日付回路からの日付表
示信号の出力タイミングを制御するコントローラ
とを備え、 上記子画面用の映像信号および上記日付表示信
号の出力タイミングが異なるようにされ、 上記第２の挿入回路の出力信号がビデオテープ
レコーダに記録信号として供給されることを特徴
とするビデオテープレコーダ装置。[Claims for Utility Model Registration] A signal processing circuit having an image memory for forming a video signal for a sub-screen of a still image from a video signal from a video camera, a date circuit for forming a date display signal, and the above. A first part that inserts a video signal for a sub-screen from the signal processing circuit into a video signal from a video camera.
a second insertion circuit that inserts a date display signal from the date circuit into the output signal of the first insertion circuit; an output timing of the video signal for the child screen from the signal processing circuit; a controller for controlling the output timing of the date display signal from the date circuit, the output timing of the video signal for the child screen and the date display signal are different from each other, and the output signal of the second insertion circuit is set to be a video signal. A video tape recorder device characterized in that the video tape recorder is supplied as a recording signal to a tape recorder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4489089U JPH0510462Y2 (en) | 1989-04-17 | 1989-04-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4489089U JPH0510462Y2 (en) | 1989-04-17 | 1989-04-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02137169U true JPH02137169U (en) | 1990-11-15 |
| JPH0510462Y2 JPH0510462Y2 (en) | 1993-03-15 |
Family
ID=31558591
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4489089U Expired - Lifetime JPH0510462Y2 (en) | 1989-04-17 | 1989-04-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0510462Y2 (en) |
-
1989
- 1989-04-17 JP JP4489089U patent/JPH0510462Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0510462Y2 (en) | 1993-03-15 |
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