JPH02122534A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPH02122534A
JPH02122534A JP63275591A JP27559188A JPH02122534A JP H02122534 A JPH02122534 A JP H02122534A JP 63275591 A JP63275591 A JP 63275591A JP 27559188 A JP27559188 A JP 27559188A JP H02122534 A JPH02122534 A JP H02122534A
Authority
JP
Japan
Prior art keywords
resin plate
thermoplastic resin
wiring
wiring layer
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63275591A
Other languages
Japanese (ja)
Inventor
Yuji Yokomizo
雄二 横溝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Lighting and Technology Corp
Original Assignee
Toshiba Lighting and Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Lighting and Technology Corp filed Critical Toshiba Lighting and Technology Corp
Priority to JP63275591A priority Critical patent/JPH02122534A/en
Publication of JPH02122534A publication Critical patent/JPH02122534A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To assure the use of a large current and miniaturized high density mounting as well as simplify the processes of manufacture by eliminating soldering connection and improve reliability of the circuit by using a metal plate as a wiring pattern. CONSTITUTION:A semiconductor chip 2 having a lead terminal 2a is disposed at an opening section 1a in a first thermoplastic resin plate 1 comprising polycarbonate, etc., and a wiring pattern 3 comprising a metal plate of substantially the same thickness as the semiconductor chip 2 is disposed. A second thermoplastic resin plate 4 is integrally connected to the first resin plate 1 by thermocompression bonding. A wiring layer 5 is formed into a multi-layer on the resin plate 4, and an opening section 4a is formed in the lower surface portion of the resin plate 4 corresponding to part of the wiring layer 5. The lead terminal 2a of the semiconductor chip 2 is inserted into the opening section 4a upon thermocompression bonding between the first and second resin plates 1, 4 and electrically connected to the wiring layer 5. The metal plate is patterned and used as wiring in such a manner, and miniaturized high density mounting can be realized.

Description

【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は混成集積回路に関し、特に電子機器の小型化を
達成しえる混成集積回路に係わる。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a hybrid integrated circuit, and particularly to a hybrid integrated circuit that can achieve miniaturization of electronic equipment.

（従来の技術） 周知の如く、電子機器の小型化を実現するため、回路の
高密度実装技術としてハイブリッドＩＣ（混成集積回路
）が広く使用されている。ここで、混成集積回路は、ア
ルミナ又はガラスエポキシ基板に配線が厚膜印刷により
（又は金属箔で）形成され、その上に半導体チップやそ
の他の半導体部品が半田付で実装された構成となってい
る。(Prior Art) As is well known, hybrid ICs (hybrid integrated circuits) are widely used as a high-density packaging technology for circuits in order to realize miniaturization of electronic devices. Here, a hybrid integrated circuit has a structure in which wiring is formed by thick film printing (or with metal foil) on an alumina or glass epoxy substrate, and semiconductor chips and other semiconductor components are mounted on it by soldering. There is.

しかしながら、従来の混成集積回路によれば、高集積化
を進めるにつれてエネルギー素子の高密度実装化が不可
欠であるが、現状ではエネルギー素子を十分高密度実装
化できない。また、従来、アルミナ又はガラスエポキシ
基板上に半導体チップやその他の半導体部品を半田付で
実装するが、半田付工程は半導体素子に悪い影響を与え
、信頓性を低下させるという欠点を存する。However, according to conventional hybrid integrated circuits, as the degree of integration increases, it is essential to package energy devices at a high density, but at present it is not possible to package energy devices at a sufficiently high density. Furthermore, conventionally, semiconductor chips and other semiconductor components are mounted on an alumina or glass epoxy substrate by soldering, but the soldering process has a disadvantage in that it has a negative effect on semiconductor elements and reduces reliability.

（発明が解決しようとする課題） 本発明は上記事情に鑑みてなされたもので、金属板を配
線パターンに使用することにより大電流を流しえかつ小
型高密度実装が可能になるとともに、半田接続をなくし
て工程の簡略化、信頼性を向上しえる混成集積回路を提
供することを目的とする。(Problems to be Solved by the Invention) The present invention has been made in view of the above circumstances, and by using a metal plate as a wiring pattern, it is possible to flow a large current and achieve compact and high-density packaging, and also enables solder connection. The purpose of the present invention is to provide a hybrid integrated circuit that can simplify the process and improve reliability by eliminating the process.

［発明の構成］ （課題を解決するための手段） 本願第１の発明は、リード端子を有した半導体素子及び
該半導体素子と略同一厚さの配線パターンを夫々配置し
た第１熱可塑性樹脂板と、この樹脂板に熱圧着され、内
部に配線層を有するとともに前記樹脂板と熱圧着される
側に前記配線層とリード端子とを接続させる開口部を有
する第２熱可塑性樹脂板とを具備することを特徴とする
混成集積回路である。[Structure of the Invention] (Means for Solving the Problems) The first invention of the present application provides a semiconductor element having lead terminals and a first thermoplastic resin plate on which a wiring pattern having approximately the same thickness as the semiconductor element is arranged. and a second thermoplastic resin plate that is thermocompression bonded to the resin plate, has a wiring layer therein, and has an opening for connecting the wiring layer and the lead terminal on the side that is thermocompression bonded to the resin plate. It is a hybrid integrated circuit characterized by:

本願第１発明において、半導体素子は通常第１熱可塑性
樹脂板に開口された開口部に配置され、又配線パターン
は通常外側に延出されている。In the first aspect of the present invention, the semiconductor element is usually arranged in an opening formed in the first thermoplastic resin plate, and the wiring pattern is usually extended to the outside.

本願第２の発明は、配線パターンを該パターンの一部が
露出するように被覆した第１熱可塑性樹脂板と、この樹
脂板に熱圧着され、内部にリード端子を有した半導体素
子や配線層を実装し前記リード端子を前記樹脂板の配線
パターンに接続する第２熱可塑性樹脂板とを具備するこ
とを特徴とする混成集積回路である。The second invention of the present application provides a first thermoplastic resin plate that covers a wiring pattern so that a part of the pattern is exposed, and a semiconductor element and a wiring layer that are thermocompression bonded to the resin plate and have lead terminals inside. and a second thermoplastic resin plate on which the lead terminal is mounted and the lead terminal is connected to the wiring pattern of the resin plate.

本願第２発明において、半導体素子や配線層は通常第２
熱可塑性樹脂板にそれらの一部を露出又は完全に樹脂封
止された状態で組込まれている。In the second invention of the present application, the semiconductor element and the wiring layer are usually
They are incorporated into the thermoplastic resin plate with some of them exposed or completely sealed with resin.

本願第１．第２発明において、第１・第２熱可塑性樹脂
板の材質は同じであることが望ましいが、必ずしも同じ
である必要はなく十分な熱圧着が可能なものであればよ
い。前記熱可塑性樹脂板の材質としては、ポリエチレン
、ポリスチレン、ポリカーボネイト、ポリ塩化ビニル、
酢酸セルロース。This application No. 1. In the second invention, it is desirable that the first and second thermoplastic resin plates are made of the same material, but they do not necessarily have to be made of the same material as long as they can be bonded by sufficient thermocompression. The material of the thermoplastic resin plate includes polyethylene, polystyrene, polycarbonate, polyvinyl chloride,
Cellulose acetate.

塩化ゴムが挙げられる。Examples include chlorinated rubber.

（作用） 本発明においては、金属板を配線パターンに使用するこ
とにより大電流を流しえかっ小型高密度実装が可能にな
るとともに、半田接続をなくして工程の簡略化、信頼性
を向上できる。(Function) In the present invention, by using a metal plate as a wiring pattern, it is possible to carry out a large current and achieve compact, high-density packaging, and also to eliminate solder connections, thereby simplifying the process and improving reliability.

以下、本発明の実施例について第１図及び第２図を参照
して説明する。Embodiments of the present invention will be described below with reference to FIGS. 1 and 2.

（実施例１） 第１図（Ａ）、（Ｂ）を参照する。ここで、同図（Ａ）
は第１熱可塑性樹脂板と第２熱可塑性樹脂板を切離した
状態の説明図、同図（Ｂ）は両樹脂板が一体化した状態
の説明図である。(Example 1) Refer to FIGS. 1(A) and (B). Here, the same figure (A)
1 is an explanatory view of a state in which the first thermoplastic resin plate and a second thermoplastic resin plate are separated, and FIG.

図中の１は、適宜な位置に開口部１ａを開口した例えば
ポリカーボネイトからなる第１熱可塑性樹脂板である。1 in the figure is a first thermoplastic resin plate made of polycarbonate, for example, with openings 1a opened at appropriate positions.

」この樹脂板１の開口部１ａにはリード端子２ａを有し
た半導体チップ（半導体素子）２が配置され、更に前記
半導体チップ２と略同一厚さの金属板からなる配線パタ
ーン３が配置されている。前記第１熱可塑性樹脂板１に
は、第２熱可塑性樹脂板４が熱圧着により一体化されて
いる。A semiconductor chip (semiconductor element) 2 having lead terminals 2a is placed in the opening 1a of the resin plate 1, and a wiring pattern 3 made of a metal plate having approximately the same thickness as the semiconductor chip 2 is placed. There is. A second thermoplastic resin plate 4 is integrated with the first thermoplastic resin plate 1 by thermocompression bonding.

この樹脂板４には、配線層５が多層に形成されている。This resin board 4 has multiple wiring layers 5 formed thereon.

この配線層５の一部に対応する前記樹脂板４の下面部分
には開口部４ａが設けられており、第１・第２熱可塑性
樹脂板１，４の熱圧着時に半導体チップ２のリード端子
２ａが前記開口部４ａに挿入され、第２熱可塑性樹脂板
４の配線層５と電気的に接続するようになっている。An opening 4a is provided in the lower surface portion of the resin plate 4 corresponding to a part of the wiring layer 5, and the lead terminal of the semiconductor chip 2 is formed during thermocompression bonding of the first and second thermoplastic resin plates 1 and 4. 2a is inserted into the opening 4a and electrically connected to the wiring layer 5 of the second thermoplastic resin plate 4.

しかして、上記実施例によれば、半導体チップ２及びこ
の半導体チップ２と略同一厚さの金属板からなる配線パ
ターン３を配置した第１熱可塑性樹脂板１と、多層化さ
れた配線層５を有する第２熱可塑性樹脂板４を熱圧着に
より一体化した構成となっている。しかるに、金属板を
パターン化して配線として用いるため、大電流を流すこ
とができるとともに、小型高密度実装を実現できる。ま
た、従来のように半田接続をする必要がないため、工程
が簡略されるとともに、半導体チップ２に悪影響を及ぼ
すことがなく信頼性の低下を回避できる。According to the above embodiment, the first thermoplastic resin plate 1 on which the semiconductor chip 2 and the wiring pattern 3 made of a metal plate having substantially the same thickness as the semiconductor chip 2 are disposed, and the multilayer wiring layer 5 It has a structure in which the second thermoplastic resin plate 4 having the following properties is integrated by thermocompression bonding. However, since a metal plate is patterned and used as wiring, a large current can flow and compact, high-density packaging can be realized. Further, since there is no need to make solder connections as in the conventional method, the process is simplified, and there is no adverse effect on the semiconductor chip 2, thereby avoiding a decrease in reliability.

（実施例２） 第２図（Ａ）、（Ｂ）を参照する。ここで、同図（Ａ）
は第１熱可塑性樹脂板と第２熱可塑性樹指板を切離した
状態の説明図、同図（Ｂ）は両樹脂板が一体化した状態
の説明図である。但し、実施例１と同部材は同符号を付
して説明を省略する。(Example 2) Refer to FIGS. 2(A) and (B). Here, the same figure (A)
1 is an explanatory view of a state where the first thermoplastic resin plate and a second thermoplastic resin board are separated, and FIG. However, the same members as those in Example 1 are given the same reference numerals, and the description thereof will be omitted.

本実施例２は、実施例１と比べ、半導体チップ２やコン
デンサ、抵抗等のチップ部品１１を第２熱可塑性樹脂板
４内に実装化するとともに、前記チップ部品１１を任意
の配線層５に接続させている点が大きく異なる。In comparison with the first embodiment, in the second embodiment, a semiconductor chip 2, a capacitor, a resistor, and other chip components 11 are mounted in the second thermoplastic resin plate 4, and the chip components 11 are mounted on an arbitrary wiring layer 5. The difference is in how they are connected.

実施例２によれば、実施例１と同様、大電流を流すこと
ができるとともに、小型高密度実装化の実現、工程の簡
略化、信頼性の向上をなしえる。According to the second embodiment, as in the first embodiment, a large current can be passed, and it is also possible to realize compact and high-density packaging, simplify the process, and improve reliability.

なお、上記実施例では、金属板をパターン化して配線と
して用いた場合について述べたが、これに限らず、リー
ド端子として用いることもできる。In the above embodiments, a case has been described in which a metal plate is patterned and used as a wiring, but the pattern is not limited to this, and the metal plate can also be used as a lead terminal.

なお、上記実施例では第１・第２熱可塑性樹脂板の材質
としてポリカーボネイトを用いた場合について述べたが
、これに限らない。例えば、ポリエチレン、ポリスチレ
ン等を用いてもよいし、また第１・第２の熱可塑性樹脂
板の材質は夫々異ならせてもよい。In addition, although the above-mentioned example described the case where polycarbonate was used as the material of the first and second thermoplastic resin plates, the present invention is not limited to this. For example, polyethylene, polystyrene, etc. may be used, and the materials of the first and second thermoplastic resin plates may be different from each other.

［発明の効果］ 以上詳述した如く本発明によれば、金属板を配線パター
ンに使用することにより大電流を流しえかつ小型高密度
実装が可能になるとともに、半田接続をなくして工程の
簡略化、信頼性を向上しえる混成集積回路を提供できる
。[Effects of the Invention] As detailed above, according to the present invention, by using a metal plate as a wiring pattern, a large current can flow and compact, high-density packaging is possible, and the process is simplified by eliminating solder connections. It is possible to provide a hybrid integrated circuit that can improve reliability and reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（Ａ）、（Ｂ）は本発明の一実施例に係る混成集
積回路を示し、同図（Ａ）は第１熱可塑性樹脂板と第２
熱可塑性樹脂板を切離した状態の説明図、同図（Ｂ）は
両樹脂板が一体化した状態の説明図、第２図（Ａ）、（
Ｂ）は本発明に係る混成集積回路の他の例を示し、同図
（Ａ）は第１熱可塑性樹脂板と第２熱可塑性樹脂板を切
離した状態の説明図、同図（Ｂ）は両樹脂板が一体化し
た状態の説明図である。 １．４・・・熱可塑性樹脂板、２・・・半導体チップ、
３・・・配線パターン、５・・・配線層、１１・・・チ
ップ部品。 出願人代理人　　弁理士　鈴江武彦 第 図 第 ２図FIGS. 1(A) and 1(B) show a hybrid integrated circuit according to an embodiment of the present invention, in which FIG. 1(A) shows a first thermoplastic resin plate and a second thermoplastic resin plate.
An explanatory diagram of the state in which the thermoplastic resin plate is separated, FIG. 2 (B) is an explanatory diagram of the state in which both the resin plates are integrated,
B) shows another example of the hybrid integrated circuit according to the present invention, in which (A) is an explanatory diagram with the first thermoplastic resin plate and the second thermoplastic resin plate separated, and (B) is It is an explanatory view of a state where both resin plates are integrated. 1.4... Thermoplastic resin plate, 2... Semiconductor chip,
3... Wiring pattern, 5... Wiring layer, 11... Chip component. Applicant's agent Patent attorney Takehiko Suzue Figure 2

Claims (2)

【特許請求の範囲】[Claims] （１）リード端子を有した半導体素子及び該半導体素子
と略同一厚さの金属板からなる配線パターンを夫々配置
した第１熱可塑性樹脂板と、この樹脂板に熱圧着され，
内部に配線層を有するとともに前記樹脂板と熱圧着され
る側に前記配線層とリード端子とを接続させる開口部を
有する第２熱可塑性樹脂板とを具備することを特徴とす
る混成集積回路。(1) a first thermoplastic resin plate on which a semiconductor element having lead terminals and a wiring pattern made of a metal plate having approximately the same thickness as the semiconductor element are arranged;
1. A hybrid integrated circuit comprising: a second thermoplastic resin plate having a wiring layer therein and an opening for connecting the wiring layer and a lead terminal on the side to be thermocompression bonded to the resin plate. （２）配線パターンを該パターンの一部が露出するよう
に被覆した第１熱可塑性樹脂板と、この樹脂板に熱圧着
され，内部にリード端子を有した半導体素子や配線層を
実装し前記リード端子を前記樹脂板の配線パターンに接
続する第２熱可塑性樹脂板とを具備することを特徴とす
る混成集積回路。(2) A first thermoplastic resin plate that covers a wiring pattern so that a part of the pattern is exposed; a semiconductor element and a wiring layer that are bonded by thermocompression and have lead terminals inside are mounted on this resin plate; A hybrid integrated circuit comprising: a second thermoplastic resin plate that connects lead terminals to the wiring pattern of the resin plate.
JP63275591A 1988-10-31 1988-10-31 Hybrid integrated circuit Pending JPH02122534A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63275591A JPH02122534A (en) 1988-10-31 1988-10-31 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63275591A JPH02122534A (en) 1988-10-31 1988-10-31 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPH02122534A true JPH02122534A (en) 1990-05-10

Family

ID=17557588

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63275591A Pending JPH02122534A (en) 1988-10-31 1988-10-31 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPH02122534A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1536673A1 (en) * 2002-05-30 2005-06-01 Taiyo Yuden Co., Ltd. Composite multi-layer substrate and module using the substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1536673A1 (en) * 2002-05-30 2005-06-01 Taiyo Yuden Co., Ltd. Composite multi-layer substrate and module using the substrate
EP1536673A4 (en) * 2002-05-30 2008-08-27 Taiyo Yuden Kk Composite multi-layer substrate and module using the substrate
USRE45146E1 (en) 2002-05-30 2014-09-23 Taiyo Yuden Co., Ltd Composite multi-layer substrate and module using the substrate

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