JPH0212015B2 - - Google Patents
Info
- Publication number
- JPH0212015B2 JPH0212015B2 JP3698681A JP3698681A JPH0212015B2 JP H0212015 B2 JPH0212015 B2 JP H0212015B2 JP 3698681 A JP3698681 A JP 3698681A JP 3698681 A JP3698681 A JP 3698681A JP H0212015 B2 JPH0212015 B2 JP H0212015B2
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- metal
- annealing
- gate
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052751 metal Inorganic materials 0.000 claims description 45
- 239000002184 metal Substances 0.000 claims description 45
- 238000000137 annealing Methods 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 9
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 150000002739 metals Chemical class 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 229910052758 niobium Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 229910052726 zirconium Inorganic materials 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 2
- 229910052735 hafnium Inorganic materials 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 15
- 238000005468 ion implantation Methods 0.000 description 12
- 230000001681 protective effect Effects 0.000 description 6
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 5
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 108091006146 Channels Proteins 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- -1 and Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910017401 Au—Ge Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
本発明は、シヨツトキ障壁ゲート電界効果トラ
ンジスタ（MESFET）特にGaAs MESFETの
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing shot barrier gate field effect transistors (MESFETs), particularly GaAs MESFETs.
GaAs等−化合物半導体は、電子速度がSi
に較べてはるかに大きいところから、マイクロ波
帯の素子に適しており、例えばGaAs MESFET
はマイクロ波増幅素子として広範囲に用いられて
いる。かかるGaAs MESFETを論理集積回路等
にまで応用範囲を広げるためには、第１図に示す
ような、プレーナ型であり、かつ直列抵抗を減す
るために、ソース・ドレイン領域にn+領域１３，
１４が設けられた構造であることが望ましい。な
お１１は高抵抗基板、１２はｎ型チヤンネル層、
１５はゲートシヨツトキ電極、１６はソース電
極、１７はドレイン電極である。ここでGaAsへ
の選択拡散の難しいこと、および量産性を考慮す
るとn+領域１３，１４は、選択イオン注入で形
成することが一般的である。またGaAs本来の高
速性を十分発揮させるためには、ゲート長LGは
小さく（例えば0.5μｍ）、かつn+領域１３とゲー
ト１５との間隔LSGもごく微小（例えば0.5μｍ以
下）である必要がある。なぜならばGaAs表面に
は表面空乏層が存在し、LSGが大きいと抵抗が大
きくなるからである。しかしながら従来かかる構
造のMESFETは、まずイオン注入およびアニー
ルによつてn+領域１３および１４を形成した後、
通常のマスク合せによつてゲート電極１５を形成
していたため、LSGを微小距離に保つことは非常
に困難であつた。したがつて、ゲート電極１５
は、n+領域１３，１４に対してセルフアライメ
ントで形成される必要がある。 In compound semiconductors such as GaAs, the electron velocity is
It is suitable for microwave band devices because it is much larger than GaAs MESFETs, such as GaAs MESFETs.
are widely used as microwave amplification elements. In order to expand the scope of application of such GaAs MESFETs to logic integrated circuits, etc., it is necessary to adopt a planar type as shown in FIG. 1, and to reduce the series resistance, n + regions 13,
14 is desirable. Note that 11 is a high resistance substrate, 12 is an n-type channel layer,
15 is a gate shot electrode, 16 is a source electrode, and 17 is a drain electrode. Considering the difficulty of selective diffusion into GaAs and mass productivity, the n + regions 13 and 14 are generally formed by selective ion implantation. In addition, in order to fully utilize the inherent high-speed performance of GaAs, the gate length L G is small (for example, 0.5 μm), and the distance L SG between the n + region 13 and the gate 15 is also extremely small (for example, 0.5 μm or less). There is a need. This is because a surface depletion layer exists on the GaAs surface, and a large LSG results in a large resistance. However, in the conventional MESFET with this structure, after forming the n + regions 13 and 14 by ion implantation and annealing,
Since the gate electrode 15 was formed by normal mask alignment, it was extremely difficult to maintain the LSG at a minute distance. Therefore, the gate electrode 15
must be formed in self-alignment with respect to the n + regions 13 and 14.
セルフアライメントの方法の一つは、Siの
MOS型FETでよく行われるように、第２図のご
とく、耐熱性のあるゲート電極１５を形成し、該
ゲート電極１５をマスクにして、ソースおよびド
レイン領域のイオン注入を行い、ゲート１５を被
着したままでアニールを行つてn+領域１３およ
び１４を形成することが考えられる。しかしなが
ら、この方法では、ゲート電極１５がMOS型で
はなく、シヨツトキ型であるので、n+領域１３
および１４と接するためにゲート耐圧が著しく低
下する欠点がある。特に、ゲート電極１５を完全
矩形断面に形成することは困難で通常は台形にな
ること、およびアニールによる拡散があることに
より、n+領域１３，１４はゲート電極１５の下
まで形成され、ゲート耐圧の一層の低下および寄
生容量の増大をもたらす。 One of the self-alignment methods is the Si
As is often done in MOS FETs, as shown in FIG. 2, a heat-resistant gate electrode 15 is formed, and using the gate electrode 15 as a mask, ions are implanted into the source and drain regions to cover the gate 15. It is conceivable to form n + regions 13 and 14 by performing annealing while the substrates are still attached. However, in this method, since the gate electrode 15 is not a MOS type but a shot type, the n + region 13
and 14, there is a drawback that the gate breakdown voltage is significantly lowered. In particular, it is difficult to form the gate electrode 15 with a perfectly rectangular cross section, and it is usually trapezoidal. Due to the diffusion caused by annealing, the n + regions 13 and 14 are formed to the bottom of the gate electrode 15, and the gate breakdown voltage This results in a further decrease in the capacitance and an increase in parasitic capacitance.
また特開昭54−25171には、本願明細書の第３
図に示すように、シヨツトキゲート金属３１およ
びその上のレジスト３２を選択イオン注入のマス
クとしてn+領域１３および１４を形成し（第３
図ａ）、その後ゲート金属（Al）をサイドエツチ
ングしてゲート電極１５をn+領域１３，１４か
ら離す（第３図ｂ）工程が示されている。しかし
ながら、かかる工程は、レジストを被着したまま
アニールを行うことになり、レジストの耐熱性の
非常に低いこと、およびアニール時の問題、特に
ゲート金属の耐熱性の問題が解決、言及されてい
ないことにより、実際上は実現しえない方法であ
る。すなわちGaAsへのドナー不純物のイオン注
入においては、アニールは通常800℃以上の温度
で行われるため、レジストを被着したままアニー
ルは行えないし、ゲート金属の選定にあたつて
は、かかる高温でもGaAsと反応しないものを見
出すことが極めて重要である。またレジスト上か
ら高濃度のイオン注入を行う場合には、レジスト
の変質が起こり、はく離困難という現象が起きイ
オン注入後の工程を複雑化させるという問題も生
じる。 In addition, in JP-A-54-25171, the third part of the specification of the present application is
As shown in the figure, n + regions 13 and 14 are formed using the shot gate metal 31 and the resist 32 thereon as a mask for selective ion implantation (third
Figure 3a) and then side-etching the gate metal (Al) to separate the gate electrode 15 from the n + regions 13 and 14 (Figure 3b) are shown. However, in this process, annealing is performed with the resist still attached, and the heat resistance of the resist is very low, and the problems during annealing, especially the heat resistance of the gate metal, have not been solved or mentioned. Therefore, this is a method that cannot be realized in practice. In other words, when ion-implanting donor impurities into GaAs, annealing is usually performed at a temperature of 800°C or higher, so annealing cannot be performed with the resist still attached. It is extremely important to find something that does not react. Furthermore, when high-concentration ion implantation is performed from above the resist, the resist changes in quality and becomes difficult to peel off, complicating the process after ion implantation.
本発明は、以上述べた従来技術上の問題点を解
決してゲート電極とソースおよびドレインのイオ
ン注入によるn+領域とをセルフアライメントで
形成することを可能にし、しかもゲート抵抗を大
きく低減できる構造のMESFETを容易に製造し
うる方法を提供するものである。第４図にもとづ
いて本発明の製法を記述すれば、高抵抗GaAs基
板１１上に形成されたｎ型チヤンネル層１２上に
イオン注入されるべきソースおよびドレイン領域
を開口するパターンに、Nb、Ta、MoおよびＷ
から選ばれた一種の金属あるいはこれらの合金、
ないしはこれらの金属あるいは合金中に、Ti、
Cr、ZrおよびHfから選ばれた１つないしそれ以
上の種類の金属を20at％以下の割合で含有した合
金で成る第１の金属層４１と、その上の第２の金
属層４２で成る多層マスクを形成し（第４図ａ）、
ドナー不純物のイオン４３をソースおよびドレイ
ン領域４４，４５に注入する（第４図ｂ）。次い
で必要ならばアニール時の表面保護膜４６を被着
し、アニールを行つて注入イオンを活性化し、
n+領域１３および１４を形成する（第４図ｃ）。
かかる後、表面保護膜４６を除去し、第２の金属
層より第１の金属層のエツチング速度の非常に大
きいエツチング手段でもつて第１の金属層をサイ
ドエツチングしてゲート電極１５を形成し（第４
図ｄ）、ソース電極１６およびドレイン電極１７
を形成する（第４図ｅ）工程で成る。 The present invention solves the above-mentioned problems with the prior art, makes it possible to form the gate electrode and the n + regions of the source and drain by ion implantation in self-alignment, and has a structure that can greatly reduce the gate resistance. The present invention provides a method for easily manufacturing a MESFET. Describing the manufacturing method of the present invention based on FIG. 4, Nb, Ta, and , Mo and W
A type of metal selected from or an alloy thereof,
Or in these metals or alloys, Ti,
A multilayer consisting of a first metal layer 41 made of an alloy containing one or more metals selected from Cr, Zr, and Hf in a proportion of 20 at% or less, and a second metal layer 42 thereon. forming a mask (Figure 4a);
Donor impurity ions 43 are implanted into the source and drain regions 44, 45 (FIG. 4b). Next, if necessary, a surface protection film 46 for annealing is applied, and annealing is performed to activate the implanted ions.
n + regions 13 and 14 are formed (FIG. 4c).
After that, the surface protective film 46 is removed, and the first metal layer is side-etched using an etching means that etches the first metal layer at a much higher etching rate than the second metal layer to form the gate electrode 15 ( Fourth
Figure d), source electrode 16 and drain electrode 17
(Fig. 4e).
本発明においては、第１の金属層４１は、アニ
ールに耐え得る耐熱性の金属でゲートシヨツトキ
接合をなし、第２の金属膜４２はAuおよびAgの
ような注入イオンの阻止能が大きく、かつ配線抵
抗の小さい金属が選ばれる。第２および第１の金
属層をマスクとしてイオン注入およびアニールに
よつてn+領域を形成した後、第１の金属層を少
しエツチングしてゲートシヨツトキの接合面積を
狭めるので、該シヨツトキ接合は、自動的にソー
スおよびドレインのn+領域間に位置し、改良さ
れた構造のMESFETがセルフアライメントで形
成できる。しかも第１の金属層上にオーバーハン
グとなる第２の金属層４２もゲート電極の一部を
成すから、ゲート配線抵抗を非常に小さくでき
る。ここでシヨツトキ接合を成す第１の金属層に
用いられる主たる金属群、Nb、Ta、Moおよび
Ｗは、GaAsにおいてn+層を形成できるに足るよ
うな例えば800℃程度でのアニールを行つても
GaAsと反応せず、シヨツトキ特性の損われない
条件で選ばれたものであり、Ti、Cr、Zrおよび
Hfの従なる金属群およびその含有範囲は上記条
件を満たす範囲で、GaAsとの接着性を改善する
目的で選ばれたものである。またかかる条件で選
ばれた第１の金属層は、代表的な第２の金属層で
あるAuの拡散阻止能が大きく、アニール時のAu
の拡散が少く、GaAsとの反応を防ぐ作用も有す
る。またイオン注入のマスクはストツピングパワ
ーの大きいAu等の金属層を用いるので、レジス
トを用いたときの問題すなわち厚いレジストを用
いる必要性、レジストの変質等を避けることがで
きる。また本発明においては、アニール時の表面
保護膜形成時には第２の金属層のオーバーハング
は、ないか、あるいは少いので、表面カバレツジ
の良い表面保護膜を形成できる。またアニール時
にはｎ型チヤンネル層全面は第１の金属層で覆わ
れているため、表面保護膜の問題による、チヤン
ネル層の変質の恐れを回避することができる。ま
た本発明において、第２の金属層４２をマスクに
してオーム性電極金属５１の蒸着を行えば、ソー
スおよびドレイン電極もセルフアライメントで形
成できる（第５図）。なお以上ではｎ型チヤンネ
ル層中にn+形成用のイオン注入を行う場合につ
いて述べたが、本発明はチヤンネル層形成をイオ
ン注入で行い、この注入層上に第１および第２の
金属層を形成してn+形成用のイオン注入を行う
場合にも適用できる。この場合は、ｎ型チヤンネ
ル層形成と、n+領域形成用のアニールは同時に
行うことができる。 In the present invention, the first metal layer 41 is made of a heat-resistant metal that can withstand annealing and forms a gate shot junction, and the second metal film 42 has a high blocking ability for implanted ions such as Au and Ag, and has a high blocking ability for implanted ions such as Au and Ag. A metal with low resistance is chosen. After forming an n + region by ion implantation and annealing using the second and first metal layers as masks, the first metal layer is slightly etched to narrow the gate shot junction area, so the shot junction is automatically formed. MESFETs with improved structure can be formed by self-alignment between the source and drain n + regions. Moreover, since the second metal layer 42 overhanging the first metal layer also forms a part of the gate electrode, the gate wiring resistance can be made very small. The main metal groups, Nb, Ta, Mo, and W used in the first metal layer that forms the shot-to-socket junction here, can be annealed at a temperature of about 800°C, which is sufficient to form an n + layer in GaAs.
It was selected under the conditions that it does not react with GaAs and does not impair its shot properties, and it contains Ti, Cr, Zr and
The sub-metal group of Hf and its content range satisfy the above conditions and were selected for the purpose of improving adhesiveness with GaAs. In addition, the first metal layer selected under these conditions has a large diffusion blocking ability for Au, which is a typical second metal layer, and has a high ability to inhibit the diffusion of Au, which is a typical second metal layer.
It also has the effect of preventing reaction with GaAs. Furthermore, since the ion implantation mask uses a metal layer such as Au having a large stopping power, problems when using a resist, such as the necessity of using a thick resist and deterioration of the resist, can be avoided. Further, in the present invention, since there is no or little overhang of the second metal layer when forming the surface protective film during annealing, a surface protective film with good surface coverage can be formed. Furthermore, since the entire surface of the n-type channel layer is covered with the first metal layer during annealing, it is possible to avoid the possibility of deterioration of the channel layer due to problems with the surface protective film. Further, in the present invention, if the ohmic electrode metal 51 is vapor-deposited using the second metal layer 42 as a mask, the source and drain electrodes can also be formed in self-alignment (FIG. 5). In addition, although the case where ion implantation for forming n + is performed in the n-type channel layer has been described above, in the present invention, the channel layer is formed by ion implantation, and the first and second metal layers are formed on this implanted layer. It can also be applied when performing ion implantation for n + formation. In this case, the formation of the n-type channel layer and the annealing for forming the n + region can be performed simultaneously.
次に本発明の具体例について説明する。高抵抗
GaAs基板上に5μｍの厚さに高純度バツフア層さ
らにキヤリア密度２×1017cm-3、厚さ約0.15μｍの
ｎ型層を成長させたGaAsウエハーを用にｎ層上
い0.5μｍの厚さにTiを15原子％含んだＷを被着す
る。次にTiを含有したＷ層上にリフトオフ法に
よつて0.25μｍの厚さのAu層を、イオン注入すべ
きソースおよびドレイン領域を開口したパターン
すなわちソース−ドレイン間2μｍを被覆したパ
ターンに形成する。CF4とO2ガスを用いた平行平
板型プラズマエツチングによつてＷ（Ti）を垂直
にエツチングする。ドナーイオンとしてSi+を
100KeVで１×1014cm-2、40KeVで７×1013cm-3
注入する。CVD法にて0.2μｍの厚さにSiO2の表
面保護膜を形成し、N2中800℃10分間のアニール
を行つてn+領域を形成する。次にCF4とO2ガスを
用いた円筒型のプラズマにエツチングよつて
SiO2をエツチングし、続いてＷ（Ti）を0.5μｍサ
イドエツチングする。最後にAu−Ge／NiをAu
をマスクにして蒸着し、450℃で熱処理してソー
スおよびドレイン電極を形成する。以上によつて
ゲート長約1μｍ、ゲートソース間約0.5μｍ、ソー
ス電極（ドレイン電極）の接触抵抗0.08Ωcm、ゲ
ート配線抵抗35Ω／mmと、ソース抵抗およびゲー
ト抵抗が大きく低減されたMESFETが形成され
る。 Next, specific examples of the present invention will be described. high resistance
A high-purity buffer layer with a thickness of 5 μm and an n-type layer with a carrier density of 2×10 17 cm -3 and a thickness of approximately 0.15 μm were grown on the GaAs wafer. W containing 15 atomic % of Ti is deposited on the surface. Next, on the Ti-containing W layer, a 0.25 μm thick Au layer is formed by a lift-off method into a pattern that opens the source and drain regions to be ion-implanted, that is, a pattern that covers the source-drain distance of 2 μm. . W (Ti) is vertically etched by parallel plate plasma etching using CF 4 and O 2 gas. Si + as donor ion
1×10 14 cm -2 at 100KeV, 7×10 13 cm -3 at 40KeV
inject. A surface protective film of SiO 2 is formed to a thickness of 0.2 μm by CVD method, and annealing is performed in N 2 at 800° C. for 10 minutes to form an n + region. Next, etching is performed using a cylindrical plasma using CF 4 and O 2 gas.
SiO 2 is etched, and then W (Ti) is side etched by 0.5 μm. Finally, add Au-Ge/Ni to Au
The source and drain electrodes are formed by vapor deposition using a mask and heat treatment at 450°C. As a result, a MESFET with greatly reduced source and gate resistances was formed, with a gate length of approximately 1 μm, gate-source distance of approximately 0.5 μm, source electrode (drain electrode) contact resistance of 0.08 Ωcm, and gate wiring resistance of 35 Ω/mm. Ru.
第１図は、論理集積回路等に応用できる改良さ
れた構造のGaAs MESFETの構造を示す図であ
る。第２図および第３図ａ，ｂは、セルフアライ
メントでゲートに対してn+領域を形成する従来
考えられた方法を説明する図である。第４図ａ〜
ｅは本発明の製造方法を説明する図である。第５
図は、本発明を用いて、さらにソースおよびドレ
イン電極をセルフアライメントで形成する方法を
説明する図である。ここで、１１は高抵抗基板、
１２はｎ型チヤンネル層、１３および１４はイオ
ン注入およびアニールによつて形成されたソース
およびドレインのn+領域、１５はゲート電極、
１６はソース電極、１７はドレイン電極である。
また３１は金属膜、３２はレジストである。４１
は高耐熱性の第１の金属膜、４２は第２の金属
膜、４３は注入されるイオン、４４および４５は
ソースおよびドレインのイオン注入された領域
（活性化前）、４６は表面保護膜、５１はオーム性
電極金属を示す。
FIG. 1 is a diagram showing the structure of an improved GaAs MESFET that can be applied to logic integrated circuits and the like. FIG. 2 and FIGS. 3a and 3b are diagrams illustrating a conventional method of forming an n + region with respect to a gate by self-alignment. Figure 4 a~
FIG. 3e is a diagram illustrating the manufacturing method of the present invention. Fifth
The figure is a diagram illustrating a method of forming source and drain electrodes in self-alignment using the present invention. Here, 11 is a high resistance board,
12 is an n-type channel layer; 13 and 14 are source and drain n + regions formed by ion implantation and annealing; 15 is a gate electrode;
16 is a source electrode, and 17 is a drain electrode.
Further, 31 is a metal film, and 32 is a resist. 41
is a highly heat-resistant first metal film, 42 is a second metal film, 43 is an implanted ion, 44 and 45 are source and drain ion-implanted regions (before activation), and 46 is a surface protective film. , 51 represents an ohmic electrode metal.
Claims (1)
ネル層上に、イオン注入されるべきソースおよび
ドレイン領域を開口するパターンに、Nb、Ta、
MoおよびＷから選ばれた一種の金属あるいはこ
れらの合金、ないしはこれらの金属あるいは合金
中にTi、Cr、ZrおよびHfから選ばれた１つない
しそれ以上の種類の金属を20at％以下の割合で含
有した合金で成る第１の金属層と、その上に被着
された第２の金属層で成る多層マスクを形成し、
ドナー不純物のイオンを該ソースおよびドレイン
領域に注入し、次いで必要ならばアニール時の表
面保護膜を被着し、アニールを行つて注入イオン
を活性化、n+領域を形成し、かかる後表面保護
膜を除去し、第２の金属層より第１の金属層のエ
ツチング速度の非常に大きいエツチング手段でも
つて、第１の金属層をサイドエツチングしてゲー
ト電極と成し、さらに前記n+領域上にソース電
極およびドレイン電極を形成して成るシヨツトキ
障壁ゲート電界効果トランジスタの製造方法。1 Nb, Ta,
A metal selected from Mo and W, or an alloy thereof, or one or more metals selected from Ti, Cr, Zr, and Hf in a proportion of 20at% or less in these metals or alloys. forming a multilayer mask comprising a first metal layer made of the alloy containing the metal and a second metal layer deposited thereon;
Donor impurity ions are implanted into the source and drain regions, and then, if necessary, a surface protection film is deposited during annealing, annealing is performed to activate the implanted ions, forming an n + region, and the surface protection is performed after such annealing. The film is removed, and the first metal layer is side-etched to form a gate electrode using an etching method that etches the first metal layer at a much higher etching rate than the second metal layer, and then etches the first metal layer to form a gate electrode. A method for manufacturing a shot barrier gate field effect transistor comprising forming a source electrode and a drain electrode in a field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3698681A JPS57152168A (en) | 1981-03-13 | 1981-03-13 | Manufacture of schottky barrier gate field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3698681A JPS57152168A (en) | 1981-03-13 | 1981-03-13 | Manufacture of schottky barrier gate field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57152168A JPS57152168A (en) | 1982-09-20 |
| JPH0212015B2 true JPH0212015B2 (en) | 1990-03-16 |
Family
ID=12485066
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3698681A Granted JPS57152168A (en) | 1981-03-13 | 1981-03-13 | Manufacture of schottky barrier gate field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57152168A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59229876A (en) * | 1983-06-13 | 1984-12-24 | Toshiba Corp | Manufacture of schottky gate type field effect transistor |
| JPS6081872A (en) * | 1983-10-11 | 1985-05-09 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
| JPS60115268A (en) * | 1983-11-28 | 1985-06-21 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS6143481A (en) * | 1984-08-08 | 1986-03-03 | Oki Electric Ind Co Ltd | Manufacture of schottky gate field effect transistor |
| JPH0812868B2 (en) * | 1984-08-27 | 1996-02-07 | 沖電気工業株式会社 | Method for manufacturing compound semiconductor device |
| EP0220605B1 (en) * | 1985-10-21 | 1990-12-12 | Itt Industries, Inc. | Method of making self-aligned gaas digital integrated circuits |
| JP2702338B2 (en) * | 1991-10-14 | 1998-01-21 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
-
1981
- 1981-03-13 JP JP3698681A patent/JPS57152168A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57152168A (en) | 1982-09-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR920002090B1 (en) | Method of manufacturing field effect transistor | |
| US4566021A (en) | Semiconductor device | |
| JPH0235462B2 (en) | ||
| JPH0212015B2 (en) | ||
| JPS58212177A (en) | Insulated gate type transistor and manufacture thereof | |
| JPH0361346B2 (en) | ||
| JPS6257255A (en) | Manufacture of compound semiconductor device | |
| JPH0235463B2 (en) | ||
| JPH0126172B2 (en) | ||
| JPS6160591B2 (en) | ||
| JP2777153B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPS6273673A (en) | Manufacture of field-effect transistor | |
| JPH0622247B2 (en) | Field effect semiconductor device | |
| JPS58124276A (en) | Schottky gate field effect transistor and manufacture thereof | |
| JPH0439772B2 (en) | ||
| JPS62291070A (en) | Manufacture of semiconductor device | |
| JP2889240B2 (en) | Compound semiconductor device and method of manufacturing the same | |
| JPS6038883A (en) | Manufacture of schottky gate type field effect transistor | |
| JPH0352238A (en) | Manufacture of compound semiconductor device | |
| JPS6196771A (en) | Manufacture of semiconductor device | |
| JPS6050966A (en) | Manufacture of field effect transistor | |
| JPH01119071A (en) | Compound semiconductor field-effect transistor | |
| JPS63246870A (en) | Compound semiconductor device and manufacture thereof | |
| JPS6276566A (en) | Manufacture of field-effect transistor | |
| JPH0245332B2 (en) |