JPH02114933U - - Google Patents
Info
- Publication number
- JPH02114933U JPH02114933U JP1989022309U JP2230989U JPH02114933U JP H02114933 U JPH02114933 U JP H02114933U JP 1989022309 U JP1989022309 U JP 1989022309U JP 2230989 U JP2230989 U JP 2230989U JP H02114933 U JPH02114933 U JP H02114933U
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- board
- wiring
- bonded
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Credit Cards Or The Like (AREA)
- Wire Bonding (AREA)
Description
第1図は本考案による配線基板を用いた情報カ
ードの一実施例を示す側面図、第2図は従来の情
報カード読取システムの構成を示す略線図、第3
図はその情報カードの電気的構成を示す略線的ブ
ロツク図、第4図は従来の配線基板を示す側面図
である。 4,30……情報カード、4A,32……基板
、4E……配線パターン、15……チツプ部品、
16……電極、17……バンプ、21,31……
配線基板。
ードの一実施例を示す側面図、第2図は従来の情
報カード読取システムの構成を示す略線図、第3
図はその情報カードの電気的構成を示す略線的ブ
ロツク図、第4図は従来の配線基板を示す側面図
である。 4,30……情報カード、4A,32……基板
、4E……配線パターン、15……チツプ部品、
16……電極、17……バンプ、21,31……
配線基板。
Claims (1)
- 【実用新案登録請求の範囲】 チツプ部品の表面に形成した複数の電極をそれ
ぞれ対応する接合部材によつて基板上に設けられ
た対応する配線パターンに接合するようになされ
た配線基板において、 上記基板を柔軟性のある材料によつて形成した ことを特徴とする配線基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989022309U JPH02114933U (ja) | 1989-02-28 | 1989-02-28 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989022309U JPH02114933U (ja) | 1989-02-28 | 1989-02-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02114933U true JPH02114933U (ja) | 1990-09-14 |
Family
ID=31240305
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1989022309U Pending JPH02114933U (ja) | 1989-02-28 | 1989-02-28 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02114933U (ja) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5873126A (ja) * | 1981-10-27 | 1983-05-02 | Seiko Keiyo Kogyo Kk | 半導体装置の実装方法 |
JPS60262430A (ja) * | 1984-06-08 | 1985-12-25 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
-
1989
- 1989-02-28 JP JP1989022309U patent/JPH02114933U/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5873126A (ja) * | 1981-10-27 | 1983-05-02 | Seiko Keiyo Kogyo Kk | 半導体装置の実装方法 |
JPS60262430A (ja) * | 1984-06-08 | 1985-12-25 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |