JPH02105612A - Schmitt circuit - Google Patents
Schmitt circuitInfo
- Publication number
- JPH02105612A JPH02105612A JP25870188A JP25870188A JPH02105612A JP H02105612 A JPH02105612 A JP H02105612A JP 25870188 A JP25870188 A JP 25870188A JP 25870188 A JP25870188 A JP 25870188A JP H02105612 A JPH02105612 A JP H02105612A
- Authority
- JP
- Japan
- Prior art keywords
- mosfet
- circuit
- voltage
- schmitt
- threshold voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 3
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Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はシュミット回路に関し、特にＣＭ０８ＦＥＴで
構成されたシュミット回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a Schmitt circuit, and more particularly to a Schmitt circuit constructed of CM08FETs.
従来、０ＭＯＳＦＥＴで構成されたシーミツト回路は、
第３図に示すように、ｐチャネルＭＯＳＦＥＴ（以下ｐ
−ＭＯＳＦＥＴと記す）１５．１６とｎチャネルＭＯＳ
ＦＥＴ（以下ｎ−ＭＯＳＦＥＴ）１７．１８によシ構成
された反転回路と、スイッチ素子１９．２０を制御する
インバータ２１とによシ構成されていた。Conventionally, a seamit circuit composed of 0 MOSFETs is
As shown in Fig. 3, p-channel MOSFET (hereinafter p
- MOSFET) 15.16 and n-channel MOS
It was composed of an inverter circuit composed of FETs (hereinafter referred to as n-MOSFETs) 17 and 18, and an inverter 21 that controlled switch elements 19 and 20.
この回路は、出力端子２２に出力される出力信号Ｖｏｕ
ｔが高レベルから低レベルに変化するしきい値電圧Ｖｔ
ｔ、と、低レベルから高レベルに変化するしきい値電圧
ｖｔｔｒの２つのしきい値電圧を有し、しきい値電圧Ｖ
ｔｔｒとしきい値電圧ＶＴＬの差電圧ＶＴυ−■〒Ｌが
この回路のシュミット幅となっている。そこで、このシ
ュミット幅を作るために、しきい値電圧Ｖｔｔはｎ−Ｍ
ＯＳＦＥＴＩ７のソース電位をｎ−ＭＯＳＦＥＴ２０の
スイッチ動作により変化させることによ３、ｐ−ＭＯＳ
ＦＥＴ１６のドレイン電流とｎ −ＭＯ８Ｆ Ｅ Ｔ
１７のドレイン電流が等しくなる電圧を一般的なＣＭ０
８ＦＥＴ反転回路のしきい値電圧■ＤＤ／２より下げて
いる。This circuit has an output signal Vou output to the output terminal 22.
Threshold voltage Vt at which t changes from high level to low level
t, and a threshold voltage vttr that changes from a low level to a high level, and the threshold voltage V
The difference voltage VTυ-■〒L between ttr and threshold voltage VTL is the Schmitt width of this circuit. Therefore, in order to create this Schmitt width, the threshold voltage Vtt is n-M
By changing the source potential of OSFETI7 by switching operation of n-MOSFET20, p-MOS
Drain current of FET16 and n-MO8FET
The voltage at which the drain currents of 17 and 17 are equal is the general CM0
The threshold voltage of the 8FET inversion circuit is lower than ■DD/2.
同様に、しきい値電圧ＶＴＵはｐ−ＭＯＳＦＥＴ１６の
ソース電位をｐ−ＭＯＳＦＥＴ１９のスイッチ動作によ
シ変化させることによｊ）、ｐ−ＭＯＳＦＥＴ１６のド
レイン電流とｎ−ＭＯＳＦＥＴ１７のドレイン電流が等
しくなる電圧を■ＤＤ／２よシ上げている。Similarly, the threshold voltage VTU is determined by changing the source potential of the p-MOSFET 16 by the switching operation of the p-MOSFET 19j), at which the drain current of the p-MOSFET 16 and the drain current of the n-MOSFET 17 become equal. is higher than ■DD/2.
これによシしきい値電圧７丁Ｕとしきい値電圧ＶＴＬに
差電圧が生じこれがシュミット幅となシ、シュミット回
路として動作する。As a result, a voltage difference is generated between the threshold voltage 7U and the threshold voltage VTL, which has a Schmitt width and operates as a Schmitt circuit.
上述した従来のシュミット回路は、シュミット幅を作る
ため、ｐ−ＭＯＳＦＥＴ１６及びｎ−ＭＯＳＦＥＴ１７
のソース電位を変化させているので、電源ＶＤＤが低下
してくると、入力端子１に入力される入力信号Ｖｉｎと
電源■ＤＤ ｖ ■８Ｂの差電圧が低下して、ｐ−ＭＯ
ＳＦＥＴ１６とｎ−ＭＯＳＦＥＴＩ７０ンース電位が直
接電源ＶＤＤ ｔ ｖｓｓに接続されてない分、ｐ−Ｍ
ＯＳＦＥＴ１６とｎ−ＭＯ８ＦＢＴ１７のゲート・ソー
ス間電圧の余裕がそれぞれなくなシ、電源電圧の低下に
よシ早く動作しなくなる（ＭＯＳＦＥＴのしきい値電圧
７丁の２倍の電圧まで動作しない）。The conventional Schmitt circuit described above has p-MOSFET 16 and n-MOSFET 17 to create the Schmitt width.
Since the source potential of the p-MO is changed, when the power supply VDD decreases, the differential voltage between the input signal Vin input to the input terminal 1 and the power supply ■DD v ■8B decreases, and the p-MO
Since the ground potential of SFET16 and n-MOSFETI70 is not directly connected to the power supply VDD t vss, p-M
The OSFET 16 and the n-MO8FBT 17 each have no margin for gate-source voltage, and they quickly stop operating due to a drop in the power supply voltage (they do not operate up to a voltage twice as high as the threshold voltage of the MOSFET).
又、低電圧動作をある程度保証しようとした場合、ｐ−
ＭＯＳＦＥＴ１６とｎ−ＭＯＳＦＥＴ１７のソースと電
源■ＤＤ、■ｓ８の電圧降下を下げるため、低電圧での
シュミット幅がとれないという欠点があった。Also, when trying to guarantee low voltage operation to some extent, p-
In order to lower the voltage drop between the sources of MOSFET 16 and n-MOSFET 17 and the power supplies DD and s8, there was a drawback that the Schmitt width could not be maintained at low voltages.
本発明のシュミット回路は、ｐチャネルＭＯＳＦＥＴと
ｎチャネルＭＯＳＦＥＴとで構成される第１の反転回路
と、ｐチャネルＭＯＳＦＥＴとｎチャネルＭＯＳＦＥＴ
とで構成されかつ入力端子が前記第１の反転回路に接続
される第２の反転回路と、前記第１の反転回路の出力端
子と前記第２の反転回路の出力端子との間に接続される
スイッチ素子と、入力端子が前記第１の反転回路の出力
端子に接続され出力信号の一部を前記スイッチ素子に帰
還して前記スイッチ素子の開閉を制御する少くとも一つ
のインバータとを含んで構成される。The Schmitt circuit of the present invention includes a first inverting circuit composed of a p-channel MOSFET and an n-channel MOSFET, and a first inverting circuit composed of a p-channel MOSFET and an n-channel MOSFET.
a second inverting circuit comprising: a second inverting circuit having an input terminal connected to the first inverting circuit; and a second inverting circuit connected between an output terminal of the first inverting circuit and an output terminal of the second inverting circuit. at least one inverter having an input terminal connected to an output terminal of the first inverting circuit and feeding back a part of an output signal to the switching element to control opening/closing of the switching element. configured.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例の回路図である。FIG. 1 is a circuit diagram of a first embodiment of the present invention.
この実施例のシュミット回路は、ｐ−ＭＯＳＦＥＴ２と
ｎ −ＭＯＳ Ｆ Ｅ Ｔ ３とで構成される第１の反
転回路と、ｐ−ＭＯＳＦＥＴ４とｎ−ＭＯＳＦＥＴ７と
で構成されかつ入力端子が第１の反転回路の入力端子Ｉ
Ｋ接続される第２の反転回路と、第１の反転回路の出力
端子と第２の反転回路の出力端子との間に接続されるス
イッチ素子５．６と、入力端子が第１の反転回路の出力
端子に接続され出力信号Ｖｏｕｔの一部をスイッチ素子
５，６のゲートに帰還してスイッチ素子５，６の開閉を
制御するインバータ８とを含んで構成される。The Schmitt circuit of this embodiment is composed of a first inverting circuit consisting of p-MOSFET2 and n-MOSFET3, and p-MOSFET4 and n-MOSFET7, and the input terminal is connected to the first inverting circuit. Input terminal I of the circuit
a second inverting circuit that is K-connected; a switch element 5.6 connected between the output terminal of the first inverting circuit and the output terminal of the second inverting circuit; and a switch element 5.6 whose input terminal is connected to the first inverting circuit. The inverter 8 is connected to the output terminal of the inverter 8 and returns a part of the output signal Vout to the gates of the switch elements 5 and 6 to control opening and closing of the switch elements 5 and 6.
次に、この実施例の動作について説明する。Next, the operation of this embodiment will be explained.
この実施例のシュミット回路は、出力信号Ｖｏｕｔが高
レベルから低レベルに変化するしきい値電圧■τＬと、
低レベルから高レベルに変化するしきい値電圧ＶＴＵの
２つのしきい値電圧を有しておシ、しきい値電圧ｖ、Ｌ
’としきい値電圧ｖｔｔｒＯ差電圧ｖｔｕ ＋ ｖ’ｒ
ｔ、がこの回路のシュミット幅となっている。そこで、
このシュミット幅を作るために、しきい値電圧ＶＴＬは
スイッチとして動作するｎ−ＭＯＳＦＥＴｅＫよりて、
ｎ−ＭＯＳＦＥＴ３に並列にｎ−ＭＯＳＦＥＴ７を接続
することによシ、ｐ−ＭＯＳＦＥＴ２のドレイン電流と
ｎ−ＭＯＳＦＥＴ３．７のドレイン電流が等しく々る電
圧をＶＤＤ ／ ２よシ下げている。The Schmitt circuit of this embodiment has a threshold voltage ■τL at which the output signal Vout changes from a high level to a low level,
It has two threshold voltages, VTU, which changes from a low level to a high level, and the threshold voltages v and L.
' and threshold voltage vttrO difference voltage vtu + v'r
t is the Schmidt width of this circuit. Therefore,
In order to create this Schmitt width, the threshold voltage VTL is set by the n-MOSFETeK that operates as a switch.
By connecting n-MOSFET 7 in parallel to n-MOSFET 3, the voltage at which the drain current of p-MOSFET 2 and the drain current of n-MOSFET 3.7 are equal is lowered to VDD/2.
同様に、しきい値電圧■Ｔυ′はスイッチとして動作す
るｐ−ＭＯ８ＦＢＴ５によって、ｐ−ＭＯＳＦＥＴ２に
並列にｐ−ＭＯＳＦＥＴ４を接続することによシ、ｐ−
ＭＯＳＦＥＴ２．４のドレイン電流とｎ−ＭＯＳＦＥＴ
３のドレイン電流が等しくなる電圧をＶＤＤ ／ ２よ
シ上げている。これによシ、シきい値電圧ｖＴｔｙとし
きい値電圧Ｖ’ｒＬに差電圧が生じ、これがシュミット
幅となシ、シュミット回路として動作する。Similarly, the threshold voltage ■Tυ' can be adjusted by connecting p-MOSFET4 in parallel to p-MOSFET2 by p-MO8FBT5 which operates as a switch.
Drain current of MOSFET2.4 and n-MOSFET
The voltage at which the drain currents of 3 and 3 are equal is raised to VDD/2. As a result, a voltage difference is generated between the threshold voltage vTty and the threshold voltage V'rL, which has a Schmitt width and operates as a Schmitt circuit.
又、しきい値電圧■ＴＬ、■テＵは次式で示される。Further, the threshold voltages TL and TE are expressed by the following equations.
ただし、ＶＴＰ：ｐ−ＭＯＳＦＥＴ しきい値電圧ＶＴ
Ｎ ： ｎ ＭＯＳＦＥＴ シきい値電圧辱 ：ｐ−
ＭＯＳＦＥＴ導伝係数
ＫＮ ：ｎ Ｍ０８ＦＥＴ導伝係数Ｗ、、Ｗ８．Ｗ
４．Ｗ、：ＭＯＳＦＥＴのチャネル幅Ｌ２．Ｌ３．Ｌ４
．Ｌ、：ＭＯＳＦＥＴのチャネル長このように本発明の
シュミット回路は、シュミット幅を作るためにｐ−ＭＯ
ＳＦＥＴ２とｐ−ＭＯＳＦＥＴ４及びｎ−ＭＯＳＦＥＴ
３とｎ−ＭＯＳＦＥＴ７をシュミット回路の出力信号Ｖ
ｏｕｔで制御されるｐ−ＭＯＳＦＥＴｓとｎ−ＭＯＳＦ
ＥＴ６にヨっテ、ツレ（ＴＬ並列に接続されることによ
シ、シきい値電圧ｖＴＬとしきい値電圧ＶＴＵの電圧に
差を生じさせているので、電源ＶＤＤの電圧が低下して
もｐ−ＭＯＳＦＥＴ２．４とｎ−ＭＯＳＦＥＴ３．７の
ソース電位が直接電源■ＤＤ、■ｓ８に接続されておシ
、ＭＯＳＦＥＴｏしきい値電圧Ｖ丁の２倍の電源電圧Ｖ
ＤＤ’ｔでは動作する０又−シュミット幅は（１） 、
（２）式よｊ５ｐ−ＭＯＳＦＥＴとｎ−ＭＯＳＦＥＴ
のサイズ比で決まるので、電圧が低下した時に、動作範
囲においてシュミット幅がなくなることはない。However, VTP: p-MOSFET threshold voltage VT
N: n MOSFET threshold voltage: p-
MOSFET conduction coefficient KN:n M08FET conduction coefficient W,, W8. W
4. W,: MOSFET channel width L2. L3. L4
．． L,: MOSFET channel length In this way, the Schmitt circuit of the present invention uses p-MOSFET to create the Schmitt width.
SFET2, p-MOSFET4 and n-MOSFET
3 and n-MOSFET7 to output signal V of Schmitt circuit.
p-MOSFETs and n-MOSFs controlled by out
By connecting ET6 in parallel, a difference is created between the threshold voltage vTL and the threshold voltage VTU, so even if the voltage of the power supply VDD drops, -The source potentials of MOSFET2.4 and n-MOSFET3.7 are directly connected to the power supplies ■DD and ■s8, and the power supply voltage V is twice the threshold voltage V of the MOSFETTo.
The operating zero-Schmidt width in DD't is (1),
(2) According to the formula, j5p-MOSFET and n-MOSFET
Since it is determined by the size ratio of , the Schmidt width does not disappear in the operating range when the voltage decreases.
第２図は本発明の第２の実施例を示す回路図である。FIG. 2 is a circuit diagram showing a second embodiment of the present invention.
構成としては第１の実施例のシュミット回路と基本的に
同じであるが、シーミツト回路の出力で制御され、スイ
ッチとして動作するＭＯＳＦＥＴがｐ−ＭＯＳＦＥＴ５
、１０とｎ−ＭＯＳＦＥＴ６ 、１１の並列接続とな
っておシ、よシスイッチとしての動作が安定となってい
る。シュミット回路としての動作及び効果は第１の実施
例と同様である。The configuration is basically the same as the Schmitt circuit of the first embodiment, but the MOSFET that is controlled by the output of the Schmitt circuit and operates as a switch is p-MOSFET5.
, 10 and n-MOSFETs 6 and 11 are connected in parallel to ensure stable operation as a switch. The operation and effect as a Schmitt circuit are the same as in the first embodiment.
以上説明したように、本発明は、シュミット回路の出力
で制御されスイッチとして動作するＭＯＳＦＥＴによっ
て、ＣＭＯ８反転回路のｐ−ＭＯｆ９ＦＥＴとｎ−ＭＯ
ＳＦＥＴのサイズを変えることによって、シュミット幅
を生じさせて一番おシ、ＣＭＯ８反転回路のｐ−ＭＯＳ
ＦＥＴとｎ−ＭＯＳＦＥＴのソース電位が直接電源ＶＤ
Ｄ ＊ ７８ｇに接続しているので、ＭＯＳＦＥＴのし
きい値電圧Ｖ丁の２倍の低電圧まで安定して動作するシ
ュミット回路を得ることができるという効果を有する。As explained above, in the present invention, the p-MOf9FET and n-MOFET of the CMO8 inverting circuit are controlled by the output of the Schmitt circuit and operate as a switch.
By changing the size of the SFET, the Schmitt width can be created and the p-MOS of the CMO8 inverting circuit can be
The source potential of FET and n-MOSFET is directly connected to the power supply VD.
Since it is connected to D*78g, it is possible to obtain a Schmitt circuit that operates stably up to a voltage as low as twice the threshold voltage of the MOSFET.
１・・・入力端子、２，４．５・・・ｐ−ＭＯＳＦＥＴ
、３゜６．７・−ｎ−ＭＯＳＦＥＴ、８−インバータ、
９・・・出力端子、１０ ・−ｎ −ＭＯＳ Ｆ Ｅ
Ｔ、１１，１５，１６゜１９−ｐ−ＭＯＳＦＥＴ、１７
，１８．２０・・・ｎ−ＭＯＳＦＥＴ、■ＤＤ ｒ ■
８Ｂ・・・電源。1...Input terminal, 2,4.5...p-MOSFET
, 3゜6.7・-n-MOSFET, 8-inverter,
9...Output terminal, 10 ・-n-MOS F E
T, 11, 15, 16° 19-p-MOSFET, 17
, 18.20...n-MOSFET, ■DD r ■
8B...Power supply.
代理人 弁理士 内 原 晋Agent: Patent Attorney Susumu Uchihara
第１図は本発明の第１の実施例を示す回路図、第２図は
本発明の第２の実施例を示す回路図、第３図は従来のシ
ュミット回路の一例を示す回路図である。
あ
［
困
あｊ
）３因Fig. 1 is a circuit diagram showing a first embodiment of the present invention, Fig. 2 is a circuit diagram showing a second embodiment of the invention, and Fig. 3 is a circuit diagram showing an example of a conventional Schmitt circuit. . A [ trouble j ] 3 reasons
Claims (1)
構成される第１の反転回路と、ｐチャネルＭＯＳＦＥＴ
とｎチャネルＭＯＳＦＥＴとで構成されかつ入力端子が
前記第１の反転回路に接続される第２の反転回路と、前
記第１の反転回路の出力端子と前記第２の反転回路の出
力端子との間に接続されるスイッチ素子と、入力端子が
前記第１の反転回路の出力端子に接続され出力信号の一
部を前記スイッチ素子に帰還して前記スイッチ素子の開
閉を制御する少くとも一つのインバータとを含むことを
特徴とするシュミット回路。A first inverting circuit composed of a p-channel MOSFET and an n-channel MOSFET, and a p-channel MOSFET
and an n-channel MOSFET, the input terminal of which is connected to the first inverting circuit, and the output terminal of the first inverting circuit and the output terminal of the second inverting circuit. and at least one inverter whose input terminal is connected to the output terminal of the first inverting circuit and which feeds back a part of the output signal to the switch element to control opening and closing of the switch element. A Schmitt circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25870188A JPH02105612A (en) | 1988-10-13 | 1988-10-13 | Schmitt circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25870188A JPH02105612A (en) | 1988-10-13 | 1988-10-13 | Schmitt circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02105612A true JPH02105612A (en) | 1990-04-18 |
Family
ID=17323899
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25870188A Pending JPH02105612A (en) | 1988-10-13 | 1988-10-13 | Schmitt circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02105612A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05272730A (en) * | 1992-03-27 | 1993-10-19 | Kubota Corp | Incinerator |
| US5767728A (en) * | 1996-09-05 | 1998-06-16 | International Business Machines Corporation | Noise tolerant CMOS inverter circuit having a resistive bias |
-
1988
- 1988-10-13 JP JP25870188A patent/JPH02105612A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05272730A (en) * | 1992-03-27 | 1993-10-19 | Kubota Corp | Incinerator |
| US5767728A (en) * | 1996-09-05 | 1998-06-16 | International Business Machines Corporation | Noise tolerant CMOS inverter circuit having a resistive bias |
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