JPS60180154A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60180154A
JPS60180154A JP59035837A JP3583784A JPS60180154A JP S60180154 A JPS60180154 A JP S60180154A JP 59035837 A JP59035837 A JP 59035837A JP 3583784 A JP3583784 A JP 3583784A JP S60180154 A JPS60180154 A JP S60180154A
Authority
JP
Japan
Prior art keywords
lead frame
package
sections
lead
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59035837A
Other languages
Japanese (ja)
Inventor
Shoji Takishima
滝島　昭二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Faurecia Clarion Electronics Co Ltd
Original Assignee
Clarion Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Clarion Co Ltd filed Critical Clarion Co Ltd
Priority to JP59035837A priority Critical patent/JPS60180154A/en
Publication of JPS60180154A publication Critical patent/JPS60180154A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49534—Multi-layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To realize a package having high density by forming a lead frame in multilayer structure, in which a plurality of conductive layers are insulated mutually, and wire-bonding each conductive layer and different electrodes on a semiconductor element. CONSTITUTION:A lead frame is formed in multilayer structure in which sections among first conductor layers 15 and second conductor layers 16 are insulated electrically by insulating layers 17. Sections among the end sections 15A of the first conductive layers 15 in several external lead 11 and the end sections 16A of the second conductive layers 16 and different electrodes 18 on an IC chip 14 are bonded by wires 19, the electrodes 18 on the IC chip 14 are lead out electrically to the outside, a desired section is molded by a resin, and sections among external leads are isolated electrically, thus completing a semiconductor device. Accordingly, the same result as two external leads are wire-bonded is obtained in one external lead, and the mounting density of a package can be doubled.

Description

【発明の詳細な説明】 本発明は、パッケージ面積を増大させることな（実装密
度を向上させるためなされた半導体装置に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device that is designed to improve packaging density without increasing package area.

半導体集積回路（ＩＣ）の高集積化に伴い、このＩＣチ
ップを実装するためのパッケージに対してもそれに沿う
ように高密度化の要求がよゼられている。第１図は従来
のパッケージの一例としてＤＩＦ（デユアルーインライ
ン−パッケージ）構造を示すもので、多数の外部リード
ｌを備えたリードフレーム２上に固着されたＩＣテップ
３は対応する電極と外部リード間がワイヤボンディング
された後、樹脂４によってモールドされて実装される。As semiconductor integrated circuits (ICs) become more highly integrated, there is a growing demand for higher density packages for mounting these IC chips. FIG. 1 shows a DIF (dual in-line package) structure as an example of a conventional package, in which an IC chip 3 fixed on a lead frame 2 with a large number of external leads 1 is connected to corresponding electrodes and external leads. After wire bonding is performed between the parts, the parts are molded with resin 4 and mounted.

この場合ＩＣチップの高集積化に応じてパッケージの高
密度化を計るためには、パッケージの面積あるいは外部
リードに着目した改良が考えられる。この考えに沿って
上記ＤＩＰＹ更に小型化しＴ、：　Ｓ　ＯＰ　（スモー
ル−アウトラインーパッケージ）構造や、外部リードを
パッケージの四辺に配置したＱＦＰ　（クワッド−フラ
ット−パッケージ）構造等が現在の為密度パッケージの
代表として知られている。In this case, in order to increase the density of the package in accordance with the increasing integration of IC chips, it is possible to improve the area of the package or the external leads. In line with this idea, the above-mentioned DIPY has been further miniaturized, and the current density packages include the SOP (Small Outline Package) structure and the QFP (Quad Flat Package) structure in which external leads are placed on the four sides of the package. known as the representative of

技術的には上記ポイントに従って外部リード間の寸法を
狭（（向えば０．８〜１．２７−間隔）したり、パッケ
ージ外形７小さくかつ薄くすることが行われている。Technically, according to the above-mentioned points, the dimensions between the external leads are narrowed (to a spacing of 0.8 to 1.27), and the package outer size 7 is made smaller and thinner.

しかしながらＬＳＩがさらに発展した超ＬＳＩ（ＶＬＳ
Ｉ）のような超高集積化チップが出現するようになると
、このチップは対応した１００本以上もの外部リードを
必要とするために、上述のような従来の思想に従ってパ
ッケージの高密度化を計るには自ずから限界がある。However, VLSI (VLSI) is a further development of LSI.
When ultra-highly integrated chips such as I) appear, these chips require more than 100 corresponding external leads, so the packaging density has been increased according to the conventional philosophy described above. has its own limits.

すなわち従来思想では、ＩＣチップ上の電極に対応した
外部リードに対しては必ず一つの電気信号系統しか設定
することができないため、例えばＩＣチップ上に１００
個の電極が存在している場合には当然１００本の外部リ
ードを配にセざるを得ないので、その密度は幾何学的加
工精度によって決定されるある限られた範囲内に抑えら
れ、１００個以上もの電極を備えたＩＣチップに適する
ような望ましい密度のものン得ることは不可能である。In other words, in the conventional thinking, only one electrical signal system can be set for the external lead corresponding to the electrode on the IC chip.
Naturally, if there are 100 external leads, it is necessary to arrange 100 external leads. It is not possible to obtain the desired density suitable for IC chips with more than one electrode.

本発明は以上の観点からなされたもので、リードフレー
ムの構造を改良することにより超高集積化チップに適す
るような高密度パッケージの出現を可能ならしめること
を目的とするものでその特徴とするところは、リードフ
レーム上に固着された半導体素子の電極と周囲のリード
フレーム間欠ワイヤボンディングした半導体装置におい
て、上記リードフレームン複数の導電層が互いに絶縁さ
れた多層構造となし、６導を層と上記半導体素子上の異
なった電極間をワイヤボンディングした半導体装＆を特
徴とするものである。The present invention has been made in view of the above, and it is an object of the present invention to enable the emergence of a high-density package suitable for ultra-highly integrated chips by improving the structure of a lead frame. However, in a semiconductor device in which electrodes of a semiconductor element fixed on a lead frame and a surrounding lead frame are intermittent wire-bonded, the lead frame has a multilayer structure in which a plurality of conductive layers are insulated from each other, and six conductive layers are formed. The semiconductor device is characterized by wire bonding between different electrodes on the semiconductor element.

以下図面ン参照して本発明実施例を説明する。Embodiments of the present invention will be described below with reference to the drawings.

第２図および第３図は共に本発明実施し０による半導体
装置を示す上面図および断面図で、１２は多数の外部リ
ード１１　ン偏えたリードフレームでその中央部のサポ
ータ部】３にはＩＣチップ１４が固着される。2 and 3 are both a top view and a sectional view showing a semiconductor device according to embodiment 0 of the present invention, in which 12 is a lead frame with a large number of external leads 11; Chip 14 is fixed.

上記リードフレーム１２は第１の導電層１５と第２の導
電１−１６とが間を絶縁１ｍ　１７　Ｋよって電気的に
絶縁された多層構造となっており、第１および第２導電
層１５．１６は共に少なくともその端部１５Ａ、１６Ａ
は露出きれるように形成きれる。The lead frame 12 has a multilayer structure in which a first conductive layer 15 and a second conductive layer 1-16 are electrically insulated by an insulation layer of 1 m 17 K, and the first and second conductive layers 15. 16 both have at least their ends 15A, 16A.
It can be formed so that it can be completely exposed.

以上の構成において、個々の外部リード１］の第１の溝
側１５の端部１５Ａおよび第２の導電層１６の端部１６
ＡＫ対してＩＣチップ１４上の異なった電極１８（ハツ
ト）との間？ワイヤ１９でボンディングすることにより
、ＩＣチップ１４上の電極１８は電気的　３− に外部へ引き出される。In the above configuration, the end 15A of the first groove side 15 of each external lead 1] and the end 16 of the second conductive layer 16
Between AK and different electrodes 18 (hats) on IC chip 14? By bonding with the wire 19, the electrode 18 on the IC chip 14 is electrically drawn out to the outside.

続いて所望部を樹脂によってモールドし外部リード間を
電気的に分離ｊることにより、半導体装置が完成する。Subsequently, the semiconductor device is completed by molding desired parts with resin and electrically isolating the external leads.

このようにして得られにノ（ツケージによれば、一本の
外部リードに対して実質的に二本分の外部リードに対し
てワイヤボンディングを行なったのと同等の結果が得ら
れ、外部リードの配列は本来の本数の半分にすることが
できる。According to Tsukei, the result obtained in this way is essentially the same as wire bonding to two external leads for one external lead, and The array can be reduced to half the original number.

したがってパッケージの実装密度を２倍にすることがで
きる。Therefore, the packaging density of the package can be doubled.

本文実施列では導電層７２層設けたリードフレームの場
合について説明したが、これに限らずさらに３層、４層
の多層化を計ることも可能であり、これによってよりパ
ッケージ実装密度な向上させることができる。In the main text, we have explained the case of a lead frame with 72 conductive layers, but it is not limited to this, and it is also possible to increase the number of layers to three or four, thereby further improving the package packaging density. I can do it.

以上述べて明らかなように本発明によれば、リードフレ
ーム上に固着された半導体菓子の電極と周囲のリードフ
レーム間をワイヤボンディングした半導体装置において
、上記リードフレームを複　４− 数の導１１．＃が互いに絶縁された多層構造となし、各
導電層と上記半導体素子上の異なった電極間ンワイヤボ
ンテイングするように構成したものであるから、パッケ
ージ面積を増大させることなく）くツケージ実装密度を
向上させることができるので従来欠点馨除去することが
できる。As is clear from the above description, according to the present invention, in a semiconductor device in which wire bonding is performed between an electrode of a semiconductor confectionery fixed on a lead frame and a surrounding lead frame, the lead frame is connected to a plurality of conductors 11. It has a multi-layered structure in which # is insulated from each other, and wire bonding is performed between each conductive layer and different electrodes on the semiconductor element, so the packaging density can be reduced without increasing the package area. Since it is possible to improve

本発明は、特に超ＬＳＩチップに対する実装技術として
最適であり、ホ型寸法を維持したままで高集積化ＩＣの
実現が可能なので特に組型スペースの制限された多くの
％種電子機器へ適用分野を拡大することができる。The present invention is especially suitable as a mounting technology for VLSI chips, and it is possible to realize highly integrated ICs while maintaining the same size, so it is particularly applicable to many types of electronic devices with limited assembly space. can be expanded.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来例を示す斜視概略図、第２図および第３図
は共に本発明実施例χ示す上面図および断面図である。 １１・・・外部リード、１２・・・リードフレーム、１
４・・・ＩＣチップ、１５．１６・・・導電層、１７・
・・絶縁層、１８・・・電極、１９・・・ボンディング
ワイヤ。 手続補正書 昭和ω年２　月＞を日 １　事件の表示 昭和５９　年特許願　第０３１５８３７　号２　発明の
名称 半導体装置 ３　補正をする者 事件との関係　特許出願人 住所 名　称　（１４ｇ）　クラリオン株式会社４、代理人〒
１０５ 住　所　東京都港区芝３丁目２番１４号芝三丁目ピル５
、補正の対象 明細書の発明の詳細な説明の欄１図面の簡単な説明の橢
および図面 ６　補正の内容 （１）　ｌＪ［ａ＋ｉｉＦ第５頁ｍ第５百入する。 ［第４図は完成した半導体装置の外観を示すもので，各
リード１１の樹脂４から外部に露出している部分は各々
第１の導電層１５と第２の導電層１６とが絶縁層１７に
よって絶縁されている構造が、そのまま第１図のように
配置される。この場合第１と第２の導電層１５．　１６
に対しては各々別系統の電気信号を加えることができる
。」 （２］明細１１第６負第１５行目を「断面図，第４図は
本発明実施例を示す外観図である。」に引止する。 （３）　図面に別紙のように第４図を追加する。FIG. 1 is a schematic perspective view showing a conventional example, and FIGS. 2 and 3 are a top view and a sectional view showing an embodiment χ of the present invention. 11... External lead, 12... Lead frame, 1
4... IC chip, 15.16... Conductive layer, 17.
...Insulating layer, 18... Electrode, 19... Bonding wire. Procedural amendment document February 1989 > Date 1 Case indication 1982 Patent application No. 0315837 2 Title of the invention Semiconductor device 3 Person making the amendment Relationship to the case Patent applicant address Name (14g) Clarion Co., Ltd. 4. Agent〒
105 Address: Shiba 3-chome Pill 5, 3-2-14 Shiba, Minato-ku, Tokyo
, Detailed Description of the Invention in the Specification Subject to Amendment Column 1 Brief Explanation of Drawings and Drawing 6 Contents of Amendment (1) lJ[a+iiF Page 5 m No. 500. [FIG. 4 shows the appearance of the completed semiconductor device. The parts of each lead 11 exposed to the outside from the resin 4 are covered with a first conductive layer 15, a second conductive layer 16, and an insulating layer 17. The structure insulated by is then placed as shown in FIG. In this case the first and second conductive layers 15. 16
Electrical signals from different systems can be applied to each of them. ” (2) The 6th negative line 15 of Specification 11 is terminated with “A sectional view, and FIG. 4 is an external view showing an embodiment of the present invention.” (3) As attached to the drawing, Add a diagram.

Claims (1)

【特許請求の範囲】[Claims] リードフレーム上に固着された半導体素子の１１極と周
囲のリードフレーム間をワイヤボンディングした半導体
装置において、上記リードフレーム２上数の導電層が互
いに絶縁された多層構造となし、６導を層と上記半導体
素子上の異なった電極間をワイヤボンディングしたこと
を特徴とする半導体装置。In a semiconductor device in which 11 poles of a semiconductor element fixed on a lead frame and a surrounding lead frame are wire-bonded, the conductive layers on the lead frame 2 have a multilayer structure insulated from each other, and six conductive layers are formed. A semiconductor device characterized in that wire bonding is performed between different electrodes on the semiconductor element.
JP59035837A 1984-02-27 1984-02-27 Semiconductor device Pending JPS60180154A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59035837A JPS60180154A (en) 1984-02-27 1984-02-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59035837A JPS60180154A (en) 1984-02-27 1984-02-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60180154A true JPS60180154A (en) 1985-09-13

Family

ID=12453085

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59035837A Pending JPS60180154A (en) 1984-02-27 1984-02-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60180154A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4825279A (en) * 1986-10-08 1989-04-25 Fuji Electric Col, Ltd. Semiconductor device
JPH01233732A (en) * 1988-03-15 1989-09-19 Fujitsu Ltd Semiconductor device
US4912547A (en) * 1989-01-30 1990-03-27 International Business Machines Corporation Tape bonded semiconductor device
US5089878A (en) * 1989-06-09 1992-02-18 Lee Jaesup N Low impedance packaging
US5592019A (en) * 1994-04-19 1997-01-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and module
US5864173A (en) * 1995-04-05 1999-01-26 National Semiconductor Corporation Multi-layer lead frame

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4825279A (en) * 1986-10-08 1989-04-25 Fuji Electric Col, Ltd. Semiconductor device
JPH01233732A (en) * 1988-03-15 1989-09-19 Fujitsu Ltd Semiconductor device
US4912547A (en) * 1989-01-30 1990-03-27 International Business Machines Corporation Tape bonded semiconductor device
US5089878A (en) * 1989-06-09 1992-02-18 Lee Jaesup N Low impedance packaging
US5592019A (en) * 1994-04-19 1997-01-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and module
US5864173A (en) * 1995-04-05 1999-01-26 National Semiconductor Corporation Multi-layer lead frame
US5994768A (en) * 1995-04-05 1999-11-30 National Semiconductor Corporation Multi-layer lead frame
US6087204A (en) * 1995-04-05 2000-07-11 National Semiconductor Corporation Method of making a multi-layer lead frame

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