JPH0198254A - Mos semiconductor device - Google Patents
Mos semiconductor deviceInfo
- Publication number
- JPH0198254A JPH0198254A JP25584087A JP25584087A JPH0198254A JP H0198254 A JPH0198254 A JP H0198254A JP 25584087 A JP25584087 A JP 25584087A JP 25584087 A JP25584087 A JP 25584087A JP H0198254 A JPH0198254 A JP H0198254A
- Authority
- JP
- Japan
- Prior art keywords
- generation circuit
- voltage generation
- substrate voltage
- substrate
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000012544 monitoring process Methods 0.000 claims description 4
- 239000008188 pellet Substances 0.000 abstract description 7
- 230000010355 oscillation Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 7
- 238000007689 inspection Methods 0.000 description 3
- 230000002411 adverse Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＭＯ８型半導体装置に関し、特に基板電圧発生
回路を有するＭＯ８型半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an MO8 type semiconductor device, and particularly to an MO8 type semiconductor device having a substrate voltage generation circuit.
従来、かかる基板電圧発生回路はチップ内に配置されて
おシ、この基板電圧特性などを試験するときはペレット
の検査時にモニターすることにより行っていた。Conventionally, such a substrate voltage generating circuit has been disposed within a chip, and testing of the substrate voltage characteristics has been carried out by monitoring during pellet inspection.
上述したように、従来は基板電圧の測定およびその他の
基板電圧特性のチエツクをペレット検査時に行っている
が、チップをパッケージに組立てた後基板電圧等を測定
しモニターするということは非常に困難であるという欠
点がある。また、パッケージのあきピンに基板電圧発生
回路の出力を接続すると、実装時にあきピン（基板電圧
出力ピン）と他の信号線とが短絡を起こし、半導体装置
が動作しなくなるという欠点もある。As mentioned above, conventionally, measurement of substrate voltage and checking of other substrate voltage characteristics are performed during pellet inspection, but it is extremely difficult to measure and monitor substrate voltage etc. after assembling the chip into a package. There is a drawback. Furthermore, if the output of the substrate voltage generation circuit is connected to the open pin of the package, there is a drawback that the open pin (substrate voltage output pin) and other signal lines will short-circuit during mounting, causing the semiconductor device to malfunction.
本発明の目的は、ペレットの検査時ではなくパッケージ
の組立後に基板電圧のモニターを可能とするＭＯ８型半
導体装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an MO8 type semiconductor device that allows substrate voltage to be monitored after package assembly rather than during pellet inspection.
本発明のＭＯ８ｍ半導体装置は、基板電圧の発生回路と
、負電圧発生回路と１前記基板電圧を外部よりモニター
するためのパッケージあきピンに前記基板電圧を出力す
る回路とを有して構成され、特に前記基板電圧を出力す
る回路はトランジスタＱｏ 、Ｑ（２および入力ピン、
あきピンによって構成され、前記入力ビンＰ１に電位を
印加するととＫより前記あきピン（ＯＵＴ）より基板電
圧をモニターすることにある。The MO8m semiconductor device of the present invention includes a substrate voltage generation circuit, a negative voltage generation circuit, and a circuit for outputting the substrate voltage to a package open pin for externally monitoring the substrate voltage, In particular, the circuit that outputs the substrate voltage includes transistors Qo, Q (2 and input pins,
It is composed of open pins, and when a potential is applied to the input pin P1, the substrate voltage is monitored from the open pin (OUT) from K.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）、 （ｂ）は本発明の第一の実施例を説明
するためのＭＯ８屋半導体装置の電圧発生回路図および
その内部電圧波形図である。FIGS. 1(a) and 1(b) are a voltage generation circuit diagram and an internal voltage waveform diagram of an MO8 semiconductor device for explaining a first embodiment of the present invention.
第１図（ａ）に示すように、このＭＯ８半導体装置の電
圧発生回路は負電圧発生回路１と、基板電圧発生回路２
と、この基板電圧発生回路２に接続されハイ、ローの電
圧を供給するリングオミレータからなる発振回路３とを
有し、ｎチャネルＭＯ８型トランジスタＱｌｌとＱ １
２の接続点に負電圧発生回路１を接続し、且つＱ１２側
に基板電圧発生回路２を接続して構成される。また、基
板電圧を取シ出すため前記Ｑｓｓには入力ピンＰ１が接
続され、前記ＱｕにはあきピンＯＵＴが接続される。As shown in FIG. 1(a), the voltage generation circuit of this MO8 semiconductor device includes a negative voltage generation circuit 1 and a substrate voltage generation circuit 2.
and an oscillation circuit 3 consisting of a ring oscillator connected to the substrate voltage generation circuit 2 and supplying high and low voltages, and includes n-channel MO8 type transistors Qll and Q1.
The negative voltage generation circuit 1 is connected to the connection point of Q12, and the substrate voltage generation circuit 2 is connected to the Q12 side. Further, in order to extract the substrate voltage, an input pin P1 is connected to the Qss, and an open pin OUT is connected to the Qu.
次に、第１図（ｂ）に示すように、かかる電圧発生回路
の動作状態においては、接続点Ｎ２が基板電圧で負電位
に保たれ、また接続点Ｎ１が負電圧発生回路の出力電圧
で負電位に保たれるので、おきピンＯＵＴに表われる出
力はトランジスタＱｓｔのオフ状態によ）フローティン
グ状態になる。Next, as shown in FIG. 1(b), in the operating state of this voltage generation circuit, the connection point N2 is maintained at a negative potential due to the substrate voltage, and the connection point N1 is maintained at a negative potential due to the output voltage of the negative voltage generation circuit. Since it is kept at a negative potential, the output appearing at the standby pin OUT becomes a floating state (due to the off state of the transistor Qst).
ここで、パッケージの基板電圧を測定するときは、入力
ビンＰ１に正の電位を印加することになるので、第一電
源φ１に接続されたトランジスタＱｌｌがオン状態にな
シ、接続点ＮｌがＧＮｉ）レベルに上昇する。この接続
点Ｎ１がＧＮＤレベルになると、トランジスタＱ１！が
オン状態になるので、その結果として出力ピンＯＵＴに
は基板電圧レベルが出力される。淘、接続点Ｎ２は入力
ビンＰＩＫ電位を印加する前後で変化なく常時一定の基
板電圧に維持される。Here, when measuring the substrate voltage of the package, a positive potential is applied to the input bin P1, so the transistor Qll connected to the first power supply φ1 is in the on state, and the connection point Nl is connected to GNi. ) to rise to the level. When this connection point N1 becomes GND level, the transistor Q1! is turned on, and as a result, the substrate voltage level is output to the output pin OUT. The connection point N2 is always maintained at a constant substrate voltage without changing before and after applying the input pin PIK potential.
第２図は本発明の第二の実施例を説明するための電圧発
生回路図である。FIG. 2 is a voltage generation circuit diagram for explaining a second embodiment of the present invention.
第２図に示すように、第二の実施例は負電圧発生回路１
の電圧源であるリングオミレータからなる発振回路３を
基板電圧発生回路２に共用した例である。As shown in FIG. 2, the second embodiment is a negative voltage generating circuit 1.
This is an example in which an oscillation circuit 3 consisting of a ring oscillator, which is a voltage source, is also used as a substrate voltage generation circuit 2.
賞、Ｎ ｌ 〜Ｎ ３はＱｌｌ ＋ Ｑｕと同様にｎチ
ャネル型ＭＯＳトランジスタである。その他は第１図（
ａ）に示す回路と同様であシ、このように構成しても前
述の第一の実施例と同様の結果が得られる。Similarly to Qll+Qu, Nl to N3 are n-channel MOS transistors. Others are shown in Figure 1 (
The circuit is similar to the circuit shown in a), and even with this configuration, the same results as in the first embodiment described above can be obtained.
以上説明したように、本発明のＭＯａ型半導体装置は基
板電圧発生回路と負電圧発生回路とベレットの入力ビン
よりミ圧を印加しパッケージのあきピンに前記基板電圧
を出力させる回路とを有することにより、ペレットを組
立だ後においても基板電圧をモニターし且つモニター時
以外は半導体装置の動作に悪影響を与えないようにする
ことができるという効果がある。As explained above, the MOa type semiconductor device of the present invention has a substrate voltage generation circuit, a negative voltage generation circuit, and a circuit that applies a voltage from the input pin of the pellet and outputs the substrate voltage to the open pin of the package. This has the advantage that the substrate voltage can be monitored even after the pellets are assembled, and the operation of the semiconductor device can be prevented from being adversely affected except during monitoring.
第１図（ａ）、 （ｂ）はそれぞれ本発明の第一の実施
例を説明するためのＭＯ８型半導体装置の電圧発生回路
図および内部電圧波形図、第２図は本発明の第二の実施
例を説明するための電圧発生回路図である。
１・・・・・・負電圧発生回路、２・・・・・・基板電
圧発生回路、３・・・・・・発振回路（リングオシレー
タ） ％ Ｑｌｌ ｒＱｔ＊ 、 Ｎ ｉ〜Ｎ３・・・
・・・ｎチャネルＭＯ８製）ランジスタ、ＰＩ・・・・
・・外部端子、ＯＵＴ・・・・・・あきピン、φ１・・
・・・・第一電源。
代理人 弁理士 内 原 晋1(a) and 1(b) are respectively a voltage generation circuit diagram and an internal voltage waveform diagram of an MO8 type semiconductor device for explaining the first embodiment of the present invention, and FIG. 2 is a diagram of the second embodiment of the present invention. FIG. 2 is a voltage generation circuit diagram for explaining an embodiment. 1...Negative voltage generation circuit, 2...Substrate voltage generation circuit, 3...Oscillation circuit (ring oscillator) % Qll rQt*, Ni~N3...
・・・N-channel MO8) transistor, PI...
・・External terminal, OUT・・Diaper pin, φ1・・
...First power supply. Agent Patent Attorney Susumu Uchihara
Claims (1)
電圧を外部よりモニターするためのパッケージあきピン
に前記基板電圧を出力する回路とを有することを特徴と
するＭＯＳ型半導体装置。1. A MOS semiconductor device comprising: a substrate voltage generation circuit; a negative voltage generation circuit; and a circuit for outputting the substrate voltage to a pin provided in a package for externally monitoring the substrate voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25584087A JPH0198254A (en) | 1987-10-09 | 1987-10-09 | Mos semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25584087A JPH0198254A (en) | 1987-10-09 | 1987-10-09 | Mos semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0198254A true JPH0198254A (en) | 1989-04-17 |
Family
ID=17284320
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25584087A Pending JPH0198254A (en) | 1987-10-09 | 1987-10-09 | Mos semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0198254A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999034445A1 (en) * | 1997-12-26 | 1999-07-08 | Hitachi, Ltd. | Semiconductor integrated circuit |
-
1987
- 1987-10-09 JP JP25584087A patent/JPH0198254A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7321252B2 (en) | 1997-11-21 | 2008-01-22 | Renesas Technology Corporation | Semiconductor integrated circuit |
| WO1999034445A1 (en) * | 1997-12-26 | 1999-07-08 | Hitachi, Ltd. | Semiconductor integrated circuit |
| US6337593B1 (en) | 1997-12-26 | 2002-01-08 | Hitachi, Ltd. | Semiconductor integrated circuit |
| US6483374B1 (en) | 1997-12-26 | 2002-11-19 | Hitachi, Ltd. | Semiconductor integrated circuit |
| US6600360B2 (en) | 1997-12-26 | 2003-07-29 | Hitachi, Ltd. | Semiconductor integrated circuit |
| US6707334B2 (en) | 1997-12-26 | 2004-03-16 | Hitachi, Ltd. | Semiconductor integrated circuit |
| US6987415B2 (en) | 1997-12-26 | 2006-01-17 | Renesas Technology Corporation | Semiconductor integrated circuit |
| US7046075B2 (en) | 1997-12-26 | 2006-05-16 | Renesas Technology Corporation | Semiconductor integrated circuit |
| US7598796B2 (en) | 1997-12-26 | 2009-10-06 | Renesas Technology Corporation | Semiconductor integrated circuit including charging pump |
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