JPH0147016B2 - - Google Patents
Info
- Publication number
- JPH0147016B2 JPH0147016B2 JP59050004A JP5000484A JPH0147016B2 JP H0147016 B2 JPH0147016 B2 JP H0147016B2 JP 59050004 A JP59050004 A JP 59050004A JP 5000484 A JP5000484 A JP 5000484A JP H0147016 B2 JPH0147016 B2 JP H0147016B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- conductivity type
- region
- gate electrode
- dose
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000012535 impurity Substances 0.000 claims description 73
- 238000005468 ion implantation Methods 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 28
- 239000004065 semiconductor Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 238000000576 coating method Methods 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 2
- 238000009792 diffusion process Methods 0.000 claims 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 claims 1
- 229910052750 molybdenum Inorganic materials 0.000 claims 1
- 239000011733 molybdenum Substances 0.000 claims 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 20
- 229910052796 boron Inorganic materials 0.000 description 16
- 239000010410 layer Substances 0.000 description 16
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 10
- 229910052785 arsenic Inorganic materials 0.000 description 10
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- -1 boron ion Chemical class 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052736 halogen Inorganic materials 0.000 description 2
- 150000002367 halogens Chemical class 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 description 1
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 description 1
- YTAHJIFKAKIKAV-XNMGPUDCSA-N [(1R)-3-morpholin-4-yl-1-phenylpropyl] N-[(3S)-2-oxo-5-phenyl-1,3-dihydro-1,4-benzodiazepin-3-yl]carbamate Chemical compound O=C1[C@H](N=C(C2=C(N1)C=CC=C2)C1=CC=CC=C1)NC(O[C@H](CCN1CCOCC1)C1=CC=CC=C1)=O YTAHJIFKAKIKAV-XNMGPUDCSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001638 boron Chemical class 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置の製造方法に関し、特に相
補型MOS（CMOS）半導体装置にLDD（Lightly
Doped Drain）構造を適用する方法に係る。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a complementary MOS (CMOS) semiconductor device.
Concerning the method of applying the Doped Drain) structure.
近年、MOS半導体装置の実効チヤネル長がサ
ブミクロンオーダーまで微細化されるにつれ、ド
レイン領域近傍でのチヤネル領域における強電界
によつて引き起こされるホツトキヤリアの発生に
伴うしきい値電圧の変動等の諸特性の劣化が問題
となつている。
In recent years, as the effective channel length of MOS semiconductor devices has been miniaturized to the submicron order, various characteristics such as threshold voltage fluctuations due to the generation of hot carriers caused by strong electric fields in the channel region near the drain region have become increasingly important. deterioration has become a problem.
こうした問題を解消するためにLDD（Lightly
Doped Drain）構造が提案されている。この
LDD構造はMOS半導体装置のドレイン領域（及
びソース領域）をチヤネル領域近傍の低濃度不純
物領域とこの低濃度不純物領域に隣接する高濃度
不純物領域とから構成し、前記低濃度不純物領域
でチヤネル領域における強電界を緩和しようとす
るものである。 To solve these problems, LDD (Lightly
Doped Drain) structure has been proposed. this
In the LDD structure, the drain region (and source region) of a MOS semiconductor device is composed of a low concentration impurity region near a channel region and a high concentration impurity region adjacent to this low concentration impurity region. This is intended to alleviate strong electric fields.
上記LDD構造をCMOS半導体装置のNMOS，
PMOSともに適用する場合、第１図ａ〜ｇに示
すような方法で行なわれている。 The above LDD structure can be used as an NMOS of a CMOS semiconductor device.
When both PMOS and PMOS are applied, the method shown in FIGS. 1a to 1g is used.
まず、例えばＰ型シリコン基板１の一部に選択
的にはＮ型ウエル領域２を形成した後、フイール
ド酸化膜３を形成する。次に、ウエル領域２以外
の基板１及びウエル領域２上にそれぞれゲート酸
化膜４，４を介してゲート電極５1，５2を形成す
る（第１図ａ図示）。つづいて、ウエル領域２上
にホトレジストパターン６を形成した後、このホ
トレジストパターン６及びゲート電極５1をマス
クとしてウエル領域２以外の基板１に例えばヒ素
を低ドーズ量でイオン注入し、ヒ素イオン注入層
７を形成する（同図ｂ図示）。つづいて、前記ホ
トレジストパターン６を除去し、ウエル領域２以
外の基板１上にホトレジストパターン８を形成し
た後、のホトレジストパターン８及びゲート電極
５2をマスクとしてウエル領域２にボロンを低ド
ーズ量でイオン注入し、ボロンイオン注入層９を
形成する（同図ｃ図示）。 First, for example, an N-type well region 2 is selectively formed in a part of a P-type silicon substrate 1, and then a field oxide film 3 is formed. Next, gate electrodes 5 1 and 5 2 are formed on the substrate 1 and the well region 2 other than the well region 2 via gate oxide films 4 and 4, respectively (as shown in FIG. 1A). Subsequently, after forming a photoresist pattern 6 on the well region 2, using the photoresist pattern 6 and the gate electrode 51 as masks, arsenic, for example, is ion-implanted at a low dose into the substrate 1 other than the well region 2. A layer 7 is formed (as shown in Figure b). Subsequently, after removing the photoresist pattern 6 and forming a photoresist pattern 8 on the substrate 1 other than the well region 2, a low dose of boron is applied to the well region 2 using the photoresist pattern 8 and the gate electrode 52 as a mask. Ions are implanted to form a boron ion-implanted layer 9 (as shown in FIG. 3C).
次いで、前記ホトレジストパターン８を除去し
た後、全面に例えばCVD酸化膜を堆積し、更に
異方性エツチングによりエツチングしてゲート電
極５1，５2の側壁にCVD酸化膜１０，…を残存
させる（同図ｄ図示）。つづいて、ウエル領域２
上にホトレジストパターン１１を形成し、このホ
トレジストパターン１１、ゲート電極５1及びゲ
ート電極５1側壁に残存しているCVD酸化膜１
０，１０をマスクとしてウエル領域２以外の基板
１に例えばヒ素を高ドーズ量でイオン注入し、ヒ
素イオン注入層１２を形成する（同図ｅ図示）。
つづて、前記ホトレジストパターン１１を除去し
た後、ウエル領域２以外の基板１上にホトレジス
トパターン１３を形成し、このホトレジストパタ
ーン１３、ゲート電極５2及びゲート電極５2側壁
に残存しているCVD酸化膜１０，１０をマスク
としてウエル領域２にボロンを高ドーズ量でイオ
ン注入し、ボロンイオン注入層１４を形成する
（同図ｆ図示）。 Next, after removing the photoresist pattern 8, a CVD oxide film, for example, is deposited on the entire surface and further etched by anisotropic etching to leave CVD oxide films 10, . . . on the side walls of the gate electrodes 5 1 , 5 2 ( (Illustrated in figure d). Next, well area 2
A photoresist pattern 11 is formed on the photoresist pattern 11, the gate electrode 5 1 and the CVD oxide film 1 remaining on the sidewalls of the gate electrode 5 1 .
0 and 10 as a mask, arsenic, for example, is ion-implanted at a high dose into the substrate 1 other than the well region 2 to form an arsenic ion-implanted layer 12 (as shown in the figure e).
Next, after removing the photoresist pattern 11, a photoresist pattern 13 is formed on the substrate 1 other than the well region 2, and the CVD oxidation remaining on the photoresist pattern 13, the gate electrode 52 , and the sidewalls of the gate electrode 52 is Boron is ion-implanted at a high dose into the well region 2 using the films 10, 10 as a mask to form a boron ion-implanted layer 14 (as shown in the figure f).
次いで、前記ホトレジストパターン１３を除去
した後、熱処理して前記ヒ素イオン注入層７，１
２及びボロンイオン注入層９，１４の不純物を活
性化させ、ウエル領域２以外の基板１にゲー電極
５1近傍のN-型不銃物領域１５ａ，１６ａとこれ
らの領域に隣接するN+型不純物領域１５ｂ，１
６ｂからなるソースドレイン領域１５，１６をウ
エル領域２にゲー電極５2近傍のP-型不純物領域
１７ａ，１８ａとこれらの領域に隣接するp+型
不純物領域１７ｂ，１８ｂとからなるソース、ド
レイン領域１７，１８を形成する（同図ｇ図示）。 Next, after removing the photoresist pattern 13, heat treatment is performed to form the arsenic ion-implanted layers 7, 1.
2 and boron ion - implanted layers 9 and 14 to activate the impurities in the substrate 1 other than the well region 2 . Impurity region 15b,1
Source and drain regions 15 and 16 consisting of P - type impurity regions 17a and 18a near the gate electrode 5 2 and p + type impurity regions 17b and 18b adjacent to these regions are placed in the well region 2. 17 and 18 (shown in g of the same figure).
以下、通常の工程に従い、層間絶縁膜の堆積、
コンタクトホール開孔、配線形成を行ない、
LDD構成のCMOSを製造する。 Hereafter, according to the usual process, the interlayer insulating film is deposited,
Opening contact holes and forming wiring,
Manufacture CMOS with LDD configuration.
しかしながら、上述した従来の方法では
NMOS，PMOSとともにLDD構造とするため
に、第１図ｂ，ｃ，ｅ及びｆに示すように合計４
回の写真蝕刻工程が必要であり、工程が煩雑にな
るうえコストが高騰する。また、CVD酸化膜を
異方性エツチングによりエツチングしてゲート電
極５1，５2の側壁に残存させる際、サイドエツチ
ングが起こるので低濃度不純物領域の寸法の制御
性が悪くなる。
However, the conventional method described above
In order to form an LDD structure together with NMOS and PMOS, a total of 4
This requires multiple photo-etching steps, which makes the process complicated and increases costs. Furthermore, when the CVD oxide film is etched by anisotropic etching to remain on the side walls of the gate electrodes 5 1 and 5 2 , side etching occurs, resulting in poor controllability of the dimensions of the low concentration impurity region.
また、従来の方法ではパンチスルー及びシヨー
トチヤネル効果を防止するために、チヤネルイオ
ン注入によりチヤネルの基板濃度をある程度高く
しておくか、バツクゲートバイアス効果（ソー
ス・基板間の電圧の上昇に伴い、しきい値電圧が
上昇する現象）によりデバイスの特性を劣化させ
るという欠点がある。 In addition, in conventional methods, in order to prevent punch-through and short channel effects, it is necessary to increase the substrate concentration of the channel to a certain extent by channel ion implantation, or to prevent the backgate bias effect (as the voltage between the source and the substrate increases, This has the disadvantage that device characteristics deteriorate due to a phenomenon in which the threshold voltage increases.
本発明は上記欠点を解消するためになされたも
のであり、LDD構造をCMOSに適用した場合、
写真蝕刻工程の回数を減らして工程を簡便化しコ
ストを低減するとともにバツクゲートバイアス効
果を防止できる半導体装置の製造方法を提供しよ
うとするものである。
The present invention was made to eliminate the above drawbacks, and when the LDD structure is applied to CMOS,
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can simplify the process and reduce costs by reducing the number of photolithography steps, and can also prevent backgate bias effects.
本発明の半導体装置の製造方法は、第１導電型
の半導体基板の第１及び第２の素子領域にそれぞ
れゲート絶縁膜を介してゲート電極を形成し、表
面に第１、第２及び第３の被膜を順次形成た後、
異方性エツチングにより各ゲート電極側壁に第１
の被膜を介して第２の被膜を残存させ、つづいて
第１の素子領域での第２導電型不純物の高ドーズ
イオン注入、残存した第２の被膜除去、第２導電
型不純物の低ドーズイオン注入及び第１導電型不
純物のイオン注入を行ない、また第２の素子領域
での第１導電型不純物の高ドーズイオン注入、残
存した第２の被膜除去、第１導電型不純物の低ド
ーズイオン注入、第２導電型不純物のイオン注入
を行ない、更に熱処理により不純物を活性化さ
せ、第１の素子領域にLDD構造のソース、ドレ
イン領域及び第１導電型の不純物領域（ポケツト
領域）を、第２の素子領域にLDD構造のソース、
ドレイン領域及び第２導電型の不純物領域（ポケ
ツト領域）をそれぞれ形成することを骨子とする
ものである。
In the method for manufacturing a semiconductor device of the present invention, gate electrodes are formed in the first and second element regions of a first conductivity type semiconductor substrate through gate insulating films, and first, second and third gate electrodes are formed on the surface of the semiconductor substrate. After sequentially forming the films of
A first layer is formed on the sidewall of each gate electrode by anisotropic etching.
The second film remains through the film, followed by high-dose ion implantation of the second conductivity type impurity in the first element region, removal of the remaining second film, and low-dose ion implantation of the second conductivity type impurity. implantation and ion implantation of first conductivity type impurities, high dose ion implantation of first conductivity type impurities in the second element region, removal of the remaining second film, and low dose ion implantation of first conductivity type impurities. , ions of second conductivity type impurities are implanted, and the impurities are further activated by heat treatment to form the source and drain regions of the LDD structure and the first conductivity type impurity regions (pocket regions) in the first device region, and the second conductivity type impurity regions (pocket regions). The source of the LDD structure is placed in the element region of
The main idea is to form a drain region and a second conductivity type impurity region (pocket region), respectively.
このような方法によれば、第１及び第２の素子
領域について、それぞれ高ドーズイオン注入、残
存した第２の被膜除去及び低ドーズイオン注入を
連続的に行なうので、LDD構造のソース、ドレ
イン領域を形成するための写真蝕刻工程を従来の
４回から２回に減少させることができる。また、
ポケツト領域によりパンチスルー及びシヨートチ
ヤネル効果を防止でき、チヤネルイオン注入で基
板濃度をそれほど高濃度とする必要がないので、
バツクゲートバイアス効果を防止することができ
る。 According to this method, high-dose ion implantation, removal of the remaining second film, and low-dose ion implantation are sequentially performed for the first and second device regions, so that the source and drain regions of the LDD structure are The number of photo-etching steps required to form the image can be reduced from the conventional four steps to two steps. Also,
The pocket region prevents punch-through and short channel effects, and channel ion implantation does not require a very high substrate concentration.
Backgate bias effects can be prevented.
以下、本発明の実施例を第２図ａ〜ｌを参照し
て説明する。
Hereinafter, embodiments of the present invention will be described with reference to FIGS. 2a to 1.
まず、Ｐ型シリコン基板２１の一部にＮ型ウエ
ル領域２２を形成した後、選択酸化法によりフイ
ールド酸化膜２３を形成する。次に、しきい値制
御用のチヤネルイオン注入を行なつた後、ウエル
領域２２以外の基板２１（第１の素子領域）上及
びウエル領域２２（第２の素子領域）上にそれぞ
れゲート酸化膜２４，２４を介してゲート電極２
５1，２５2を形成する（第２図ａ図示）。つづい
て、ゲート電極２５1，２５2の表面及び露出した
基板２１、ウエル領域２２の表面に膜厚100〜
1000Åの熱酸化膜（第１の被膜）２６を形成す
る。つづいて、全面に膜厚1000Å〜1μｍの多結
晶シリコン膜（第２の被膜）２７を堆積し、更に
熱酸化を行ない多結晶シリコン膜２７表面に膜厚
100〜1000Åの熱酸化膜（第３被膜）２８を形成
する（同図ｂ図示）。次いで、反応性イオンエツ
チングにより前記熱酸化膜２８をエツチングし、
ゲート電極２５1，２５2の形状に対応する多結晶
シリコン膜２７の段差部の側壁に残存熱酸化膜２
８′，…を形成する（同図ｃ図示）。つづいて、残
存熱酸化膜２８′，…をマスクとして反応性イオ
ンエツチングにより多結晶シリコン膜２７をエツ
チングし、ゲート電極２５1，２５2の側壁に熱酸
化膜２６を介して、残存多結晶シリコン膜２７′
…，を形成する。この残存多結晶シリコン膜２
７′，…の端部には残存熱酸化膜２８′，…が形成
された状態となつている。このように多結晶シリ
コン膜２７の反応性イオンエツチング時に残存熱
酸化膜８′，…によりサイドエツチングが防止さ
れ、多結晶シリコン膜２７の膜厚に等しい幅の残
存多結晶シリコン膜２７′，…が制御性よく形成
される（同図ｄ図示）。 First, an N-type well region 22 is formed in a part of a P-type silicon substrate 21, and then a field oxide film 23 is formed by selective oxidation. Next, after channel ion implantation for threshold control is performed, a gate oxide film is formed on the substrate 21 (first device region) other than the well region 22 and on the well region 22 (second device region). Gate electrode 2 via 24, 24
5 1 and 25 2 (as shown in Figure 2a). Subsequently, a film with a thickness of 100 to 100 nm is applied to the surfaces of the gate electrodes 25 1 and 25 2 , the exposed substrate 21, and the well region 22.
A thermal oxide film (first film) 26 of 1000 Å is formed. Next, a polycrystalline silicon film (second film) 27 with a thickness of 1000 Å to 1 μm is deposited on the entire surface, and thermal oxidation is further performed to form a thick film on the surface of the polycrystalline silicon film 27.
A thermal oxide film (third film) 28 with a thickness of 100 to 1000 Å is formed (as shown in Figure b). Next, the thermal oxide film 28 is etched by reactive ion etching,
A residual thermal oxide film 2 is formed on the side wall of the stepped portion of the polycrystalline silicon film 27 corresponding to the shape of the gate electrodes 25 1 and 25 2 .
8',... (as shown in figure c). Next, the polycrystalline silicon film 27 is etched by reactive ion etching using the remaining thermal oxide films 28 ' , . membrane 27'
..., is formed. This remaining polycrystalline silicon film 2
Residual thermal oxide films 28', . . . are formed at the ends of 7', . In this way, side etching is prevented by the residual thermal oxide films 8', . . . during reactive ion etching of the polycrystalline silicon film 27, and the remaining polycrystalline silicon films 27', . is formed with good controllability (as shown in figure d).
次いで、ウエル領域２２上にホトレジストパタ
ーン２９を形成し、このホトレジストパターン２
９，ゲート電極２５1及びその側壁の残存多結晶
シリコン膜２７′，２７′をマスクとしてウエル領
域２２以外の基板２１に例えばヒ素を高ドーズ量
（通常のソース、ドレイン形成のためのドーズ量
程度）でイオン注入し、ヒ素イオン注入層３０を
形成する（同図ｅ図示）。つづて、ハロゲン系の
プラズマガスあるいはKOH系のエツチヤントを
用いた等方性エツチングによりゲート電極２５1
側壁の残存多結晶シリコン膜２７′，２７′を除去
し、同時に残存熱酸化膜２８′，２８′をリフトオ
フする。つづいて、ホトレジストパターン２９及
びゲート電極２５1をマスクとしてウエル領域２
２以外の基板２１に例えばヒ素を低ドーズ量でイ
オン注入し、ヒ素イオン注入層３１を形成する
（同図ｆ図示）。更に、ポケツト領域形成のたにホ
トレジストパターン２９及びゲート電極２５1を
マスクとしてウエル領域２２以外の基板２１に
1012〜1013cm-2のドーズ量でボロンをイオン注入
し、ボロンイオン注入層３２を形成する。このボ
ロンイオン注入は前記ヒ素の低ドーズイオン注入
よりも深くする（同図ｇ図示）。 Next, a photoresist pattern 29 is formed on the well region 22, and this photoresist pattern 2
9. Using the gate electrode 251 and the remaining polycrystalline silicon films 27' and 27' on its side walls as a mask, apply a high dose of arsenic to the substrate 21 other than the well region 22 (approximately the dose for normal source and drain formation). ) to form an arsenic ion-implanted layer 30 (as shown in Figure e). Next, the gate electrode 25 1 is etched by isotropic etching using a halogen-based plasma gas or a KOH-based etchant.
The remaining polycrystalline silicon films 27', 27' on the side walls are removed, and at the same time, the remaining thermal oxide films 28', 28' are lifted off. Next, using the photoresist pattern 29 and the gate electrode 251 as a mask, the well region 2 is
For example, arsenic is ion-implanted at a low dose into the substrates 21 other than 2 to form an arsenic ion-implanted layer 31 (as shown in the figure f). Furthermore, when forming the pocket region, the photoresist pattern 29 and the gate electrode 251 are used as a mask to form a pattern on the substrate 21 other than the well region 22.
Boron ions are implanted at a dose of 10 12 to 10 13 cm −2 to form a boron ion implanted layer 32 . This boron ion implantation is made deeper than the low-dose arsenic ion implantation (as shown in figure g).
次いで、前記ホトレジストパターン２９を除去
した後、ウエル領域２２以外の基板２１上にホト
レジストパターン３３を形成し、このホトレジス
トパターン３３、ゲート電極２５2及びその側壁
の残存多結晶シリコン膜２７′，２７′をマスクと
してウエル領域２２にボロンをイオン注入し、ボ
ロンイオン注入層３４を形成する（同図ｈ図示）。
つづいて、ハロゲン系のプラズマガスあるいは
KOH系のエツチヤントを用いた等方性エツチン
グによりゲート電極２５2側壁の残存多結晶シリ
コン膜２７′，２７′を除去し、同時に残存熱酸化
膜２８′，２８′をリフトオフする。つづいて、ホ
トレジストパターン３３及びゲート電極２５2を
マスクとしてウエル領域２２にボロンを低ドーズ
量でイオン注入し、ボロンイオン注入層３５を形
成する（同図ｉ図示）。更に、ポケツト領域形成
のためにホトレジストパターン２９及びゲート電
極２５2をマスクとしてウエル領域２２に1012〜
1013cm-2のドーズ量で例えばリンをイオン注入
し、リンイオン注入層３６を形成する（同図ｊ図
示）。 Next, after removing the photoresist pattern 29, a photoresist pattern 33 is formed on the substrate 21 other than the well region 22, and this photoresist pattern 33, the gate electrode 252 , and the remaining polycrystalline silicon films 27', 27' on the side walls thereof are removed. Using this as a mask, boron ions are implanted into the well region 22 to form a boron ion implantation layer 34 (shown in h of the same figure).
Next, halogen-based plasma gas or
The remaining polycrystalline silicon films 27', 27' on the side walls of the gate electrode 252 are removed by isotropic etching using a KOH-based etchant, and at the same time, the remaining thermal oxide films 28', 28' are lifted off. Subsequently, using the photoresist pattern 33 and the gate electrode 252 as a mask, boron is ion-implanted into the well region 22 at a low dose to form a boron ion-implanted layer 35 (as shown in the figure i). Furthermore, in order to form a pocket region, 10 12 to 10 12 to
For example, phosphorus is ion-implanted at a dose of 10 13 cm -2 to form a phosphorus ion-implanted layer 36 (as shown in j in the same figure).
次いで、前記ホトレジストパターン３３を除去
した後、熱処理により各イオン注入層の不純物を
活性化させ、ウエル領域２２以外の基板２１にゲ
ート電極２５1近傍のN-型不純物領域３７ａ，３
８ａ（不純物濃度1016〜1018cm-3）とこれらの領域
に隣接するN+型不純物領域３７ｂ，３８ｂ（不純
物濃度1019〜1021cm-3）とからなるソース、ドレ
イン領域３７，３８及び前記N-型不純物領域３
７ａ，３８ａの下部に接するＰ型ポケツト領域３
９，３９を、ウエル領域２２にゲート電極２５2
近傍のP-型不純物領域４０ａ，４１ａ（不純物濃
度1016〜1018cm-3）とこれらの領域に隣接するP+
型不純物領域４０ｂ，４１ｂ（不純物濃度1019〜
1021cm-3）とからなるソース、ドレイン領域４
０，４１及び前記P-型不純物領域４０ａ，４１
ａの下部に接するＮ型ポケツト領域４２，４２
を、それぞれ形成する（同図ｋ図示）。次いで、
全面に層間絶縁膜としてCVD酸化膜４３を堆積
した後、コンタクトホールを開孔し、更に全面に
Al膜を蒸着した後、パターニングしてAl配線４
４を形成し、NMOS，PMOSともにLDD構造の
CMOS半導体装置を製造する（同図ｌ図示）。 Next, after removing the photoresist pattern 33, the impurities in each ion implantation layer are activated by heat treatment, and N - type impurity regions 37a, 3 near the gate electrode 251 are formed in the substrate 21 other than the well region 22.
Source and drain regions 37 and 38 are composed of N + type impurity regions 8a (impurity concentration 10 16 to 10 18 cm -3 ) and N + type impurity regions 37b and 38b (impurity concentration 10 19 to 10 21 cm -3 ) adjacent to these regions. and the N - type impurity region 3
P-type pocket area 3 in contact with the lower part of 7a and 38a
9, 39, and the gate electrode 25 2 in the well region 22.
Nearby P - type impurity regions 40a, 41a (impurity concentration 10 16 to 10 18 cm -3 ) and P + adjacent to these regions
Type impurity regions 40b, 41b (impurity concentration 10 19 ~
10 21 cm -3 ), the source and drain regions 4
0, 41 and the P - type impurity regions 40a, 41
N-type pocket regions 42, 42 in contact with the lower part of a
are formed respectively (as shown in figure k). Then,
After depositing a CVD oxide film 43 as an interlayer insulating film on the entire surface, contact holes are opened and
After depositing the Al film, it is patterned and the Al wiring 4
4, and both NMOS and PMOS have an LDD structure.
A CMOS semiconductor device is manufactured (as shown in FIG. 1).
しかして、上述した方法によれば、第２図ａ〜
ｄの工程でゲート電極２５1，２５2の側壁に熱酸
化膜（第１の被膜）２６を介して残存多結晶シリ
コン膜２７′，…を形成し、同図ｅの工程でウエ
ル領域２２上にホトレジストパターン２９を形成
した後、ヒ素の高ドーズイオン注入（同図ｅの工
程）、ゲート電極５1側壁の残存多結晶シリコン膜
２７′，…の除去及びヒ素の低ドーズイオン注入
（同図ｆの工程）、Ｐポケツト形成のためのボロン
イオン注入（同図ｇの工程）を連続的に行ない、
更に同図ｈの工程でウエル領域２２以外の基板２
１上にホトレジストパターン３３を形成した後、
ボロンの高ドーズイオン注入（同図ｈの工程）、
ゲート電極２５2側壁の残存多結晶シリコン膜２
７′，…の除去及びボロンの低ドーズイオン注入
（同図ｉの工程）、Ｎポケツト形成のためのリンイ
オン注入（同図ｊの工程）を連続的に行なうこと
によりNMOS，PMOSともにLDD構造でポケツ
ト領域を有するCMOS半導体装置を製造するこ
とができる。すなわち、LDD構造形成のために
従来は４回必要であつて写真蝕刻工程を２回に減
少させることができ、工程の簡便化及びコストの
低減を達成することができる。 According to the method described above, FIG.
In the step d , residual polycrystalline silicon films 27 ' , . After forming a photoresist pattern 29, high-dose ion implantation of arsenic (step e in the same figure), removal of the remaining polycrystalline silicon film 27' on the side wall of the gate electrode 51 , and low-dose ion implantation of arsenic (step e in the same figure) are performed. Step f), boron ion implantation for forming a P pocket (step g in the same figure) are carried out continuously,
Furthermore, in the step h of the same figure, the substrate 2 other than the well region 22 is
After forming a photoresist pattern 33 on 1,
High-dose boron ion implantation (step h in the same figure)
Gate electrode 25 2 Remaining polycrystalline silicon film 2 on side wall
By sequentially removing 7', ..., implanting low-dose boron ions (step i in the same figure), and implanting phosphorus ions to form N pockets (step j in the same figure), both NMOS and PMOS can have an LDD structure. A CMOS semiconductor device having a pocket region can be manufactured. That is, the photolithography process, which conventionally required four steps, can be reduced to two to form the LDD structure, thereby simplifying the process and reducing costs.
また、第２図ｃの工程における反応性イオンエ
ツチング（RIE）による熱酸化膜２８のエツチン
グ及び同図ｄの工程における残存熱酸化膜２８′，
…をマスクとしてRIEによる多結晶シリコン膜２
７のエツチングを行なうことにより、サイドエツ
チングが起こることがなく、極めて制御性よくゲ
ート電極２５1，２５2の側壁に残存多結晶シリコ
ン膜２７′，…を形成することができる。したが
つて、LDD構造のソース、ドレイン領域の低濃
度不純物領域の所定の寸法とすることができる。 In addition, the thermal oxide film 28 is etched by reactive ion etching (RIE) in the step of FIG. 2c, and the remaining thermal oxide film 28',
Polycrystalline silicon film 2 by RIE using ... as a mask
By carrying out the etching step 7, the remaining polycrystalline silicon films 27', . . . can be formed on the side walls of the gate electrodes 25 1 and 25 2 with extremely good controllability without causing side etching. Therefore, the low concentration impurity regions of the source and drain regions of the LDD structure can have predetermined dimensions.
また、Ｐ型ポケツト領域３９，３９及びＮ型ポ
ケツト領域４２，４２を形成することによりパン
チスルー及びシヨートチヤネル効果を有効に防止
することができ、チヤネルイオン注入により基板
濃度をそれほど高濃度とする必要がないので、バ
ツクゲートバイアス効果を防止することができ
る。 Furthermore, by forming the P-type pocket regions 39, 39 and the N-type pocket regions 42, 42, punch-through and short channel effects can be effectively prevented, and it is not necessary to make the substrate concentration so high by channel ion implantation. Therefore, the backgate bias effect can be prevented.
なお、上記実施例では第１の被膜として熱酸化
膜を用いたが、これに限らずスパツタ法または
CVD法により形成した酸化膜又は窒化膜でもよ
い。また、第２の被膜としては多結晶シリコン膜
を用いたが、これに限らずCVD法により形成し
たシリコン窒化膜でもよい。また、第３の被膜と
しては多結晶シリコン膜の熱酸化膜を用いたが、
スパツタ法又はCVD法により形成した酸化膜、
窒化膜、Al膜又はMo膜でもよい。 In addition, in the above embodiment, a thermal oxide film was used as the first film, but the method is not limited to this, and sputtering or
An oxide film or a nitride film formed by a CVD method may be used. Further, although a polycrystalline silicon film is used as the second film, the present invention is not limited to this, and a silicon nitride film formed by a CVD method may be used. In addition, as the third film, a thermally oxidized polycrystalline silicon film was used.
Oxide film formed by sputtering method or CVD method,
A nitride film, an Al film, or a Mo film may be used.
ただし、第２図ｄの工程で示したように第２の
被膜の異方性エツチング時に残存している第３の
被膜がエツチングされてはならず、かつ基板がエ
ツチングされないためのマスクとなる第１の被膜
もエツチングされてはならないので、第２の被膜
と第３の被膜及び第２の被膜と第１の被膜は異な
る材質であることが必要である。このような条件
を満たすとともに工程の簡便さを考慮した場合、
第１〜第３の被膜は上記実施例で用いたものが最
も適当である。また、LDD構造のソース、ドレ
イン領域の低濃度不純物領域の寸法制御性を考慮
した場合、第１の被膜の膜厚は100〜1000Å、第
２の被膜の膜厚は1000Å〜1μｍ、第３の被膜の
膜厚は100〜100Åであることが望ましい。 However, as shown in the step of FIG. 2d, the remaining third film must not be etched during the anisotropic etching of the second film, and the third film must not be etched as a mask to prevent the substrate from being etched. Since the first coating must not be etched, the second coating and the third coating and the second coating and the first coating must be made of different materials. When satisfying these conditions and considering the simplicity of the process,
The most suitable first to third coatings are those used in the above embodiments. Also, when considering the dimensional controllability of the low concentration impurity regions of the source and drain regions of the LDD structure, the thickness of the first film is 100 to 1000 Å, the thickness of the second film is 1000 Å to 1 μm, and the thickness of the third film is 100 to 1000 Å. The thickness of the coating is preferably 100 to 100 Å.
なお、第３の被膜は第２の被膜の段差部側壁に
残存され、第２の被膜の異方性エツチング時に第
２の被膜のサイドエツチング防止する役割を担つ
ているが、LDD構造のソース、ドレイン領域を
構成する低濃度不純物領域の横方向の巾にマージ
ンがある場合、あるいは第２の被膜のエツチング
が制御性よく、残存した第３の被膜がなくとも行
なえる場合には第３の被膜は形成しなくてもよ
い。この場合、前記低濃度不純物領域の横方向の
巾のマージンを予め知つておく必要がある。 Note that the third film remains on the side wall of the stepped portion of the second film and plays the role of preventing side etching of the second film during anisotropic etching of the second film. If there is a margin in the lateral width of the low concentration impurity region constituting the drain region, or if the etching of the second film is well controlled and can be performed without the remaining third film, the third film is etched. does not need to be formed. In this case, it is necessary to know in advance the lateral width margin of the low concentration impurity region.
また、上記実施例ではＰ型シリコン基板にＮ型
ウエル領域を形成する場合について説明したが、
Ｎ型シリコン基板にＰ型ウエル領域を形成しても
よいことは勿論である。また、上記実施例では
NMOS形成用のイオン注入、PMOS形成用のイ
オン注入の順に行なつたが、この順序は逆でもよ
い。また、低濃度不純物領域形成用のイオン注入
とポケツト領域形成用のイオン注入の順序も逆で
もよい。これらのイオン注入後の不純物の活性化
のための熱処理は随時行なうことができる。 Furthermore, in the above embodiment, the case where an N-type well region is formed in a P-type silicon substrate has been explained.
Of course, a P-type well region may be formed in an N-type silicon substrate. Also, in the above example
Although ion implantation for forming NMOS and ion implantation for forming PMOS were performed in this order, this order may be reversed. Furthermore, the order of ion implantation for forming a low concentration impurity region and ion implantation for forming a pocket region may be reversed. Heat treatment for activating these impurities after ion implantation can be performed at any time.
更に、第２図ｆの工程におけるＮ型不純物の低
ドーズイオン注入は１種の不純物（As）のみを
用いたが、この低ドーズイオン注入は拡散係数の
大きい不純物（Ｐ）と拡散係数の小さい不純物
（As）の２種の不純物を用いてもよい。このよう
に２種の不純物を用いると、NMOSのソース、
ドレイン領域は第３図に示すようにゲート電極近
傍のＮ型不純物領域５１及びN-型不純物領域５
２、これらの領域に隣接するN+型不純物領域５
３及びＰ型ポケツト領域５４とで構成される。上
記実施例のようにゲート電極近傍がN-型不純物
領域だけで形成されている場合には抵抗が無視で
きなくなるおそれがあるのに対し、このような構
成によればＮ型不純物領域５１によつて高抵抗化
を緩和することができる。 Furthermore, the low-dose ion implantation of N-type impurities in the process shown in Figure 2 f used only one type of impurity (As); Two types of impurities (As) may be used. When two types of impurities are used in this way, the NMOS source,
As shown in FIG. 3, the drain region includes an N type impurity region 51 and an N - type impurity region 5 near the gate electrode.
2. N + type impurity region 5 adjacent to these regions
3 and a P-type pocket region 54. If the vicinity of the gate electrode is formed only of the N - type impurity region as in the above embodiment, there is a risk that the resistance will not be negligible. Therefore, the increase in resistance can be alleviated.
以上詳述した如く、本発明の半導体装置の製造
方法によれば、簡便な工程で素子の微細化に伴う
素子特性の劣化を有効に防止し得るCMOS半導
体装置を製造できる等顕著な効果を奏するもので
ある。
As detailed above, the method for manufacturing a semiconductor device of the present invention has remarkable effects such as being able to manufacture a CMOS semiconductor device that can effectively prevent deterioration of device characteristics due to device miniaturization through a simple process. It is something.
第１図ａ〜ｇは従来のCMOSの製造方法を示
す断面図、第２図ａ〜ｌは本発明の実施例におけ
るCMOSの製造方法を示す断面図、第３図は本
発明の他の実施例において形成されるＮ型ソー
ス、ドレイン領域の説明図である。
２１……Ｐ型シリコン基板、２２……Ｎ型ウエ
ル領域、２３……フイールド酸化膜、２４……ゲ
ート酸化膜、２５1，２５2……ゲート電極、２６
……熱酸化膜（第１の被膜）、２７……多結晶シ
リコン膜（第２の被膜）、２７′……残存多結晶シ
リコン膜、２８……熱酸化膜（第３の被膜）、２
８′……残存熱酸化膜、２９，３３……ホトレジ
ストパターン、３０，３１，３６……リンイオン
注入層、３２，３４，３５……ボロンイオン注入
層、３７ａ，３８ａ……N-型不純物領域、３７
ｂ，３８ｂ……N+型不純物領域、３７，３８…
…ソース、ドレイン領域、３９……Ｐ型ポケツト
領域、４０ａ，４１ａ……P-型不純物領域、４
０ｂ，４１ｂ……P+型不純物領域、４０，４１
……ソース、ドレイン領域、４２……Ｎ型ポケツ
ト領域、４３……CVD酸化膜、４４……Al配線、
５１……Ｎ型不純物領域、５２……N-型不純物
領域、５３……N+型不純物領域。
FIGS. 1a to 1g are cross-sectional views showing a conventional CMOS manufacturing method, FIGS. FIG. 3 is an explanatory diagram of N-type source and drain regions formed in an example. 21... P type silicon substrate, 22... N type well region, 23... Field oxide film, 24... Gate oxide film, 25 1 , 25 2 ... Gate electrode, 26
...Thermal oxide film (first film), 27... Polycrystalline silicon film (second film), 27'... Remaining polycrystalline silicon film, 28... Thermal oxide film (third film), 2
8'...Remaining thermal oxide film, 29, 33...Photoresist pattern, 30, 31, 36...Phosphorus ion implantation layer, 32, 34, 35...Boron ion implantation layer, 37a, 38a...N - type impurity region , 37
b, 38b...N + type impurity region, 37, 38...
...Source, drain region, 39...P type pocket region, 40a, 41a...P - type impurity region, 4
0b, 41b...P + type impurity region, 40, 41
... Source, drain region, 42 ... N-type pocket region, 43 ... CVD oxide film, 44 ... Al wiring,
51...N-type impurity region, 52...N - type impurity region, 53...N + -type impurity region.
Claims (1)
の素子領域及び第２導電型の第２の素子領域を形
成する工程と、該第１及び第２の素子領域上にそ
れぞれゲート絶縁膜を介してゲート電極を形成す
る工程と、少なくとも各素子領域上のゲート電極
表面及び露出した各素子領域表面に第１の被膜を
形成する工程と、全面に第２の被膜を堆積し、更
に該第２の被膜上に第３の被膜を堆積する工程
と、該第３の被膜を異方性エツチングによりエツ
チングし、前記第２の被膜の段差部の側面にのみ
第３の被膜を残存させる工程と、残存した第３の
被膜をマスクとして前記第２の被膜を異方性エツ
チングによりエツチングし、前記ゲート電極の側
壁に前記第１の被膜を介して第２の被膜を残存さ
せる工程と、第１の素子領域上のゲート電極及び
その側壁に残存した第２の被膜をマスクとして第
１の素子領域に選択的に第２導電型の不純物を高
ドーズ量でイオン注入する工程と、第１の素子領
域上のゲート電極側壁に残存した第２の被膜を除
去した後、このゲート電極をマスクとして利用し
第１の素子領域に選択的に第２導電型の不純物を
低ドーズ量でイオン注入し、更に第１導電型の不
純物を第２導電型不純物の低ドーズイオン注入よ
りも深くイオン注入する工程と、第２の素子領域
上のゲート電極及びその側壁に残存した第２の被
膜をマスクとして利用し第２の素子領域に選択的
に第１導電型の不純物を高ドーズ量でイオン注入
する工程と、第２の素子領域上のゲート電極側壁
に残存した第２の被膜を除去した後、このゲート
電極をマスクとして利用し第２の素子領域に選択
的に第１導電型の不純物を低ドーズ量でイオン注
入し、更に第２導電型の不純物を第１導電型不純
物の低ドーズイオン注入よりも深くイオン注入す
る工程と、熱処理により不純物を活性化させ、第
１の素子領域にゲート電極近傍の低濃度不純物領
域とこれらの領域に隣接する高濃度不純物領域と
からなる第２導電型のソース、ドレイン領域及び
前記低濃度不純物領域の下部に接する第１導電型
の不純物領域を、第２の素子領域にゲート電極近
傍の低濃度不純物領域とこれらの領域に隣接する
高濃度不純物領域とからなる第１導電型のソー
ス、ドレイン領域及び前記低濃度不純物領域の下
部に接する第２導電型の不純物領域をそれぞれ形
成する工程とを具備したことを特徴とする半導体
装置の製造方法。 ２ 第１の被膜がシリコン酸化膜又はシリコン窒
化膜である特許請求の範囲第１項記載の半導体装
置の製造方法。 ３ 第２の被膜が非単結晶シリコン膜又はシリコ
ン窒化膜である特許請求の範囲第１項記載の半導
体装置の製造方法。 ４ 第３の被膜がシリコン酸化膜、シリコン窒化
膜、アルミニウム膜又はモリブデン膜である特許
請求の範囲第１項記載の半導体装置の製造方法。 ５ 第１の被膜の膜厚が100〜1000Å、第２の被
膜の膜厚が0.1〜1μｍ、第３の被膜の膜厚が100〜
1000Åである特許請求の範囲第１項記載の半導体
装置の製造方法。 ６ 第２導電型不純物の低ドーズイオン注入又は
第１導電型不純物の低ドーズイオン注入に拡散係
数の大きい不純物と拡散係数の小さい不純物の２
種の不純物を用いる特許請求の範囲第１項記載の
半導体装置の製造方法。[Claims] 1. A semiconductor substrate of a first conductivity type, a first semiconductor substrate of a first conductivity type;
a step of forming an element region and a second element region of a second conductivity type; a step of forming a gate electrode on each of the first and second element regions via a gate insulating film; and at least each element region. a step of forming a first film on the upper gate electrode surface and the exposed surface of each element region; a step of depositing a second film on the entire surface; and a step of depositing a third film on the second film. , etching the third film by anisotropic etching to leave the third film only on the side surface of the stepped portion of the second film; and etching the third film using the remaining third film as a mask. etching the film by anisotropic etching to leave a second film on the sidewalls of the gate electrode via the first film; A process of selectively ion-implanting impurities of the second conductivity type into the first element region at a high dose using the film No. 2 as a mask, and removing the second film remaining on the side walls of the gate electrode on the first element region. After removing the gate electrode, using this gate electrode as a mask, ions of a second conductivity type impurity are selectively implanted into the first element region at a low dose, and the first conductivity type impurity is further implanted into a second conductivity type impurity. A step of implanting ions deeper than low-dose ion implantation, and selectively injecting the first conductivity type into the second device region using the second film remaining on the gate electrode and its sidewalls as a mask. After the process of ion-implanting impurities at a high dose and removing the second film remaining on the sidewalls of the gate electrode on the second device region, this gate electrode is used as a mask to select the second device region. The first conductivity type impurity is ion-implanted at a low dose, and the second conductivity type impurity is further ion-implanted deeper than the low-dose ion implantation of the first conductivity type impurity, and the impurity is activated by heat treatment. and a second conductivity type source and drain region consisting of a low concentration impurity region near the gate electrode and a high concentration impurity region adjacent to these regions, and a second conductivity type source and drain region in contact with the lower part of the low concentration impurity region in the first device region. a first conductivity type impurity region, and a first conductivity type source and drain region consisting of a low concentration impurity region near the gate electrode and a high concentration impurity region adjacent to these regions, and the low concentration impurity region in the second element region. 1. A method of manufacturing a semiconductor device, comprising the step of forming impurity regions of a second conductivity type in contact with the lower portions of the regions. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first film is a silicon oxide film or a silicon nitride film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the second film is a non-single crystal silicon film or a silicon nitride film. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the third film is a silicon oxide film, a silicon nitride film, an aluminum film, or a molybdenum film. 5 The thickness of the first coating is 100 to 1000 Å, the thickness of the second coating is 0.1 to 1 μm, and the thickness of the third coating is 100 to 1000 Å.
A method for manufacturing a semiconductor device according to claim 1, wherein the thickness is 1000 Å. 6 Low-dose ion implantation of second conductivity type impurities or low-dose ion implantation of first conductivity type impurities with impurities with a large diffusion coefficient and impurities with a small diffusion coefficient.
2. A method of manufacturing a semiconductor device according to claim 1, using seed impurities.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59050004A JPS60193371A (en) | 1984-03-15 | 1984-03-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59050004A JPS60193371A (en) | 1984-03-15 | 1984-03-15 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60193371A JPS60193371A (en) | 1985-10-01 |
| JPH0147016B2 true JPH0147016B2 (en) | 1989-10-12 |
Family
ID=12846851
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59050004A Granted JPS60193371A (en) | 1984-03-15 | 1984-03-15 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60193371A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4843023A (en) * | 1985-09-25 | 1989-06-27 | Hewlett-Packard Company | Process for forming lightly-doped-drain (LDD) without extra masking steps |
| US4722909A (en) * | 1985-09-26 | 1988-02-02 | Motorola, Inc. | Removable sidewall spacer for lightly doped drain formation using two mask levels |
| US4703551A (en) * | 1986-01-24 | 1987-11-03 | Ncr Corporation | Process for forming LDD MOS/CMOS structures |
| JPS62190862A (en) * | 1986-02-18 | 1987-08-21 | Matsushita Electronics Corp | Manufacture of complementary mos integrated circuit |
| US4728617A (en) * | 1986-11-04 | 1988-03-01 | Intel Corporation | Method of fabricating a MOSFET with graded source and drain regions |
| JPS63252461A (en) * | 1987-04-09 | 1988-10-19 | Nec Corp | Manufacture of cmos type semiconductor device |
| JP2004014941A (en) * | 2002-06-10 | 2004-01-15 | Nec Corp | Semiconductor device, circuit using the same and manufacturing method for semiconductor device |
-
1984
- 1984-03-15 JP JP59050004A patent/JPS60193371A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60193371A (en) | 1985-10-01 |
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