JPH0139236B2 - - Google Patents
Info
- Publication number
- JPH0139236B2 JPH0139236B2 JP54138342A JP13834279A JPH0139236B2 JP H0139236 B2 JPH0139236 B2 JP H0139236B2 JP 54138342 A JP54138342 A JP 54138342A JP 13834279 A JP13834279 A JP 13834279A JP H0139236 B2 JPH0139236 B2 JP H0139236B2
- Authority
- JP
- Japan
- Prior art keywords
- plating
- photoresist
- layer
- pattern
- noble metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000007747 plating Methods 0.000 claims description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- 229910000510 noble metal Inorganic materials 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 10
- 239000010409 thin film Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 5
- 239000010970 precious metal Substances 0.000 claims description 5
- 238000010304 firing Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 31
- 239000010931 gold Substances 0.000 description 18
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 16
- 229910052737 gold Inorganic materials 0.000 description 16
- 239000010408 film Substances 0.000 description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 239000012790 adhesive layer Substances 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- UOCLXMDMGBRAIB-UHFFFAOYSA-N 1,1,1-trichloroethane Chemical compound CC(Cl)(Cl)Cl UOCLXMDMGBRAIB-UHFFFAOYSA-N 0.000 description 1
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
本発明は高密度多層基板の製造方法に関し、特
にコンピユータまたは電子交換機等を用いるIC、
LSIまたは超LSI等の集積回路実装用の高密度な
耐熱性多層回路基板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a high-density multilayer board, and in particular to a method for manufacturing a high-density multilayer board, particularly an IC using a computer or an electronic exchange, etc.
This article relates to a method for manufacturing a high-density heat-resistant multilayer circuit board for mounting integrated circuits such as LSI or VLSI.
従来の多層基板の製造は、厚膜による製造方法
または薄膜による製造方法により行なつている。
厚膜による多層回路基板の製造の場合、厚膜ペー
ストをスクリーン印刷するため、100μ（ミクロ
ン）以下のパターンおよび一辺が250μ以下の方
形のヴイアホールを有する多層基板を形成するこ
とは非常にむずかしい。一方、薄膜による多層回
路基板の製造の場合、特にヴイアフイルの形成に
おいて、このヴイア高さをメツキ等で50μ以上に
し、一辺が100μ以下の方形にすると高さに対す
る密着面積が小さいため、フオトレジストを溶剤
等で剥離する時ヴイア部も同時に剥離してししま
うという欠点がある。さらにパターン幅は50μ以
下となると絶縁層の表面の粗さ等の関係で形成が
困難となる。このように通常の薄膜とメツキを利
用した方法でパターン幅30μ以下、方形のヴイア
サイズの一辺が100μ以下の多層基板を形成する
ことはむずかしい。 Conventional multilayer substrates have been manufactured using a thick film manufacturing method or a thin film manufacturing method.
In the case of manufacturing multilayer circuit boards using thick films, thick film paste is screen printed, so it is extremely difficult to form a multilayer board with a pattern of 100μ (microns) or less and a rectangular via hole with a side of 250μ or less. On the other hand, in the case of manufacturing multilayer circuit boards using thin films, especially when forming a via film, if the height of the via is set to 50μ or more using plating, etc., and the via is made into a rectangular shape with a side of 100μ or less, the adhesion area is small relative to the height, so photoresist is not used. There is a drawback that when peeling with a solvent or the like, the via portion is also peeled off at the same time. Further, if the pattern width is less than 50 μm, it becomes difficult to form the pattern due to the roughness of the surface of the insulating layer. In this way, it is difficult to form a multilayer substrate with a pattern width of 30 μm or less and a rectangular via size of 100 μm or less on a side using a method using ordinary thin films and plating.
本発明の目的は上述の欠点を除去しパターン幅
30μ以下一辺がヴイアサイズ100μ以下の方形の高
密度耐熱性多層回路基板の製造方法を提供するこ
とにある。 The object of the present invention is to eliminate the above-mentioned drawbacks and improve pattern width.
An object of the present invention is to provide a method for manufacturing a rectangular high-density heat-resistant multilayer circuit board with a diameter of 30μ or less and a side diameter of 100μ or less.
この発明では、パターン属およびヴイア部を薄
膜およびメツキにより、絶縁層は厚膜によりそれ
ぞれ形成している。特に、薄膜とメツキのための
フオトレジストとを焼成することにより酸化また
は焼却し、次に、不必要な金属薄膜部分をエツチ
ングで除去している。このため、ヴイア部の剥離
もなく一辺が100μ以下の方形の形成が可能とな
る。次に絶縁層の表面研磨もしくはエツチング表
面の粗さ良好に制御することができるため30μ以
下のパターンの形成も可能となる。 In this invention, the pattern element and the via portion are formed by a thin film and plating, and the insulating layer is formed by a thick film. In particular, the thin film and the photoresist for plating are oxidized or incinerated by firing, and then unnecessary portions of the metal thin film are removed by etching. Therefore, it is possible to form a rectangular shape with one side of 100 μm or less without peeling of the via portion. Next, since the roughness of the surface of the insulating layer can be well controlled by polishing or etching, it is possible to form a pattern with a diameter of 30 μm or less.
この発明の製造方法は、耐熱性絶縁基板の上表
面に薄膜金属層を少なくとも１層形成する工程
と、該薄膜金属層上にフオトレジストを塗布し露
光し現像して所定のパターンを形成する工程と、
該所定のパターンに貴金属メツキをする工程と、
前記フオトレジストと貴金属メツキ上に二回目の
フオトレジストを塗布露光現像し所定のヴイアを
形成したあと所定のヴイア部に貴金属メツキする
工程と、前記耐熱性絶縁基板を焼成しフオトレジ
ストを除去する工程と、前記貴金属メツキ以外の
前記薄膜金属層をエツチングで除去する工程と、
前記耐熱性絶縁基板上表面および貴金属メツキを
覆うようにアルミナおよびガラス等からなる絶縁
層を塗布し焼成する工程と、該絶縁層の上表面を
研磨除去し前記貴金属メツキの所定のヴイア部を
露出する工程と少なくとも１回繰り返すことを特
徴としている。 The manufacturing method of the present invention includes the steps of forming at least one thin metal layer on the upper surface of a heat-resistant insulating substrate, and applying a photoresist on the thin metal layer, exposing and developing it to form a predetermined pattern. and,
plating the predetermined pattern with precious metal;
A step of applying a second photoresist on the photoresist and precious metal plating, exposing and developing it to form a predetermined via, and then plating the predetermined via portion with a noble metal; and a step of baking the heat-resistant insulating substrate and removing the photoresist. and a step of removing the thin film metal layer other than the noble metal plating by etching,
A step of applying and firing an insulating layer made of alumina, glass, etc. to cover the upper surface of the heat-resistant insulating substrate and the noble metal plating, and polishing away the upper surface of the insulating layer to expose a predetermined via portion of the noble metal plating. The process is repeated at least once.
次に図面を参照して本発明を詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.
第１図から第９図は本発明の一実施例を示す図
である。第１図では、所望の寸法精度を有するア
ルミナ（Al2O397ｇ）磁気基板１上にチタン
（Ti）またはタングステン（Ｗ）等の金属密着層
２が蒸着またはスパツタリングで1000Å（オング
ストロング）〜2000Åの厚さで形成されている。
さらに、その上表面にメツキ下地およびメツキ電
源のための貴金属層３（パラジウムPdまた白金
Pt）が蒸着またはスパツタリングで1000Å〜
2000Åの厚さで形成されている。 1 to 9 are views showing one embodiment of the present invention. In Fig. 1, a metal adhesion layer 2 of titanium (Ti) or tungsten (W), etc., is deposited by vapor deposition or sputtering on an alumina (Al 2 O 3 97 g) magnetic substrate 1 having a desired dimensional accuracy, and is deposited to a thickness of 1000 Å (angstrong) to It is formed with a thickness of 2000 Å.
Furthermore, on the upper surface, a noble metal layer 3 (palladium Pd or platinum
Pt) is deposited or sputtered to 1000Å~
It is formed with a thickness of 2000 Å.
第２図ではフオトレジスト４が貴金属層３の上
表面にコーテイングされたあと、図示していない
所定のガラスマスクを利用して露光し、さらにス
プレー現像した状態を示す。ここで、フオトレジ
スト４は通常ドライフイルムと呼ばれる10μ以上
のフイルムタイプレジストを使用し、現像液はク
ロロセン（1.1.1トリクロロエタン）が用いられ
る。 FIG. 2 shows a state in which the photoresist 4 is coated on the upper surface of the noble metal layer 3, exposed to light using a predetermined glass mask (not shown), and further developed by spraying. Here, as the photoresist 4, a film type resist of 10 μm or more, usually called dry film, is used, and as the developer, chlorocene (1.1.1 trichloroethane) is used.
次に現像で除去された部分に電解メツキにより
金（Au）パターン５を第３図のごとく形成する。
このとき、貴金属層３は電解Auメツキの電極層
となつており、また、金メツキパターン５の厚さ
は７〜8μパターン幅は30μである。 Next, a gold (Au) pattern 5 is formed by electrolytic plating on the portion removed by development, as shown in FIG.
At this time, the noble metal layer 3 serves as an electrode layer for electrolytic Au plating, and the gold plating pattern 5 has a thickness of 7 to 8 μm and a pattern width of 30 μm.
第４図に示す工程においては、上層パターンと
の接続のために２回目のフオトレジスト６が１回
目のフオトレジスト４と金パターン５の上層にコ
ーテイングされたあとで所定のガラスマスクによ
り露光現像され、さらに、一回目のメツキと同じ
く、貴金属層を電極とした電解金メツキを金パタ
ーン５上にかけることによりヴイア７を形成して
いる。ここで、ヴイア７の金メツキの厚さは50μ
以上ヴイアサイズは一辺が100μの方形で形成さ
れている。 In the process shown in FIG. 4, after the second photoresist 6 is coated on the first photoresist 4 and the gold pattern 5 for connection with the upper layer pattern, it is exposed and developed using a predetermined glass mask. Furthermore, as in the first plating, vias 7 are formed by applying electrolytic gold plating using the noble metal layer as an electrode on the gold pattern 5. Here, the thickness of the gold plating on Via 7 is 50μ
The Via size is formed by a square with each side of 100μ.
第５図は前工程の基板を900℃〜1000℃の空気
雰囲気炉に介して焼成した状態を示す。ここで、
前記フオトレジスト４とフオトレジスト６とは、
高温で焼却されかつ金パターン５の下層部の貴金
属層３と密着層２とは金パターン５およびアルミ
ナ磁器基板１に拡散または酸化し金パターン５の
密着を強固にする。また、金パターン５以外の貴
金属層３と密着層２とは拡散すると同時に密着層
２は完全に酸化される。 FIG. 5 shows the state in which the substrate in the previous step was fired in an air atmosphere furnace at 900°C to 1000°C. here,
The photoresist 4 and the photoresist 6 are:
The noble metal layer 3 and adhesion layer 2 which are incinerated at high temperature and under the gold pattern 5 are diffused or oxidized into the gold pattern 5 and the alumina ceramic substrate 1 to strengthen the adhesion of the gold pattern 5. Furthermore, the noble metal layer 3 other than the gold pattern 5 and the adhesive layer 2 are diffused, and at the same time, the adhesive layer 2 is completely oxidized.
第６図に示すように、貴金属層３（パラジウム
Pdまたは白金Pt）をエツチング除去する。ここ
で、第１パターン層（金パターン５）と第１ヴイ
ア層（ヴイア７）とが完成する。このとき、密着
層２は酸化されており絶縁体となつている。 As shown in FIG. 6, the noble metal layer 3 (palladium
Remove Pd or platinum (Pt) by etching. Here, the first pattern layer (gold pattern 5) and the first via layer (via 7) are completed. At this time, the adhesive layer 2 is oxidized and becomes an insulator.
第７図は前記金パターン５とヴイア７との上表
面に、さらにアルミナ、ガラスおよび結晶化ガラ
ス等からなる絶縁ペーストを全面にスクリーン印
刷し、さらに、900℃〜1000℃で空気雰囲気焼成
して、絶縁層８を形成した状態と示す。ここで、
絶縁層８の厚さは60μ以上になつている。 FIG. 7 shows that an insulating paste made of alumina, glass, crystallized glass, etc. is screen printed on the entire surface of the gold pattern 5 and the via 7, and then fired in an air atmosphere at 900°C to 1000°C. , a state in which an insulating layer 8 is formed is shown. here,
The thickness of the insulating layer 8 is 60μ or more.
第８図に示す工程では、研磨盤を使用し前記絶
縁層８を20〜30μラツピング研磨して、ヴイア７
の金接続部分を露出させる。 In the process shown in FIG.
expose the gold connections.
第９図は第１図から第８図までの工程をさらに
繰り返して多層化した断面図を示す。ここで、参
照数字２′は密着層、５′は金パターン、７′はヴ
イア、８′は絶縁層を示している。このようにし
て、本発明を利用した導体２層構成の高密度多層
基板が完成する。 FIG. 9 shows a cross-sectional view of a multi-layer structure obtained by repeating the steps from FIG. 1 to FIG. 8. Here, reference numeral 2' indicates an adhesion layer, 5' indicates a gold pattern, 7' indicates a via, and 8' indicates an insulating layer. In this way, a high-density multilayer board with a two-layer conductor structure using the present invention is completed.
本発明には、フオトレジストとメツキとを繰り
返して金パターンとヴイアとを形成し、焼成して
フオトレジストを除去したあとで不要薄膜をエツ
チングすることと、絶縁層の研磨工程との組み合
せにより微細パターンおよび微少ヴイアを高精度
かつ高密度に形成できるという効果がある。 In the present invention, a gold pattern and vias are formed by repeating photoresist and plating, and after the photoresist is removed by firing, unnecessary thin films are etched, and an insulating layer polishing process is combined to form a fine pattern. This has the effect that patterns and minute vias can be formed with high precision and high density.
第１図から第９図まではそれぞれ本発明の一実
施例を示す図である。
第１図から第９図において、１……アルミナ磁
気基板、２，２′……密着層、３……貴金属層、
４，６……フオトレジスト、５，５′……金パタ
ーン、７，７′……ヴイア、８，８′……絶縁層。
FIG. 1 to FIG. 9 are diagrams each showing an embodiment of the present invention. In FIGS. 1 to 9, 1...Alumina magnetic substrate, 2, 2'...Adhesion layer, 3...Precious metal layer,
4, 6... Photoresist, 5, 5'... Gold pattern, 7, 7'... Via, 8, 8'... Insulating layer.
Claims (1)
くとも１層形成する第１の工程と、 該薄膜金属層上にフオトレジストを塗布し露光
し現像して所定のパターンを形成する第２の工程
と、 該所定のパターンに貴金属メツキをする第３の
工程と、 前記フオトレジストと貴金属メツキ上に２回目
のフオトレジストを塗布露光現像し所定のヴイア
を形成したあと所定ヴイア部に貴金属メツキをす
る第４の工程と、 前記耐熱性絶縁基板を焼成しフオトレジストを
除去する第５の工程と、 前記貴金属メツキ以外の前記薄膜金属層をエツ
チング除去する第６の工程と、 前記耐熱性絶縁基板上表面および貴金属メツキ
を覆うように絶縁層を塗布し焼成する第７の工程
と、 該絶縁層の上表面を研磨除去し前記貴金属メツ
キの所定ヴイア部を露出する第８の工程とを少な
くとも１回繰り返すことを特徴とする高密度多層
基板の製造方法。[Claims] 1. A first step of forming at least one thin metal layer on the upper surface of a heat-resistant insulating substrate, and applying a photoresist on the thin metal layer, exposing and developing it to form a predetermined pattern. a second step of forming a predetermined pattern; a third step of plating the predetermined pattern with a precious metal; and coating the photoresist and the precious metal plating with a second photoresist, exposing and developing the photoresist to form a predetermined via, and then plating the predetermined via. a fourth step of plating the heat-resistant insulating substrate with a noble metal; a fifth step of removing the photoresist by baking the heat-resistant insulating substrate; a sixth step of etching away the thin film metal layer other than the noble metal plating; a seventh step of applying and firing an insulating layer to cover the upper surface of the heat-resistant insulating substrate and the noble metal plating; and an eighth step of polishing and removing the upper surface of the insulating layer to expose a predetermined via portion of the noble metal plating. A method for manufacturing a high-density multilayer substrate, the method comprising repeating the steps at least once.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13834279A JPS5662398A (en) | 1979-10-26 | 1979-10-26 | Method of manufacturing high density multilayer board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13834279A JPS5662398A (en) | 1979-10-26 | 1979-10-26 | Method of manufacturing high density multilayer board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5662398A JPS5662398A (en) | 1981-05-28 |
| JPH0139236B2 true JPH0139236B2 (en) | 1989-08-18 |
Family
ID=15219669
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13834279A Granted JPS5662398A (en) | 1979-10-26 | 1979-10-26 | Method of manufacturing high density multilayer board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5662398A (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58119694A (en) * | 1982-01-12 | 1983-07-16 | 株式会社日立製作所 | Method of producing circuit board |
| JPS58121698A (en) * | 1982-01-12 | 1983-07-20 | 株式会社日立製作所 | Multilayer printed board |
| JPS58128797A (en) * | 1982-01-27 | 1983-08-01 | 日本電気株式会社 | Method of producing multilayer ceramic board |
| JPH0695543B2 (en) * | 1984-09-26 | 1994-11-24 | 株式会社日立製作所 | Semiconductor device and manufacturing method thereof |
| JPS61121392A (en) * | 1984-11-19 | 1986-06-09 | 日本電信電話株式会社 | Manufacture of multilayer wiring |
| JPS649694A (en) * | 1987-07-01 | 1989-01-12 | Toyo Giken Kogyo Kk | Multilayer interconnection circuit board and manufacture thereof |
| JP2001007529A (en) * | 1999-06-23 | 2001-01-12 | Ibiden Co Ltd | Multilayer printed wiring board and its manufacture, and semiconductor chip and its manufacture |
| JP5455116B2 (en) * | 2009-10-24 | 2014-03-26 | 京セラＳｌｃテクノロジー株式会社 | Wiring board and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5064767A (en) * | 1973-10-12 | 1975-06-02 | ||
| JPS51145853A (en) * | 1975-06-10 | 1976-12-15 | Nippon Electric Co | Method of fabricating ceramic membrane |
| JPS5346666A (en) * | 1976-10-07 | 1978-04-26 | Nippon Electric Co | Method of producing multilayer circuit substrate |
| JPS5392465A (en) * | 1977-01-24 | 1978-08-14 | Nippon Electric Co | Electronic circuit element board |
-
1979
- 1979-10-26 JP JP13834279A patent/JPS5662398A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5064767A (en) * | 1973-10-12 | 1975-06-02 | ||
| JPS51145853A (en) * | 1975-06-10 | 1976-12-15 | Nippon Electric Co | Method of fabricating ceramic membrane |
| JPS5346666A (en) * | 1976-10-07 | 1978-04-26 | Nippon Electric Co | Method of producing multilayer circuit substrate |
| JPS5392465A (en) * | 1977-01-24 | 1978-08-14 | Nippon Electric Co | Electronic circuit element board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5662398A (en) | 1981-05-28 |
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