JPH0136266B2 - - Google Patents
Info
- Publication number
- JPH0136266B2 JPH0136266B2 JP56129748A JP12974881A JPH0136266B2 JP H0136266 B2 JPH0136266 B2 JP H0136266B2 JP 56129748 A JP56129748 A JP 56129748A JP 12974881 A JP12974881 A JP 12974881A JP H0136266 B2 JPH0136266 B2 JP H0136266B2
- Authority
- JP
- Japan
- Prior art keywords
- light
- pnpn
- gate
- semiconductor substrate
- anode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000000926 separation method Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000002996 emotional effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000012885 constant function Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Thyristors (AREA)
- Light Receiving Elements (AREA)
Description
【発明の詳細な説明】
本発明は1個のLED(発光ダイオード)で1個
の半導体基板内に組み込まれた4個のPNPN素
子を駆動する光結合形PNPNスイツチに関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an optically coupled PNPN switch that uses one LED (light emitting diode) to drive four PNPN elements built into one semiconductor substrate.
一般に、電子化ボタン電話装置、電子化PBX
など回線の切替を要する装置の通話路切替スイツ
チには、スイツチングと同時に極性の一定化機能
が要求される。第1図は、この目的を達成するた
めに従来提案されているPNPN素子のブリツジ
接続回路である。第1図においてのは電話回
線、1はPNPN素子、2は交叉点回路、3は電
話回線抵抗、4は局電源、5は電話端未である。
通話路スイツチは駆動回路が電気的に分離されて
いる方が望まし第1図においてもPNPN素子は
光結合による駆動が適している。しかし、この回
路は1交叉点に4つのPNPN素子を使用するた
め、これらを個別ホトカプラで構成した場合には
装置は大型化し、スイツチ駆動電力は増加し、電
子化の利点は生かせない。そこで、1交叉点回路
を1個のホトカプラで構成する検討が重要にな
る。しかし、これには解決すべき大きな問題点が
ある。以下にそれを述べる。 Generally, electronic button telephone equipment, electronic PBX
A communication path changeover switch for a device that requires line switching, such as a telephone line, is required to have a polarity constant function at the same time as switching. FIG. 1 shows a bridge connection circuit for PNPN elements that has been proposed to achieve this objective. In FIG. 1, reference numeral 1 is a telephone line, 1 is a PNPN element, 2 is a cross-point circuit, 3 is a telephone line resistance, 4 is a station power supply, and 5 is a telephone terminal.
It is preferable that the drive circuit of the communication path switch is electrically separated, and as shown in FIG. 1, it is suitable to drive the PNPN element by optical coupling. However, since this circuit uses four PNPN elements at one intersection point, if these were constructed using individual photocouplers, the device would become larger, the switch driving power would increase, and the advantages of computerization would not be utilized. Therefore, it is important to consider configuring one cross-point circuit with one photocoupler. However, there are major problems that need to be resolved. I will explain it below.
(i) 第1図の回路で交叉点が動作し、太い実線
のように電流が流れている場合、PNPN素子
6,9は順方向ゆえ動作状態にあるが、
PNPN素子7,8は逆方向ゆえ不動作状態に
あり4の直流電圧が印加されている。従つて
7,8は光が照射されていても逆方向に十分な
耐圧が必要である。また、4の極性が逆になれ
ば6,9に同様に耐圧が要求される。従つて、
6,7,8,9は各々電気的に絶縁分離されて
おり、光照射時においても十分な耐圧があるこ
と。(i) In the circuit shown in Fig. 1, when the crossing point operates and current flows as shown by the thick solid line, the PNPN elements 6 and 9 are in the operating state because they are in the forward direction.
Since the PNPN elements 7 and 8 are in opposite directions, they are in an inactive state and a DC voltage of 4 is applied thereto. Therefore, even if 7 and 8 are irradiated with light, sufficient withstand voltage is required in the opposite direction. Moreover, if the polarity of 4 is reversed, voltage resistance is similarly required for 6 and 9. Therefore,
6, 7, 8, and 9 are electrically isolated from each other and have sufficient withstand voltage even when irradiated with light.
(ii) ブリツジ交叉点ではつねに2つのPNPN素
子に逆方向に電圧が印加される。LEDの光は
これら逆方向PNPN素子にも照射されるため
破線のように光もれ電流が流れることになる。
この光もれ電流は約0.3dB/mAで通話損失を
もたらすのでこれを極力低減化すること。(ii) At the bridge crossing point, voltages are always applied to the two PNPN elements in opposite directions. Since the LED light is also applied to these reverse direction PNPN elements, a light leakage current flows as shown by the broken line.
This light leakage current causes call loss at approximately 0.3 dB/mA, so this should be reduced as much as possible.
(iii) 4つのPNPN素子の各ゲート接合に発光体
からの光が効率良く照射される対向構造である
こと。(iii) The facing structure allows light from the light emitter to be efficiently irradiated to each gate junction of the four PNPN elements.
(iv) PNPN素子は順方向に立上りの早い電圧が
印加されると誤点弧する特性(dv/pt特性)
がある。そこで、dv/dt耐量を向上するため
ゲート・カソード間に抵抗RGKを挿入すること
が多い。しかし、この抵抗値はPNPN素子の
感動値と相反する関係にあり抵抗値が小さくな
ると感動しにくくなる。一方、抵抗体は光が当
たると低くなるものが多い。そこで、感動特性
を悪くしないためには、RGKに光が当たらない
構造にすること。(iv) The PNPN element has the characteristic of erroneous firing when a voltage that rises quickly in the forward direction is applied (dv/pt characteristic)
There is. Therefore, a resistor R GK is often inserted between the gate and cathode to improve dv/dt tolerance. However, this resistance value has a contradictory relationship with the emotional value of the PNPN element, and as the resistance value decreases, it becomes difficult to be impressed. On the other hand, many resistors become weaker when exposed to light. Therefore, in order to not deteriorate the emotional characteristics, it is necessary to create a structure that prevents light from hitting the R GK .
などを解決する必要がある。etc. need to be resolved.
本発明は前記問題点を解決するために、半導体
基板を十字形の分離帯により4つに絶縁分離し、
分離された各部分にラテラル形PNPN素子を、
各ゲート領域が十字の交点近くに集まるように、
かつ陽極領域がゲート領域の外側をとりまくよう
に形成し、発光体には光照射に指向性をもたせた
4つのゲート接合に集中的に光を照射し、陽極接
合には光の照射を少なくするように対向させたも
のである。以下図面を用いて説明する。 In order to solve the above-mentioned problems, the present invention insulates and separates a semiconductor substrate into four parts by a cross-shaped separation band,
Lateral type PNPN element in each separated part,
So that each gate area gathers near the intersection of the crosses,
In addition, the anode region is formed so as to surround the outside of the gate region, and the light irradiation is directed to the light emitter, and the four gate junctions are irradiated with light in a concentrated manner, while the anode junction is irradiated with less light. They are facing each other like this. This will be explained below using the drawings.
第2図は本発明の実施例で、第3図の1交叉点
回路に対応するものである。第2図において22
はスイツチチツプ、11はシリコンなどのN形半
導体基板、10は11を保持する基板で11と同
じ材質のものが適している。13は10と11を
絶縁分離する樹脂などの板、14はAlなどの陽
極電極、15は陰極電極、19は電極機能とスイ
ツチチツプをパツケージ固定する機能を果たすバ
ンプ電極、17はPNPN素子をブリツジ形に接
続する配線、18は4つのPNPN素子に同時に
光を照射するGaAsLEDなどの発光体、16はダ
イシングなどによつて11に切り込み各PNPN
素子を絶縁分離する溝、12は酸化シリコンなど
の絶縁被膜、A1〜A4はP形拡散層で構成される
陽極領域、K1〜K4はN形拡散層で構成される陰
極領域、G1〜G4はP形拡散層で構成される感光
性ゲート領域、RGK1〜RGK4はP形の拡散抵抗でゲ
ート・陰極間に接続されている。第4図は第2図
から14,15の電極パターンを取り除いたとき
の平面図である。第5図は第2図の断面図で第4
図の一点鎖線に対応する部分である。A1′,A2′は
陽極電極、K1′,K2′は陰極電極である。 FIG. 2 shows an embodiment of the present invention, which corresponds to the one-crossing point circuit shown in FIG. 22 in Figure 2
1 is a switch chip, 11 is an N-type semiconductor substrate such as silicon, and 10 is a substrate for holding 11, which is preferably made of the same material as 11. 13 is a plate made of resin or the like that insulates and separates 10 and 11, 14 is an anode electrode such as Al, 15 is a cathode electrode, 19 is a bump electrode that functions as an electrode and fixes the switch chip to the package, and 17 is a bridge type PNPN element. 18 is a light emitter such as GaAs LED that irradiates light to four PNPN elements at the same time, 16 is a light emitting device that is cut into 11 by dicing etc. and each PNPN
A groove for insulating and separating the elements, 12 an insulating film such as silicon oxide, A 1 to A 4 an anode region composed of a P-type diffusion layer, K 1 to K 4 a cathode region composed of an N-type diffusion layer, G 1 to G 4 are photosensitive gate regions composed of P-type diffusion layers, and R GK1 to R GK4 are P-type diffusion resistors connected between the gate and the cathode. FIG. 4 is a plan view when electrode patterns 14 and 15 are removed from FIG. 2. Figure 5 is a cross-sectional view of Figure 2.
This is the part corresponding to the dashed line in the figure. A 1 ′ and A 2 ′ are anode electrodes, and K 1 ′ and K 2 ′ are cathode electrodes.
以下に本実施例の特徴を述べる。 The features of this embodiment will be described below.
4個のPNPN素子を表面に形成した半導体基
板の裏面を13を介して10に接着後、半導体基
板表面を十字に切断し絶縁分離する。この方法は
簡単にかつ高耐圧に絶縁分離できる特徴がある。
18は、図のように光出射面を台形に切断するこ
とによつてレンズ化し、発光強度が半導体基板の
前記十字交点近傍で強くなるように指向性を持た
せてある。第4図に示す円内が光強度が強く、円
外は弱い。また、PNPN素子はラテラル構造と
し、ゲート領域を前記十字交点近傍に配し、第5
図19,20に示すゲート接合面近傍領域に光が
効率良く照射されるようにしてある。また、逆方
向に電圧が印加されたPNPN素子に流れる光も
れ電流を少なくするため、陽極はゲート領域の外
側をとり囲むように、すなわち、十字交点からの
陽極領域への距離はゲート領域のどの部分より遠
くなるようにし、陽極接合近傍への光の照射を少
なくしている。また、ゲートをとり囲むように陽
極を配することによつてPNPN素子動作時の陽
極・陰極間抵抗を小さくでき、順方向の電圧降下
を低減化できる。また、dv/dt耐量を向上させ
るためのゲート・カソード間抵抗はP形の拡散抵
抗で構成するが、照射光の影響を受けないように
ゲート領域から十分離れた光が当らない位置に配
してある。 After bonding the back side of a semiconductor substrate on which four PNPN elements are formed to 10 via 13, the surface of the semiconductor substrate is cut in a cross shape to isolate the semiconductor substrate. This method is characterized by simple insulation and isolation with high voltage resistance.
Reference numeral 18 is formed into a lens by cutting the light emitting surface into a trapezoid as shown in the figure, and is made to have directivity so that the light emission intensity becomes strong near the cross intersection of the semiconductor substrate. The light intensity is strong inside the circle shown in FIG. 4, and weak outside the circle. Further, the PNPN element has a lateral structure, and the gate region is arranged near the cross intersection, and the fifth
Light is efficiently irradiated to the region near the gate junction surface shown in FIGS. 19 and 20. In addition, in order to reduce the light leakage current flowing through the PNPN element to which a voltage is applied in the opposite direction, the anode is arranged so as to surround the outside of the gate region, that is, the distance from the cross point to the anode region is It is placed farther away than any other part to reduce the irradiation of light to the vicinity of the anodic junction. Further, by arranging the anode to surround the gate, the resistance between the anode and the cathode during operation of the PNPN element can be reduced, and the voltage drop in the forward direction can be reduced. In addition, the resistance between the gate and cathode in order to improve the dv/dt withstand capability is composed of a P-type diffused resistance, but it is placed at a location far enough away from the gate area and out of the light to avoid being affected by the irradiation light. There is.
第6図はスイツチチツプの他の実施例である。
第6図において21は酸化シリコンなどの誘電体
膜である。この誘電体膜を用いた絶縁方法は製造
工程が複雑ではあるが、10,13を用いないの
で半導体基板が薄く、光の透過性が良い場合には
半導体基板の裏面から光を照射することもでき
る。裏面には電極パターンなどの光を遮るものは
ないのでゲート接合近傍に光を効率良く当てるこ
とができる。 FIG. 6 shows another embodiment of the switch chip.
In FIG. 6, 21 is a dielectric film such as silicon oxide. This insulation method using a dielectric film has a complicated manufacturing process, but since it does not use 10 and 13, if the semiconductor substrate is thin and has good light transmission, it is possible to irradiate light from the back side of the semiconductor substrate. can. Since there is nothing on the back surface that blocks light, such as an electrode pattern, light can be efficiently applied to the vicinity of the gate junction.
また、本発明では発光体の指向性を2つあるい
は4つにし、ゲート接合をより効率的に照射する
ことも可能である。 Further, in the present invention, it is also possible to use two or four directivity of the light emitters to more efficiently irradiate the gate junction.
第7,8図はそれぞれ、2つ、4つの指向性を
持たせるためのLEDの素子構造例である。第9
図aは発光体として、第7図のLEDを用いたス
イツチ実施例の平面図、図において23は第7図
のLED、24は23の光照射領域、第9図bは
光強度分布で斜線の内側が強くゲートを集中的に
照射する。また、斜線の外側は強度は弱く陽極領
域への照射は少ない。第10図aは第8図の
LEDを用いたスイツチ実施例の平面図、25は
第8図のLED、26は25の光照射領域、第1
0図bは光強度分布である。 Figures 7 and 8 show examples of LED element structures for providing two and four directivities, respectively. 9th
Figure a is a plan view of a switch embodiment using the LED shown in Figure 7 as a light emitting body, in the figure 23 is the LED shown in Figure 7, 24 is the light irradiation area of 23, and Figure 9 b is the light intensity distribution with diagonal lines. The inside of the gate is strongly illuminated. Further, the intensity is weaker outside the diagonal line, and the irradiation to the anode region is less. Figure 10a is the same as Figure 8.
A plan view of an embodiment of the switch using LEDs, 25 is the LED of FIG. 8, 26 is the light irradiation area of 25, and the first
Figure 0b shows the light intensity distribution.
以上説明したように本発明は
1LEDで絶縁分離された4つのPNPN素子を
駆動することができ経済化、高信頼化、駆動電
力の低減化が可能である。 As explained above, the present invention allows one LED to drive four isolated PNPN elements, making it possible to achieve economy, high reliability, and reduction in driving power.
陽極接合光が照射されにくく、従つて逆方向
光もれ電流は少なく低損失のスイツチが実現で
きる。 It is difficult to irradiate the anodic junction with light, so the reverse light leakage current is small, and a switch with low loss can be realized.
などの利点があるためボタン電話機、交換機の通
話路切替スイツチなどに利用できる。Because of these advantages, it can be used in key telephones, switchboards, etc.
第1図は従来の通話路スイツチ回路を示す図、
第2図は本発明の一実施例を示す斜視図、第3図
は本発明に係るスイツチチツプ1個の回路構成
図、第4図は第2図の電極パターンを除いたとき
の平面図、第5図は第2図の断面図、第6,7,
8,9,10図は本発明の他の実施例を説明する
図である。
1……PNPN素子、2……交叉点回路、3…
…電話線抵抗、4……局電源、5……電話端末、
,……電話回線、6,7,8,9……
PNPN素子、10……保持基板、11……半導
体基板、12……絶縁被膜、13……絶縁板、1
4……陽極電極、15……陰極電極、16……絶
縁溝、17……配線、18……発光体(LED)、
19……バンプ電極、20……ゲート近傍領域、
21……誘電体膜、22……スイツチチツプ、2
3……LED、24……LED光照射領域、25…
…LED、26……LED光照射領域。
FIG. 1 is a diagram showing a conventional communication path switch circuit.
FIG. 2 is a perspective view showing an embodiment of the present invention, FIG. 3 is a circuit diagram of one switch chip according to the present invention, FIG. 4 is a plan view with the electrode pattern of FIG. 2 removed, and FIG. Figure 5 is a sectional view of Figure 2, 6th, 7th,
Figures 8, 9, and 10 are diagrams for explaining other embodiments of the present invention. 1...PNPN element, 2...Cross point circuit, 3...
... Telephone line resistance, 4 ... Station power supply, 5 ... Telephone terminal,
,...Telephone line, 6, 7, 8, 9...
PNPN element, 10... Holding substrate, 11... Semiconductor substrate, 12... Insulating coating, 13... Insulating plate, 1
4...Anode electrode, 15...Cathode electrode, 16...Insulating groove, 17...Wiring, 18...Light emitter (LED),
19... Bump electrode, 20... Gate vicinity region,
21... Dielectric film, 22... Switch chip, 2
3...LED, 24...LED light irradiation area, 25...
...LED, 26...LED light irradiation area.
Claims (1)
る光結合形PNPNスイツチであつて、十字形の
分離帯で4つに絶縁分離された半導体基板の各々
の部分にラテラル形に形成され、各々の感光性ゲ
ート領域を前記十字の交点近傍に配し、陽極領域
を前記十字の交点から遠い領域にゲート領域を取
り囲むように配置した光駆動形PNPN素子と、 前記半導体基板に対向し、4つのゲート接合を
同時にかつ集中的に光を照射すると共に陽極接合
には光の照射を少なくするようにして、前記
PNPN素子を駆動し得る発光体とから成ること
を特徴とする光結合形PNPNスイツチ。[Scope of Claims] 1. An optically coupled PNPN switch that ignites a plurality of PNPN elements with one light source, in which each part of a semiconductor substrate is insulated and separated into four parts by a cross-shaped separation band. an optically driven PNPN element formed in the shape of a shape, with each photosensitive gate region disposed near the intersection of the crosses, and an anode region disposed in a region far from the intersection of the crosses so as to surround the gate region; and the semiconductor substrate. The four gate junctions are simultaneously and intensively irradiated with light while the anode junction is irradiated with less light.
An optically coupled PNPN switch comprising a light emitting body capable of driving a PNPN element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56129748A JPS5831571A (en) | 1981-08-19 | 1981-08-19 | Photocoupling type p-n-p-n switch |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56129748A JPS5831571A (en) | 1981-08-19 | 1981-08-19 | Photocoupling type p-n-p-n switch |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5831571A JPS5831571A (en) | 1983-02-24 |
JPH0136266B2 true JPH0136266B2 (en) | 1989-07-31 |
Family
ID=15017222
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56129748A Granted JPS5831571A (en) | 1981-08-19 | 1981-08-19 | Photocoupling type p-n-p-n switch |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5831571A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5468976A (en) * | 1993-08-27 | 1995-11-21 | Evseev; Yury | Semi conductor rectifying module |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50157081A (en) * | 1974-06-07 | 1975-12-18 |
-
1981
- 1981-08-19 JP JP56129748A patent/JPS5831571A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50157081A (en) * | 1974-06-07 | 1975-12-18 |
Also Published As
Publication number | Publication date |
---|---|
JPS5831571A (en) | 1983-02-24 |
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