JPH01316840A - Diagnosis control system - Google Patents

Diagnosis control system

Info

Publication number
JPH01316840A
JPH01316840A JP63149507A JP14950788A JPH01316840A JP H01316840 A JPH01316840 A JP H01316840A JP 63149507 A JP63149507 A JP 63149507A JP 14950788 A JP14950788 A JP 14950788A JP H01316840 A JPH01316840 A JP H01316840A
Authority
JP
Japan
Prior art keywords
processor
diagnosed
signal line
diagnosis
diagnostic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63149507A
Other languages
Japanese (ja)
Inventor
Mitsuhiro Suda
須田 充弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63149507A priority Critical patent/JPH01316840A/en
Publication of JPH01316840A publication Critical patent/JPH01316840A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To eliminate limitation for a memory accessible storage area by comprising a system so that built-in diagnosis using a storage part in a system controller can be feasible. CONSTITUTION:A diagnosis control part 10 in the system controller 1 informs state display to a bus control part 20 in a processor 2 to be diagnosed by using an address/write data signal line 30 and a bus control signal 33 so as to make access to storage area display 21 in the processor 2 to be diagnosed by the storage part 11 in the system controller 1. The bus control part 20 in the processor 2 to be diagnosed sets the information on the write data signal line 30 on the storage area display 21 by the above information. After that, the diagnosis control part 10 informs a diagnosis start-up request signal 23 to a processor part 22 in the processor 2 to be diagnosed by the address/write data signal line 30 and the bus control signal line 33 via the bus control part 20. The processor 2 to be diagnosed executes a diagnostic program by the diagnosis start-up request signal 23.

Description

【発明の詳細な説明】 産業−1二の利用分野 本発明は、診断制御方式に関し、特に、中央処理装置に
おけるプロセッサのオンライン組込み診断方式に関する
DETAILED DESCRIPTION OF THE INVENTION FIELD OF THE INVENTION The present invention relates to a diagnostic control method, and more particularly to an online built-in diagnostic method for a processor in a central processing unit.

従来の技術 システムがオンライン動作中に、プロセッサをシステム
に組込む前に該プロセッサの診断を自プロセッサにあら
かじめ組込まれたマイクロプログラムによる診断または
オペレージリンシステム下によ°る1つのシaブとして
該プロセッサの診断が実行される。
While the conventional technology system is in online operation, the processor is diagnosed by a microprogram pre-installed in the processor or as a single server under the operating system, before the processor is installed in the system. diagnostics are performed.

このような場合に、該診断プロセッサの主記憶装置への
アクセスに関して、システムはオンライン状態である以
上、システムへ固膏の記憶領域のアクセスを保護する必
要があり、例えばプロセ、。
In such a case, with regard to access to the main memory of the diagnostic processor, since the system is online, it is necessary to protect access to the storage area of the plaster, for example, the process.

す内の記憶保護機構において、あるいは主記憶装置内の
記憶保護機構において監視されていた。
storage protection mechanism within the main storage device or the storage protection mechanism within the main storage device.

第2図は従来におけるこの種の制御方式の一例を示すブ
ロック図である。
FIG. 2 is a block diagram showing an example of this type of conventional control system.

発明が解決しようとする課題 」−述した従来の診断制御方式は、該診断プロセッサの
メモリアクセスに対する記憶領域の保護をシステム構成
上から考慮する必要があり、かつ該診断プロセッサがメ
モリアクセス可能な記憶領域が制限されるという問題が
ある。
``Problems to be Solved by the Invention'' - The conventional diagnostic control method described above requires consideration of protection of storage areas against memory access by the diagnostic processor from the system configuration, and also requires consideration of protection of storage areas from memory access by the diagnostic processor. There is a problem that the area is limited.

本発明は従来の上記実情に鑑みてなされたものであり、
従って本発明の目的は、従来の技術に内在する上記課題
を解決することを可能とした新規な診断制御方式を提供
することにある。
The present invention has been made in view of the above-mentioned conventional situation,
Therefore, an object of the present invention is to provide a novel diagnostic control method that makes it possible to solve the above-mentioned problems inherent in the conventional technology.

課題を解決するための手段 上記目的を達成する為に、本発明の診断制御方式はシス
テム制御装置内に組込み診断実行中の被診断プロセッサ
がメモリアクセスする記憶手段を有し、かつ前記被診断
プロセッサは組込み診断実行中は該記憶手段へアクセス
する構成側90(前記被診断プロセッサの記憶領域表示
)手段を有し、前記システム制御装置は該構成制御手段
を指定する診断制御手段を備えて構成され、前記被診断
プロセッサが診断動作実行中に前記記憶手段への情報の
書込み、及び読出しの転送制御を行うことを特徴として
いる。
Means for Solving the Problems In order to achieve the above object, the diagnostic control method of the present invention has a storage means embedded in a system control device and which is accessed by a processor to be diagnosed that is executing a built-in diagnosis, and the processor to be diagnosed is has a configuration side 90 (storage area display of the diagnosed processor) means for accessing the storage means during execution of the built-in diagnosis, and the system control device is configured with a diagnosis control means for specifying the configuration control means. , the processor to be diagnosed controls the transfer of writing and reading information to the storage means during execution of the diagnostic operation.

実施例 次に、本発明をその好ましい一実施例について図面を参
照して具体的に説明する。
Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

第1図は本発明の一実施例を示すブロック構成図である
FIG. 1 is a block diagram showing one embodiment of the present invention.

第1図において、システム制御装置1内の診断制御部1
0は、被診断プロセッサ2内の記憶領域表示21をシス
テム制御装置l内の記憶部IIがアクセスするように状
態表示をアドレス/書込みデータ信号線30、バス制御
信号線33で被診断プロセッサ2のバス制御部20に通
知する。
In FIG. 1, a diagnostic control section 1 in a system control device 1
0 is a status display of the processor to be diagnosed 2 via the address/write data signal line 30 and the bus control signal line 33 so that the storage area display 21 in the processor to be diagnosed 2 is accessed by the storage unit II in the system control unit I. The bus control unit 20 is notified.

被診断プロセッサ2のパス1制御部2oは、前記通知に
よって、記憶領域表示2Iへ書込みデータ信号線30の
情報を設定する。
In response to the notification, the path 1 control unit 2o of the processor to be diagnosed 2 sets the information of the write data signal line 30 in the storage area display 2I.

その後、診断制御部IOは、被診断プロセッサ2ヘアド
レス/書込みデータ信号線30.バス制御信号線33に
よってバス制御部2oを介し、診断起動要求信号23を
プロセッサ部22へ通知する。
Thereafter, the diagnostic control unit IO sends the address/write data signal line 30 . The diagnostic activation request signal 23 is sent to the processor section 22 via the bus control signal line 33 and the bus control section 2o.

被診断プロセッサ2は診断起動要求信号線23によって
診断プログラムを実行する。
The processor to be diagnosed 2 executes the diagnostic program using the diagnostic activation request signal line 23.

被診断プロセッサ2が診断実行中におけるメモリアクセ
スは、バス制御部20内の記憶領域表示21に保持され
た状態表示情報がバス要求信号線31によってバス上へ
送出され、またアドレス/書込みデータ信号線30によ
ってメモリアドレス情報及び書込みデータ情報が送出さ
れる。
When the processor 2 to be diagnosed performs a diagnosis, memory access is performed by sending the status display information held in the storage area display 21 in the bus control unit 20 onto the bus via the bus request signal line 31, and by sending it to the bus via the address/write data signal line. 30 sends out memory address information and write data information.

診断制御部lOは、バス要求信号線31の内容が自記憶
部へのアクセスかを識別し、メモリアドレス信号線12
及びデータ書込み時には書込みデータ信号線30の書込
みデータ情報をデータ信号線■3で記憶部IIへ送出す
る。被診断プロセッサ2から記憶部It内の情報の読出
しのときには、記憶部■からの読出しデータ情報がデー
タ信号13で送出され、診断制御部IOは読出しデータ
信号線32に該続出しデータ情報を送出する。
The diagnostic control unit 10 identifies whether the content of the bus request signal line 31 is an access to its own storage unit, and the memory address signal line 12
When writing data, the write data information on the write data signal line 30 is sent to the storage section II via the data signal line 3. When reading information in the storage unit It from the processor to be diagnosed 2, the read data information from the storage unit 2 is sent out as a data signal 13, and the diagnostic control unit IO sends out the successive data information to the read data signal line 32. do.

発明の詳細 な説明したように、本発明によれば、オンライン動作中
におけるプロセッサの組込み診断を実行するに際し、被
診断プロセッサのメモリアクセスに関し、主記憶装置へ
のアクセスは行わず、ンステム制8装置が記憶部を有し
、被診断プロセッサは組込み診断実行中は、該記憶部へ
メモリアクセスする構成手段を有し、該構成手段はシス
テム制御装置により指定する手段を備えることによって
、システム制御装置内の記憶部を使用して組込み診断を
実行することができ、組込み診断中の主記憶装置の記憶
保護が可能であり、かつシステム構成によって被診断プ
ロセッサのメモリアクセスの記憶領域の制限の複雑さが
ないという効果が得られる。
DETAILED DESCRIPTION OF THE INVENTION As described in detail, according to the present invention, when executing built-in diagnosis of a processor during online operation, access to the main memory of the processor to be diagnosed is not performed, and the system system has a storage section, the processor to be diagnosed has configuration means for memory access to the storage section during execution of the built-in diagnosis, and the configuration means includes means for specifying by the system control device, so that the processor can Embedded diagnostics can be executed using the memory of the processor being diagnosed, the memory of the main memory can be protected during embedded diagnostics, and depending on the system configuration, the complexity of storage area limitations for memory access of the processor being diagnosed can be reduced. The effect is that there is no

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る診断制御方式の一実施例を示すブ
ロック構成図、第2図は従来方式によるこの種の方式の
構成例を示すブロック図である。 161.システム制御装置、2.、、被診断プロセッサ
、30.、主記憶装置、10.、、診断制御部、110
0.記憶部、+2.、、メモリアドレス信号線、+3.
、。 メモリデータ信号線、+4.、、メモリ制御信号線、2
0、、、バス制御部、21.、、記憶領域表示部、22
.、。 プロセッサ部、23.、、診断起動要求信号線、24.
、。 プロセッサ記憶保護機構、25.、、主記憶装置記憶保
護機構、30.、、アドレス/@込みデータ信号線、3
1、、、バス要求信号線、 32.、、読出しデータ信
号線、33.、、バス制御信号線 特許出願人   日本電気株式会社 代 理 人   弁理士 熊谷雄太部
FIG. 1 is a block diagram showing an embodiment of the diagnostic control system according to the present invention, and FIG. 2 is a block diagram showing an example of the configuration of this type of system according to the conventional system. 161. system control device, 2. , ,diagnosed processor, 30. , main memory, 10. ,,diagnosis control unit, 110
0. Memory section, +2. , , memory address signal line, +3.
,. Memory data signal line, +4. , , memory control signal line, 2
0, , bus control unit, 21. ,, storage area display section, 22
.. ,. Processor section, 23. ,,diagnosis activation request signal line, 24.
,. Processor storage protection mechanism, 25. , , Main memory storage protection mechanism, 30. ,,address/@include data signal line, 3
1. Bus request signal line, 32. , , read data signal line, 33. , Bus control signal line patent applicant NEC Corporation Representative Patent attorney Yutabe Kumagai

Claims (1)

【特許請求の範囲】[Claims] 複数のプロセッサ、主記憶装置、入出力制御装置及びシ
ステム制御装置が同一バスで接続される中央処理装置に
おいて、システムがオンライン動作中に前記複数のプロ
セッサに組込まれるプロセッサの組込み診断を行うに際
し前記システム制御装置が記憶部を有し、前記組込み診
断が行われる被診断プロセッサは組込み診断実行中に前
記記憶部へメモリアクセスする手段を有し、前記システ
ム制御装置は前記被診断プロセッサの記憶領域表示手段
を指定する診断制御手段を有し、前記被診断プロセッサ
が診断動作実行中に前記記憶部への情報の書込みまたは
読出しに対する転送制御を行うように構成されているこ
とを特徴とする診断制御方式。
In a central processing unit in which a plurality of processors, a main storage device, an input/output control device, and a system control device are connected by the same bus, when performing an embedded diagnosis of a processor incorporated in the plurality of processors while the system is online, the system The control device has a storage unit, the processor to be diagnosed on which the embedded diagnosis is performed has means for memory accessing the storage unit during execution of the embedded diagnosis, and the system control device has a memory area display unit for the processor to be diagnosed. 1. A diagnostic control system, comprising: a diagnostic control means for specifying a diagnostic control method, the processor being configured to perform transfer control for writing or reading information to or from the storage unit while the processor to be diagnosed performs a diagnostic operation.
JP63149507A 1988-06-17 1988-06-17 Diagnosis control system Pending JPH01316840A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63149507A JPH01316840A (en) 1988-06-17 1988-06-17 Diagnosis control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63149507A JPH01316840A (en) 1988-06-17 1988-06-17 Diagnosis control system

Publications (1)

Publication Number Publication Date
JPH01316840A true JPH01316840A (en) 1989-12-21

Family

ID=15476653

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63149507A Pending JPH01316840A (en) 1988-06-17 1988-06-17 Diagnosis control system

Country Status (1)

Country Link
JP (1) JPH01316840A (en)

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