JPH01282523A - Liquid crystal display panel - Google Patents
Liquid crystal display panelInfo
- Publication number
- JPH01282523A JPH01282523A JP63113060A JP11306088A JPH01282523A JP H01282523 A JPH01282523 A JP H01282523A JP 63113060 A JP63113060 A JP 63113060A JP 11306088 A JP11306088 A JP 11306088A JP H01282523 A JPH01282523 A JP H01282523A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- glass substrate
- liquid crystal
- bus line
- display panel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 35
- 239000010408 film Substances 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000011521 glass Substances 0.000 claims abstract description 43
- 239000010409 thin film Substances 0.000 claims abstract description 20
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 abstract description 6
- 229920001721 polyimide Polymers 0.000 abstract description 5
- 239000009719 polyimide resin Substances 0.000 abstract description 5
- 239000007787 solid Substances 0.000 abstract description 4
- 238000004040 coloring Methods 0.000 abstract 1
- 238000004898 kneading Methods 0.000 abstract 1
- 239000010936 titanium Substances 0.000 description 10
- 238000007740 vapor deposition Methods 0.000 description 10
- 239000011651 chromium Substances 0.000 description 9
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 7
- 229910052804 chromium Inorganic materials 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 239000011159 matrix material Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 241001164374 Calyx Species 0.000 description 1
- 241001648319 Toronia toru Species 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000000049 pigment Substances 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概 要］
薄膜トランジスタを用いて駆動させるアクティブマトリ
クス型液晶表示パネルに関し、薄膜トランジスタの接触
防止用の絶縁膜と非画素部に入射する光の遮光体とを同
一のマスクを用いて一括形成して製造工程の短縮を図っ
た液晶表示パネルを目的とし、
第１のガラス基板上にゲートパスラインと、ドレインバ
スラインと、画素単位の篠数の薄膜トランジスタ及び画
素電極と、配向膜とを設け、前記各薄膜トランジスタの
ゲート電極を前記ゲートパスライン、ソース電極を前記
画素電極、ドレイン電極を前記ドレインバスラインにそ
れぞれ接続し、前記第１のガラス基板に対向する第２の
ガラス基板に力し−フィルタと、前記表示電極と対向す
る共通電極を設け、前記第１および第２のガラス基板間
に液晶を封入したパネルに於いて、前記第１のガラス基
板の非画素領域となる薄膜トランジスタのソース電極お
よびドレイン電極と接続するドレインバスラインの形成
領域と対向した、前記第２のガラス基板の共通電極上に
遮光体と絶縁膜とを、その順序で積層して設け、更にこ
の積層体を含む第２のガラス基板に配向膜を設けて構成
する。[Detailed Description of the Invention] [Summary] Regarding an active matrix liquid crystal display panel driven using thin film transistors, an insulating film for preventing contact between the thin film transistors and a light shielding member for light entering non-pixel areas are covered with the same mask. The purpose is to create a liquid crystal display panel that can be formed all at once to shorten the manufacturing process, using a first glass substrate to form gate pass lines, drain bus lines, thin film transistors and pixel electrodes for each pixel, and an alignment film. A gate electrode of each thin film transistor is connected to the gate pass line, a source electrode is connected to the pixel electrode, a drain electrode is connected to the drain bus line, and a force is applied to a second glass substrate facing the first glass substrate. In a panel in which a filter and a common electrode facing the display electrode are provided, and a liquid crystal is sealed between the first and second glass substrates, a thin film transistor serving as a non-pixel area of the first glass substrate is provided. A light shield and an insulating film are laminated in that order on the common electrode of the second glass substrate, which faces the formation region of the drain bus line connected to the source electrode and the drain electrode, and further this laminated body is provided. An alignment film is provided on a second glass substrate.
本発明は薄膜トランジスタを用いたアクティブマトリク
ス型液晶表示パネルに関する。The present invention relates to an active matrix liquid crystal display panel using thin film transistors.
液晶表示パネルの一画素毎に薄膜トランジスタを設けて
該トランジスタをアクティブ素子として利用するアクテ
ィブマトリックス駆動方式の液晶表示パネルは、多数の
画素をそれぞれ独立に駆動させることができるので、表
示容量の増加に伴ってスキャンハスラインやデータバス
ライン等の本数が増加しても、単純マトリックス駆動方
式の液晶表示パネルのように駆動デユーティ比が低下す
ることによるコントラストの低下をきたすような問題が
生じない利点がある。Active matrix drive type liquid crystal display panels, in which a thin film transistor is provided for each pixel of the liquid crystal display panel and the transistor is used as an active element, can drive a large number of pixels independently, so as the display capacity increases. Even if the number of scan bus lines, data bus lines, etc. increases, there is no problem such as a decrease in contrast due to a decrease in drive duty ratio, which is the case with simple matrix drive type liquid crystal display panels. .
またパネル構成がフラットで、低消費電力、鮮明なフル
カラー表示が実現できることから、小型テレビや各種Ｏ
Ａ表示端末用として鋭意、研究開発が進められている。In addition, the panel configuration is flat, low power consumption, and provides clear full-color display, making it ideal for use on small TVs and various types of TVs.
Research and development for A-display terminals is currently underway.
このような従来のアクティブマトリックス駆動型の液晶
表示パネルの構成図を第５図に示し、該液晶表示パネル
の模式的断面図を第６図に、該液晶表示パネルの要部平
面図を第７図に、第７図のｃ−ｃ’線に沿った断面図を
第８図に、第７図のＤ−Ｄ”線に沿った断面図を第９図
に示す。FIG. 5 shows a configuration diagram of such a conventional active matrix drive type liquid crystal display panel, FIG. 6 shows a schematic cross-sectional view of the liquid crystal display panel, and FIG. FIG. 8 is a sectional view taken along line cc' in FIG. 7, and FIG. 9 is a sectional view taken along line DD'' in FIG. 7.
第５図より第９図迄に示すように、第１の透明ガラス基
板ｌ上には所定パターンのチタン（Ｔｉ）よりなるゲー
ト電極２が形成され、該ゲート電極２を含むガラス基板
ｌ上に窒化シリコン（ＳｉＮ）よりなる絶縁膜３が形成
され、その上にインジウム・錫酸化物（ＩＴＯ）より成
る画素電極４が形成されてイル。更に該絶縁膜３上にア
モルファスシリコン（ａＳｉ）層５を介してｎ”５ａＳ
ｉ層６と、チタン（Ｔｉ）ＦＩＪ７と、アルミニウム（
Ａ２）層８と、クロム（Ｃｒ）層９と１層１０から成る
とソース電極１１とドレイン電極１２が形成され、該ソ
ース電極１２はＩＴＯ層１３を介して前記画素電極４に
接続され、前記ドレイン電極１２は、ゲートパスライン
１４上の絶縁膜３を介して直交するドレインバスライン
１５に接続されている。As shown in FIG. 5 to FIG. 9, a gate electrode 2 made of titanium (Ti) in a predetermined pattern is formed on a first transparent glass substrate l, and a gate electrode 2 made of titanium (Ti) is formed on a first transparent glass substrate l. An insulating film 3 made of silicon nitride (SiN) is formed, and a pixel electrode 4 made of indium tin oxide (ITO) is formed thereon. Further, an n”5aS layer is formed on the insulating film 3 via an amorphous silicon (aSi) layer 5.
i-layer 6, titanium (Ti) FIJ7, and aluminum (
A2) A source electrode 11 and a drain electrode 12 are formed by the layer 8, chromium (Cr) layer 9, and one layer 10, and the source electrode 12 is connected to the pixel electrode 4 via the ITO layer 13, and the The drain electrode 12 is connected to a drain bus line 15 orthogonal to the gate pass line 14 via an insulating film 3 on the gate pass line 14 .
また前記第１のガラス基板ｌに対向する第２のガラス基
板１６上にポリイミド樹脂に染料を混練したカラーフィ
ルタ１７が塗布形成され、該カラーフィルタ１７上に透
明な１７０層よりなる共通電極１８が全面にベタ電極と
して形成されている。そして共通電極１８と画素電極４
上にそれぞれ配向膜１９，２０が形成され、第１のガラ
ス基板ｌと第２のガラス基板１６との間に液晶２１が封
入されて液晶表示パネルが形成されている。A color filter 17 made of polyimide resin mixed with dye is coated on a second glass substrate 16 facing the first glass substrate l, and a common electrode 18 made of 170 transparent layers is formed on the color filter 17. It is formed as a solid electrode over the entire surface. And the common electrode 18 and the pixel electrode 4
Alignment films 19 and 20 are formed thereon, and a liquid crystal 21 is sealed between the first glass substrate 1 and the second glass substrate 16 to form a liquid crystal display panel.
このような液晶表示パネルの動作に付いて述べると、前
記したゲートパスライン１４に所定の電圧を印加するこ
とでゲート電極２に所定の電圧を印加し、薄膜トランジ
スタ２２を導通状態にすることでドレインバスライン１
５のデータ電圧が画素電極４に書き込まれる。即ち、画
素電極４に書き込まれたデータ電圧がセル電圧となる。Regarding the operation of such a liquid crystal display panel, a predetermined voltage is applied to the gate pass line 14 described above to apply a predetermined voltage to the gate electrode 2, and the thin film transistor 22 is brought into a conductive state. line 1
A data voltage of 5 is written to the pixel electrode 4. That is, the data voltage written to the pixel electrode 4 becomes the cell voltage.
次いで薄膜トランジスタ２２をオフ状態、即ち、非導通
状態とすることでセル電圧は、データ電圧の変動に殆、
ど影響無く、（容量結合があるために僅かに電圧は変動
するが）一定の状態に保持され、それによって、大容量
の液晶表示パネルが得られる。Next, by setting the thin film transistor 22 to an off state, that is, a non-conducting state, the cell voltage is almost insensitive to fluctuations in the data voltage.
The voltage is maintained at a constant state without any influence (although the voltage varies slightly due to capacitive coupling), thereby providing a large capacity liquid crystal display panel.
ところで、従来の装置に於いては非画素領域、即ち、ド
レイン電極１２とソース電極１１よりなる薄膜トランジ
スタ２２の領域とドレインバスライン１５、ゲートパス
ライン１４領域と、これ等の領域の間では光のＯＮ／
ＯＦＦは行われず、第６図に示すように偏光板２３．２
４を偏光方向が直交するように設けた場合、非画素領域
２５では常に光が透過するため、コントラストが低下し
ていた。By the way, in the conventional device, light is not turned on between the non-pixel area, that is, the area of the thin film transistor 22 consisting of the drain electrode 12 and the source electrode 11, the drain bus line 15, and the gate pass line 14 area. /
OFF is not performed, and the polarizing plate 23.2 is turned off as shown in FIG.
4 so that the polarization directions are perpendicular to each other, light always passes through the non-pixel area 25, resulting in a decrease in contrast.
そこで第１０図に示すように、第２のガラス基板１６に
於いて、第１のガラス基板１の非画素領域に対向する領
域に、クロム（Ｃｒ）等の金属膜よりなる光の遮光体２
６を蒸着およびホトリソグラフィ方法を用いて所定のパ
ターンに形成し、非画素領域での光の漏れを塞いだ構造
をとっている。Therefore, as shown in FIG. 10, in the second glass substrate 16, a light shielding body 2 made of a metal film such as chromium (Cr) is provided in an area facing the non-pixel area of the first glass substrate 1.
6 is formed into a predetermined pattern using vapor deposition and photolithography methods, and has a structure that blocks light leakage in non-pixel areas.
また視野角を広くとったり、コントラストを向Ｉ−させ
るために液晶が１，１人される画素電極４と共１１１１
電極１８間の距離を狭くする構造が採られているが、こ
の際、下側のガラス基板１に形成されたトレインハスラ
インＩ５やソース電極■１と上側のガラス基板１６の共
通電極１８とのショートを防止するために第１１図に示
すように、上側ガラス基板１６のドレインバスライン１
５とソース電極１１と対向する位置に絶縁膜２７を形成
する構造を採っている。In addition, in order to widen the viewing angle and improve the contrast, the pixel electrodes 4 and 1111 each have a liquid crystal layer arranged one by one.
A structure is adopted in which the distance between the electrodes 18 is narrowed, but in this case, the distance between the train line I5 formed on the lower glass substrate 1 and the common electrode 18 on the upper glass substrate 16 is reduced. In order to prevent short circuits, the drain bus line 1 of the upper glass substrate 16 is connected as shown in FIG.
5 and a structure in which an insulating film 27 is formed at a position facing the source electrode 11.
ところで、従来の構造のパネルを形成する際、第２のガ
ラス基板１６−Ｆに先ずクロム等の遮光体２６を茎着で
形成した後、該薄着膜を含む基板１６上にホトリソグラ
フィを用いた所定パターンのホトレジスト膜を形成し、
該ホトレジスト膜をマスクとしてガスエツチング等を用
いて遮光体２６を形成後、カラーフィルタ１７をスピナ
ー等を用いて塗布形成し、更に共通電極１８を基若によ
り形成した後、酸化シリコン（５ｉｎ）より成る絶縁膜
２９を蒸着、およびガスエンチング法を用いて所定パタ
ーンに形成後、その−Ｆに配向膜１９を形成している。By the way, when forming a panel with a conventional structure, first a light shielding material 26 made of chromium or the like is formed on the second glass substrate 16-F by means of a stem coating, and then photolithography is used on the substrate 16 including the thin film. Form a photoresist film with a predetermined pattern,
After forming the light shielding body 26 using gas etching using the photoresist film as a mask, coating the color filter 17 using a spinner or the like, and forming the common electrode 18 using silicon oxide (5 inches). After the insulating film 29 is formed into a predetermined pattern by vapor deposition and gas etching, the alignment film 19 is formed on -F.
そのため、遮光体２６および絶縁膜２９を所定のパター
ンに形成するためのレジストパターンを２回形成するこ
とが必要で、その都度マスク合わせをせねばならず、製
造工程が煩雑で液晶表示パネルの形成工程が掛かりすぎ
る難点があった。Therefore, it is necessary to form a resist pattern twice to form the light shielding body 26 and the insulating film 29 in a predetermined pattern, and masks must be aligned each time, making the manufacturing process complicated and forming the liquid crystal display panel. The problem was that the process was too long.
本発明は上記した問題点を除去し、前記した遮蔽体と絶
縁膜を同一マスクを用いて一括して形成し、簡単な工程
でパネルが形成できるようにした液晶表示パネルのの提
供を目的とするものである。The present invention aims to eliminate the above-mentioned problems and provide a liquid crystal display panel in which the above-described shielding body and insulating film are formed all at once using the same mask, and the panel can be formed in a simple process. It is something to do.
上記目的を達成する本発明の液晶表示パネルは、第１の
ガラス基板上にゲートバスラインと、ドレインバスライ
ンと、画素単位の複数の薄膜トランジスタ及び画素電極
と、配向〇Ｑとを設け、前記各薄膜トランジスタのゲー
ト電極を前記ゲートバスライン、ソース電極を前記画素
電極、ドレイン電極を前記ドレインバスラインにそれぞ
れ接続し、１１ｆ［記第１のガラス基板に対向する第２
のガラス基板にカラーフィルタと、前記表示電極と対向
する共通電極を設け、前記第１および第２のガラス基板
間に液晶を封入したパネルに於いて、前記第１のガラス
基板の非画素領域となる薄膜トランジスタのソース電極
およびドレイン電極と接続するドレインバスラインの形
成領域と対向した、前記第２のガラス基板の共通電極上
に遮光体と絶縁膜とを、その順序で積層して設け、更に
この積層体を含む第２のガラス基板に配向膜を設けて構
成する。A liquid crystal display panel of the present invention that achieves the above object is provided with a gate bus line, a drain bus line, a plurality of thin film transistors and pixel electrodes in pixel units, and an orientation 〇Q on a first glass substrate, and The gate electrode of the thin film transistor is connected to the gate bus line, the source electrode is connected to the pixel electrode, and the drain electrode is connected to the drain bus line, respectively.
In a panel in which a color filter and a common electrode facing the display electrode are provided on a glass substrate, and a liquid crystal is sealed between the first and second glass substrates, a non-pixel area of the first glass substrate and a common electrode facing the display electrode are provided. A light shielding body and an insulating film are laminated in that order on the common electrode of the second glass substrate, which faces the formation region of the drain bus line connected to the source electrode and the drain electrode of the thin film transistor, and An alignment film is provided on a second glass substrate including a laminate.
非画素領域を遮光する遮光体と、共通電極とソース電極
およびドレインバスラインとの接触防ＩＦ用に設けた絶
縁膜の面積は略一定である。そこで遮光体と絶縁膜の製
造工程順序を変更して上記遮蔽体と絶縁膜が同一のマス
クで一括して形成されるようなパネル構造と成し、それ
によって表示パネルの製造工程を短縮させる。The area of the light shielding body that shields the non-pixel area from light and the insulating film provided for the contact prevention IF between the common electrode and the source electrode and drain bus line are approximately constant. Therefore, the manufacturing process order of the light shielding body and the insulating film is changed to create a panel structure in which the shielding body and the insulating film are formed all at once using the same mask, thereby shortening the manufacturing process of the display panel.
以下、図面を用いて本発明の一実施例に付き３”［細に
説明する。Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.
第１図は本発明の液晶表示パネルの平面図、第２図は第
１図のＡ−Ａ ′線に沿った断面図、第３図は第１図の
Ｂ−Ｂ ’線に沿った断面図である。FIG. 1 is a plan view of the liquid crystal display panel of the present invention, FIG. 2 is a cross-sectional view taken along line A-A' in FIG. 1, and FIG. 3 is a cross-sectional view taken along line B-B' in FIG. It is a diagram.
第１図より第３図までに示すように、本発明の液晶表示
パネルが従来の装置と異なる点は、薄膜トランジスタが
形成された第１のガラス基板Ｉに対向する第２のガラス
基板１５上にカラーフィルタ１７が形成され、更にその
上に１７０層より成る透明なベタの共通電極１８が形成
されている。As shown in FIGS. 1 to 3, the liquid crystal display panel of the present invention differs from conventional devices in that a second glass substrate 15 facing the first glass substrate I on which thin film transistors are formed is A color filter 17 is formed, and a transparent solid common electrode 18 consisting of 170 layers is further formed thereon.
更にと記薄膜トランジスタのドレイン電極１２並びに該
電極に接続するドレインバスライン１５、ソース電極１
１の非画素領域上に対向して所定パターンに形成され、
非画素領域への光の通過を遮蔽するクロムよりなる遮光
体２６、およびドレインバスライン１５、ソース電極１
１と共通電極１８との接触を防！ヒするためのＳｉｎ膜
よりなる絶縁膜２７が積層して形成され、その上に配向
膜１９が形成されている点にある。Furthermore, the drain electrode 12 of the thin film transistor, the drain bus line 15 connected to the electrode, and the source electrode 1
formed in a predetermined pattern facing each other on one non-pixel area,
A light shielding body 26 made of chromium that blocks the passage of light to a non-pixel area, a drain bus line 15, and a source electrode 1
Prevent contact between 1 and common electrode 18! An insulating film 27 made of a Sin film for heat shielding is formed in a stacked manner, and an alignment film 19 is formed thereon.
このような本発明の液晶表示パネルを形成するには、第
３図（ａ）に示すように第２のガラス基板１６ヒにポリ
イミド樹脂に色素染料を混練したカラーフィルタ１７を
スピナーを用いて均一な厚さに塗布形成する。In order to form such a liquid crystal display panel of the present invention, as shown in FIG. 3(a), a color filter 17 made of polyimide resin mixed with pigment is uniformly coated on a second glass substrate 16 using a spinner. Coat and form to a certain thickness.
次いでＩＴＯ層よりなるベタの共通電極１８を蒸着によ
り形成する。Next, a solid common electrode 18 made of an ITO layer is formed by vapor deposition.
次いで第３図（ｂ）に示すように、該共通電極１８を含
む基板上にレジスト膜３１を塗布し、該レジスト膜を所
定のパターンにホトリソグラフィ法により形成する。Next, as shown in FIG. 3(b), a resist film 31 is applied onto the substrate including the common electrode 18, and the resist film is formed into a predetermined pattern by photolithography.
次いで該レジスト膜３１を形成した基板上に金属クロム
膜より成る遮光体２６、酸化珪素（Ｓｉｎ）より成る絶
縁膜２７としてのＳｉｎ膜を蒸着により連続して形成す
る。Next, on the substrate on which the resist film 31 is formed, a light shielding body 26 made of a metal chromium film and a Sin film as an insulating film 27 made of silicon oxide (Sin) are successively formed by vapor deposition.
更に第３図（Ｃ）に示すように、前記形成したレジスト
膜３１を除去することで、その上の不要な金属クロム膜
２６および絶縁膜２７を除去して共通電極１８上に金属
クロム膜２６と絶縁膜２７が積層形成されたガラス基板
１６が得られる。Furthermore, as shown in FIG. 3(C), by removing the resist film 31 formed above, the unnecessary metal chromium film 26 and insulating film 27 thereon are removed, and a metal chromium film 26 is formed on the common electrode 18. A glass substrate 16 on which an insulating film 27 and an insulating film 27 are laminated is obtained.
更に前記したように第１のガラス基板上に、所定パター
ンのチタン（Ｔｉ）よりなるゲート電極２を蒸着、およ
びエツチングを用いて形成し、該ゲート電極２を含むガ
ラス基板１上に、窒化シリコン（ＳｉＮ）よりなる絶縁
膜３を蒸着等により形成し、更に該絶縁膜３上に蒸着お
よびエツチングにより形成したａＳｉ層５を介してｎ”
：ａＳｉ層５とＴｉ層７とＡＩ層８を形成する。更にそ
の上に画素電極４と接続するためのインジウム・錫酸化
物（ＩＴＯ）層１３と、画素電極４を蒸着およびエツチ
ング法を用いて形成する。更に０１層９とＡｆｆｉ層１
ｏがら成るソース電極１１とドレイン電極１２を蒸着お
よびエツチング法を用いて形成する。前記ソース電極１
１は１７０層１３を介して前記画素電極４に接続し、前
記ドレイン電極１２は、ゲートパスライン１４上の絶縁
膜３を介して直交するドレインバスライン１５に接続す
る。Further, as described above, a gate electrode 2 made of titanium (Ti) having a predetermined pattern is formed on the first glass substrate by vapor deposition and etching, and a silicon nitride film is formed on the glass substrate 1 including the gate electrode 2. An insulating film 3 made of (SiN) is formed by vapor deposition or the like, and an aSi layer 5 is formed on the insulating film 3 by vapor deposition and etching.
: Form an aSi layer 5, a Ti layer 7, and an AI layer 8. Furthermore, an indium-tin oxide (ITO) layer 13 for connection to the pixel electrode 4 and the pixel electrode 4 are formed thereon using vapor deposition and etching methods. Furthermore, 01 layer 9 and Affi layer 1
A source electrode 11 and a drain electrode 12 are formed using vapor deposition and etching methods. The source electrode 1
1 is connected to the pixel electrode 4 via the 170 layer 13, and the drain electrode 12 is connected to the drain bus line 15 orthogonal to it via the insulating film 3 on the gate pass line 14.
そしてこれ等電極を形成した基板上にポリイミド樹脂よ
りなる配向膜２０を塗布形成し、ガラス基板】、１６間
に液晶２１を封入して液晶表示パネルを形成する。Then, an alignment film 20 made of polyimide resin is coated on the substrates on which these electrodes are formed, and a liquid crystal 21 is sealed between the glass substrates 16 to form a liquid crystal display panel.
このようにすれば、遮光体２６および絶縁膜２７を形成
するためのレジストパターンが同一ノホトマスクで一括
形成されるので、従来の方法に比較して製造工程が大幅
に短縮される。In this way, the resist patterns for forming the light shielding body 26 and the insulating film 27 are formed all at once using the same photomask, so that the manufacturing process is significantly shortened compared to the conventional method.
尚、本実施例では絶縁膜としてＳｉｎ膜を蒸着により形
成したが、ポリイミド樹脂をスピナーを用いて塗布形成
しても良い。In this embodiment, a Sin film was formed as the insulating film by vapor deposition, but polyimide resin may be applied and formed using a spinner.
以上の説明から明らかなように本発明によれば、非画素
領域への光の入射を防止する遮光体、およびソース電極
およびドレインバスラインとの接触を防止するための絶
縁膜を形成するためのレジストパターンが同一マスクを
用いて一括して形成されるので液晶表示パネル形成に要
する工程が大幅に短縮される効果がある。As is clear from the above description, according to the present invention, a light shielding body that prevents light from entering a non-pixel area and an insulating film that prevents contact with a source electrode and a drain bus line are formed. Since the resist patterns are formed all at once using the same mask, there is an effect that the steps required for forming the liquid crystal display panel are significantly shortened.
第１図は本発明の液晶表示パネルの要部平面図、第２図
は第１図のＡ−Ａ ’線に沿った断面図、第３図は第１
図のＢ−Ｂ ′線に沿った断面図、第４図（ａ）、第４
図（ｂ）、第４図（Ｃ）ハ本発明（７） ＹＴＬ 品表
示パネルの製造工程を示す断面図、
第５図はアクティブマトリックス駆動型液晶表示パネル
の構成図、
第６図は従来の液晶表示パネルの模式的断面図、第７図
は従来の液晶表示パネルの要部平面図、第８図は第７図
のｃ−ｃ ’線に沿った断面図、第９図は第７図のＤ−
Ｄ ’線に沿った断面図、第１０図は従来の液晶表示パ
ネルの模式的断面図、第１１図は従来の液晶表示パネル
の模式的断面図である。
図において、
■は第１のガラス基板、２はゲート電極、３は絶縁膜、
４は画素電極、５はａ−Ｓｉ層、６はｎ”：ａＳｉ層、
７はＴｉ層、８，１０はＡ２層、９はＣｒｌ５．１１は
ソース電極、１２はドレイン電極、１３はＩＴＯ層、１
４はゲートパスライン、１５はドレインバスライン、１
６は第２のガラス基＋反、１７はカラーフィルり、１８
は共通電極、１９．２０は配向膜、２１は液晶、２６は
遮光体、２７は絶縁膜、３Ｉはレジスト膜を示す。
才４Ｓ９〃眉に一シＡ炙木ハ・亨１１萼Ｉｐモ面１フ第
１図
才ｒ■ＩＡ Ａ−Ａ’線材句図
第２図
２１図のＢ−８’ａ泉片面図
第３図
（Ｇ３
＋ｌ）＋
（Ｃ）
年勃シガ心友晶材ハ・デルｎ＾こ遣Ｔネｆを脂よｔｉ酎
Ｕ第４図
了７テイ７淋ソ、ッ７ズ５ビ動１４塙−ち（し扛ハＩ九
司ヂ葦へ′の第５図
第６図
梯子のメし亀衷末パネル午零即平面Ｎり第７図
１ｃ）Ａｌｌ
第８図
オフ ｒ’３ 、ＰＩＤ −Ｄ’ 、！Ｊ ｔｓ；９−
ｔ−、肘（ｈ ＩＺＩ第９図
第１０図
ゾロめ３花山親木ハ０半ルｑｊ＃Ｘｒ吟諮ケｉ句図第１
１図FIG. 1 is a plan view of essential parts of a liquid crystal display panel according to the present invention, FIG. 2 is a sectional view taken along line A-A' in FIG. 1, and FIG.
A cross-sectional view taken along the line B-B' in the figure, Fig. 4(a), Fig. 4
Figures (b) and 4 (C) are cross-sectional views showing the manufacturing process of the present invention (7) YTL product display panel. Figure 5 is a configuration diagram of an active matrix drive type liquid crystal display panel. Figure 6 is a conventional A schematic cross-sectional view of a liquid crystal display panel, FIG. 7 is a plan view of essential parts of a conventional liquid crystal display panel, FIG. 8 is a cross-sectional view taken along line c-c' in FIG. 7, and FIG. 9 is a cross-sectional view of FIG. D-
10 is a schematic sectional view of a conventional liquid crystal display panel, and FIG. 11 is a schematic sectional view of a conventional liquid crystal display panel. In the figure, ① is the first glass substrate, 2 is the gate electrode, 3 is the insulating film,
4 is a pixel electrode, 5 is an a-Si layer, 6 is an n'':aSi layer,
7 is a Ti layer, 8 and 10 are A2 layers, 9 is a Crl5.11 source electrode, 12 is a drain electrode, 13 is an ITO layer, 1
4 is a gate pass line, 15 is a drain bus line, 1
6 is the second glass base + anti, 17 is color fill, 18
19 and 20 are common electrodes, 19 and 20 are alignment films, 21 is a liquid crystal, 26 is a light shield, 27 is an insulating film, and 3I is a resist film. 4S9〃Eyebrow Ichishi A Roki Ha・Toru 11 Calyx Ip Mo side 1 F 1st figure Sai r IA A-A' Wire rod figure 2 Figure 21 B-8'a Izumi single side figure 3rd Figure (G3 +l) + (C) New year's erection Shiga Shinyu Akira Material Ha Del n^ Kokage Tnef wo fat ti Chuu U 4th Figure 7 Tei 7 Hino So, Tsu 7 Zu 5 Bi Motion 14 Hana -chi (Fig. 5, Fig. 6, end panel of the ladder, Fig. 7, plane N, Fig. 7, 1c) All Fig. 8 Off r'3, PID - D',! Jts;9-
t-, elbow (h IZI Figure 9 Figure 10 Zorome 3 Hanayama Oyagi ha 0 half qj#
Figure 1
Claims (1)
と、ドレインバスライン（１５）と、画素単位の複数の
薄膜トランジスタ及び画素電極（４）と、配向膜（１９
）とを設け、前記各薄膜トランジスタのゲート電極（２
）を前記ゲートバスライン（１４）、ソース電極（１１
）を前記画素電極（４）、ドレイン電極（１２）を前記
ドレインバスライン（１５）にそれぞれ接続し、前記第
１のガラス基板（１）に対向する第２のガラス基板（１
６）にカラーフィルタ（１７）と、前記表示電極と対向
する共通電極（１８）を設け、前記第１および第２のガ
ラス基板間に液晶（２１）を封入したパネルに於いて、 前記第１のガラス基板（１）の非画素領域となる薄膜ト
ランジスタのソース電極およびドレイン電極と接続する
ドレインバスラインの形成領域と対向した、前記第２の
ガラス基板（６）の共通電極（１８）上に遮光体（２６
）と絶縁膜（２７）とを、その順序で積層して設け、更
にこの積層体を含む第２のガラス基板に配向膜（２０）
を設けたことを特徴とする液晶表示パネル。[Claims] A gate bus line (14) is provided on the first glass substrate (1).
, a drain bus line (15), a plurality of thin film transistors and pixel electrodes (4) for each pixel, and an alignment film (19).
), and a gate electrode (2) of each thin film transistor is provided.
) to the gate bus line (14) and the source electrode (11
) is connected to the pixel electrode (4), a drain electrode (12) is connected to the drain bus line (15), and a second glass substrate (1) facing the first glass substrate (1) is connected.
6) in which a color filter (17) and a common electrode (18) facing the display electrode are provided, and a liquid crystal (21) is sealed between the first and second glass substrates, comprising: A light shielding layer is provided on the common electrode (18) of the second glass substrate (6), which is opposite to the formation area of the drain bus line connected to the source and drain electrodes of the thin film transistor, which is the non-pixel area of the glass substrate (1). Body (26
) and an insulating film (27) are laminated in that order, and an alignment film (20) is further provided on a second glass substrate including this laminated body.
A liquid crystal display panel characterized by being provided with.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63113060A JPH01282523A (en) | 1988-05-09 | 1988-05-09 | Liquid crystal display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63113060A JPH01282523A (en) | 1988-05-09 | 1988-05-09 | Liquid crystal display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01282523A true JPH01282523A (en) | 1989-11-14 |
Family
ID=14602484
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63113060A Pending JPH01282523A (en) | 1988-05-09 | 1988-05-09 | Liquid crystal display panel |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01282523A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994007177A1 (en) * | 1992-09-11 | 1994-03-31 | Kopin Corporation | Color filter system for display panels |
| US5444557A (en) * | 1990-12-31 | 1995-08-22 | Kopin Corporation | Single crystal silicon arrayed devices for projection displays |
| WO1997012277A1 (en) * | 1995-09-27 | 1997-04-03 | Seiko Epson Corporation | Display device, electronic appliance and production method of the display device |
| US5661371A (en) * | 1990-12-31 | 1997-08-26 | Kopin Corporation | Color filter system for light emitting display panels |
| WO2002001286A1 (en) * | 2000-06-27 | 2002-01-03 | Kabushiki Kaisha Advanced Display | Tft array substrate, and liquid crystal display device using the same |
| KR100684699B1 (en) * | 2000-03-28 | 2007-02-20 | 샤프 가부시키가이샤 | Liquid crystal display and method of manufacturing the same |
-
1988
- 1988-05-09 JP JP63113060A patent/JPH01282523A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5444557A (en) * | 1990-12-31 | 1995-08-22 | Kopin Corporation | Single crystal silicon arrayed devices for projection displays |
| US5661371A (en) * | 1990-12-31 | 1997-08-26 | Kopin Corporation | Color filter system for light emitting display panels |
| WO1994007177A1 (en) * | 1992-09-11 | 1994-03-31 | Kopin Corporation | Color filter system for display panels |
| WO1997012277A1 (en) * | 1995-09-27 | 1997-04-03 | Seiko Epson Corporation | Display device, electronic appliance and production method of the display device |
| US5999155A (en) * | 1995-09-27 | 1999-12-07 | Seiko Epson Corporation | Display device, electronic apparatus and method of manufacturing display device |
| KR100684699B1 (en) * | 2000-03-28 | 2007-02-20 | 샤프 가부시키가이샤 | Liquid crystal display and method of manufacturing the same |
| WO2002001286A1 (en) * | 2000-06-27 | 2002-01-03 | Kabushiki Kaisha Advanced Display | Tft array substrate, and liquid crystal display device using the same |
| US6825907B2 (en) | 2000-06-27 | 2004-11-30 | Kabushiki Kaisha Advanced Display | TFT array substrate, and liquid crystal display device using the same |
| US7098969B2 (en) | 2000-06-27 | 2006-08-29 | Kabushiki Kaisha Advanced Display | TFT array substrate and liquid crystal display device using it |
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