JPH0127427Y2 - - Google Patents
Info
- Publication number
- JPH0127427Y2 JPH0127427Y2 JP17881983U JP17881983U JPH0127427Y2 JP H0127427 Y2 JPH0127427 Y2 JP H0127427Y2 JP 17881983 U JP17881983 U JP 17881983U JP 17881983 U JP17881983 U JP 17881983U JP H0127427 Y2 JPH0127427 Y2 JP H0127427Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output voltage
- output
- voltage
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- 230000010355 oscillation Effects 0.000 claims description 17
- 238000001514 detection method Methods 0.000 claims description 15
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 14
- 238000003079 width control Methods 0.000 claims description 14
- 230000005669 field effect Effects 0.000 claims description 9
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 claims description 5
- 238000009499 grossing Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 10
- 239000008186 active pharmaceutical agent Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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- Protection Of Static Devices (AREA)
- Dc-Dc Converters (AREA)
Description
【考案の詳細な説明】
本考案は直流安定化スイツチング電源装置の過
電流保護回路に関し、従来の回路に極く簡単な回
路を付加することによつて、負荷短絡時の過大電
流を容易確実に避けることができる過電流保護回
路の提供にある。[Detailed description of the invention] The present invention relates to an overcurrent protection circuit for a DC stabilized switching power supply, and by adding an extremely simple circuit to the conventional circuit, it is possible to easily and reliably prevent overcurrent in the event of a load short circuit. The purpose is to provide an overcurrent protection circuit that can be avoided.
トランジスタなどのスイツチング素子を介して
電圧変換用変圧器を直流電源に接続して、上記ス
イツチング素子を発振器を備えた制御回路の発振
周波数に同期してON−OFFし、変圧器の２次側
に得られた交流出力を整流平滑して直流出力を得
る、電圧安定化回路を備えたスイツチング電源装
置においては、装置を負荷短絡などによる過大電
流から保護するため、従来次のような方法が用い
られている。即ち電圧変換用変圧器の１次側スイ
ツチング電流の瞬時値を各サイクル毎に検出し、
この電流値が所定の設定レベルになつたとき、ス
イツチング素子をOFFせしめON−OFFデユーテ
イ比を小さくして、第１図に示す出力電圧の垂下
特性図の如く、出力電流を定電流に制限すること
によつて保護する方法である。 A voltage conversion transformer is connected to a DC power supply via a switching element such as a transistor, and the switching element is turned on and off in synchronization with the oscillation frequency of a control circuit equipped with an oscillator, and the voltage is applied to the secondary side of the transformer. In switching power supplies equipped with voltage stabilization circuits that rectify and smooth the resulting AC output to obtain DC output, the following methods have been used to protect the equipment from excessive current caused by load short circuits, etc. ing. That is, the instantaneous value of the primary side switching current of the voltage conversion transformer is detected every cycle,
When this current value reaches a predetermined set level, the switching element is turned off, the ON-OFF duty ratio is reduced, and the output current is limited to a constant current as shown in the output voltage droop characteristic diagram shown in Figure 1. This is a method of protection.
しかしこの方法では変圧器の１次側電流の検出
回路や、スイツチング素子の制御回路の遅れ時間
によつて、スイツチング素子のON−OFFデユー
テイ比を無限に小さく制御することが難かしく、
特にスイツチング素子としてバイポーラトランジ
スタが用いられた場合には、よく知られるその蓄
積時間ににより、特にON−OFFデユーテイ比を
小さくすることは難かしい。このため特に出力負
荷が短絡状態に近ずくと、第１図中にIsによつて
示すように出力電流が非常に大きくなり、これに
よつて装置を破損するおそれが大きい。以下これ
について回路図により更に詳しく説明する。 However, with this method, it is difficult to control the ON-OFF duty ratio of the switching element to an infinitely small value due to the delay time of the transformer's primary current detection circuit and the switching element control circuit.
Particularly when a bipolar transistor is used as a switching element, it is difficult to reduce the ON-OFF duty ratio due to its well-known storage time. For this reason, particularly when the output load approaches a short-circuit condition, the output current becomes very large as indicated by Is in FIG. 1, and there is a great possibility that the device will be damaged. This will be explained in more detail below using circuit diagrams.
第２図は従来の直流安定化スイツチング電源装
置の基本回路図であつて、図において１は電圧変
換用の主変圧器、２は主スイツチング用トランジ
スタ（以下主スイツチング素子と称す。）、３は電
流検出回路であつて、主変圧器１の１次側回路に
接続された電流変成器CTと、抵抗R1，R2および
ダイオードD1からなり、１次電流に比例した電
圧を得る。４は整流回路、５は平滑フイルタ回路
を示し、主スイツチング素子２のON−OFFによ
り、主変圧器１の２次側に得られた交流電圧を整
流平滑して、直流出力を取出す。６は主スイツチ
ング素子の駆動回路、７はパルス幅制御信号発生
回路を示し、コンデンサCTと抵抗RTにより設定
される発振周波数で動作する発振器を備え、その
出力に同期するパルス幅制御信号を作つて上記駆
動回路６に与える。８は出力電圧検出回路を示
し、平滑フイルタ回路５から得られた直流電圧
を、抵抗R3とR4および可変抵抗VRによつて分圧
検出する。９は定電圧制御のための誤差増幅器で
あつて、出力電圧検出回路８による分圧電圧V0
と基準直流電圧Vr1とを比較し、その誤差電圧を
負帰還増幅してパルス幅制御信号発生回路７に与
え、出力電圧が定電圧E0になるように、駆動回
路６を介して主スイツチング素子２を制御する。
１０は過電流制限を行うための比較器を示し、上
記電流変成器CTと、その出力側に接続された抵
抗R1，R2と、ダイオードD1とにより検出された、
主変圧器１の１次側スイツチング電流に比例した
電圧V1と、基準直流電圧Vr2とのレベル比較を行
い、その出力をパルス幅制御信号発生回路７に加
える。そして１次側スイツチング電流値が設定レ
ベル以上になつたとき、比較器１０の出力レベル
値を変化させて、パルス幅制御信号発生回路７か
らOFF信号を発生させ、これにより駆動回路６
を通して主スイツチング素子２をOFFさせる。 Figure 2 is a basic circuit diagram of a conventional DC stabilized switching power supply device, in which 1 is the main transformer for voltage conversion, 2 is the main switching transistor (hereinafter referred to as the main switching element), and 3 is the main switching element. The current detection circuit is composed of a current transformer CT connected to the primary circuit of the main transformer 1, resistors R 1 , R 2 and a diode D 1 , and obtains a voltage proportional to the primary current. Reference numeral 4 indicates a rectifier circuit, and 5 indicates a smoothing filter circuit, which rectify and smooth the AC voltage obtained on the secondary side of the main transformer 1 by turning the main switching element 2 ON and OFF, and output a DC output. Reference numeral 6 indicates a drive circuit for the main switching element, and reference numeral 7 indicates a pulse width control signal generation circuit, which includes an oscillator that operates at an oscillation frequency set by a capacitor CT and a resistor R T , and generates a pulse width control signal synchronized with the output of the oscillator. and supplies it to the drive circuit 6. Reference numeral 8 denotes an output voltage detection circuit, which divides and detects the DC voltage obtained from the smoothing filter circuit 5 using resistors R 3 and R 4 and a variable resistor VR. 9 is an error amplifier for constant voltage control, and the divided voltage V 0 by the output voltage detection circuit 8 is
is compared with the reference DC voltage Vr 1 , and the error voltage is amplified by negative feedback and given to the pulse width control signal generation circuit 7, and the main switching is performed via the drive circuit 6 so that the output voltage becomes a constant voltage E 0 . Control element 2.
10 indicates a comparator for limiting overcurrent, which is detected by the current transformer CT, resistors R 1 and R 2 connected to its output side, and diode D 1 .
A voltage V 1 proportional to the primary side switching current of the main transformer 1 is compared in level with a reference DC voltage Vr 2 , and its output is applied to the pulse width control signal generation circuit 7 . When the primary side switching current value exceeds the set level, the output level value of the comparator 10 is changed to cause the pulse width control signal generation circuit 7 to generate an OFF signal, which causes the drive circuit 6
The main switching element 2 is turned OFF through the switch.
この回路においては上記の如き構成と動作によ
り、主変圧器１の１次側スイツチング電流値が過
電流制限値以下の領域では、電流変成器CTの２
次側にダイオードD1を介して接続された抵抗R2
に発生する電圧は、基準直流電圧Vr2のレベルに
達しない。このため出力電圧は第１図中に示す実
線曲線の平坦部のようにE0に定電圧制御される。
また過負荷の状態になつて１次側スイツチング電
流が電流制限レベルになると、前記したように各
サイクル毎に主スイツチング素子２はOFFにな
るため、過負荷（負荷インピーダンスの低下）が
進むと共に出力電圧は垂下し、電流制限を行う。 In this circuit, due to the above-described configuration and operation, when the primary side switching current value of the main transformer 1 is below the overcurrent limit value, the current transformer CT
Resistor R 2 connected via diode D 1 on the next side
The voltage generated at Vr2 does not reach the level of the reference DC voltage Vr2. Therefore, the output voltage is controlled to a constant voltage E 0 as shown in the flat part of the solid curve shown in FIG.
Furthermore, when an overload condition occurs and the primary side switching current reaches the current limit level, the main switching element 2 turns OFF every cycle as described above, so as the overload (load impedance decreases) progresses, the output The voltage droops and current is limited.
しかし実際上電流検出回路３の動作の遅れ時
間、過電流制限用比較器１０、パルス幅制御信号
発生回路７、駆動回路６などの制御回路がもつ、
動作の遅れ時間をなくすことができない。また特
に主スイツチング素子２としてバイポーラトラン
ジスタが用いられた場合には、その蓄積時間が上
記制御回路の遅れ時間に加わることになる。この
ため出力電圧が非常に低くなつた垂下領域では主
スイツチング素子のON−OFFデユーテイ比を十
分小さくすることができにくい。従つて第１図に
示すように完全な定電流特性とはならないばかり
か、出力電圧が非常に低くなつた領域では第１図
中に実線で示す如く、定電流曲線を大きくはずれ
て電流は急激に増加し、負荷の短絡状態ではIsで
示す大きな電流となる。このため電源装置内の部
品を破壊することがあり、この現象は電源装置内
の回路インピーダンスが相対的に低くなる出力電
圧E0が高いものほど著しい。 However, in practice, the delay time of the operation of the current detection circuit 3, the overcurrent limiting comparator 10, the pulse width control signal generation circuit 7, the drive circuit 6, and other control circuits have
Operation delay time cannot be eliminated. Moreover, especially when a bipolar transistor is used as the main switching element 2, its accumulation time will be added to the delay time of the control circuit. Therefore, in a drooping region where the output voltage is extremely low, it is difficult to make the ON-OFF duty ratio of the main switching element sufficiently small. Therefore, not only is the constant current characteristic not perfect as shown in Figure 1, but in the region where the output voltage is extremely low, the current deviates sharply from the constant current curve, as shown by the solid line in Figure 1. When the load is short-circuited, the current becomes large as indicated by Is. Therefore, components within the power supply device may be destroyed, and this phenomenon becomes more pronounced as the output voltage E 0 becomes higher and the circuit impedance within the power supply device becomes relatively lower.
そこでその対策として例えば第２図に示すよう
に、比較器１０の基準直流電圧Vr2の接続端子と
正極性出力端子間に、ダイオードD2を追加接続
する方法が提案されている。この方法によれば出
力電圧が基準直流電圧Vr2以下に低下したときに
は、ダイオードD2の作用により、基準となるレ
ベルは出力電圧により決定されることから、出力
電圧の垂下が進むに伴い基準となるレベルも低下
して、電流の制限レベルも下げられる。このため
負荷短絡時における電流を効果的に制限して回路
を過大電流から保護できるが、前記したように電
源装置内の回路インピーダンスが相対的に低くな
る、出力電圧E0が高く短絡電流が大きい装置の
場合には、前記した制御回路の遅れ時間によつ
て、垂下特性は第１図中に点線によつて図示する
ようになり、負荷短絡時の出力電流もI′sで示す
大きい値となるので、十分な過電流保護機能を発
揮できない欠点がある。 Therefore, as a countermeasure, a method has been proposed in which a diode D 2 is additionally connected between the connection terminal of the reference DC voltage Vr 2 and the positive output terminal of the comparator 10, as shown in FIG. 2, for example. According to this method, when the output voltage drops below the reference DC voltage Vr 2 , the reference level is determined by the output voltage due to the action of the diode D 2 , so as the output voltage continues to drop, the reference level becomes lower. The current limit level is also lowered. For this reason, the current can be effectively limited when the load is short-circuited and the circuit can be protected from excessive current, but as mentioned above, the circuit impedance within the power supply is relatively low, the output voltage E 0 is high, and the short-circuit current is large. In the case of a device, due to the delay time of the control circuit described above, the drooping characteristic becomes as shown by the dotted line in Figure 1, and the output current when the load is shorted also reaches a large value indicated by I's. Therefore, there is a drawback that a sufficient overcurrent protection function cannot be exhibited.
本考案は従来の回路に簡単な回路を付加するこ
とによつて、出力電圧が高い直流安定化スイツチ
ング装置においても、負荷短絡時の過電流を効果
的に制限して、装置の保護を確実に行いうる過電
流保護回路の提供を目的とするものである。次に
図面を用いてその詳細を説明する。 By adding a simple circuit to the conventional circuit, this invention effectively limits overcurrent in the event of a load short circuit, even in DC stabilizing switching devices with high output voltages, and ensures protection of the device. The purpose of this invention is to provide an overcurrent protection circuit that can perform Next, the details will be explained using the drawings.
第３図は本考案の一実施例回路図、第４図ａ，
ｂは垂下領域での動作変換周波数特性図および出
力電圧の垂下特性図（第１図と同一符号は同等部
分を示す。）であつて、本考案の特徴とするとこ
ろは次の点にある。即ち従来回路を示す第２図と
対比して明らかなように、本考案においてはパル
ス幅制御信号発生回路７において、その発振器の
発振周波数を設定する抵抗RTと直列に抵抗R5を
接続すると同時に、R5と並列にドレイン．ソー
ス間が接続された電界効果トランジスタFETを
設けて、そのゲートに正バイアスを与えるように
出力電圧検出回路８に接続する。そし出力電圧の
分圧値を選定して、ドレイン．ソース間インピー
ダンスZD-Sが、定電圧領域においては抵抗RTに対
して充分小さい値を呈するようにゲートバイアス
VGを保持して、パルス幅制御信号発生回路７の
もつ発振器の発振周波数が変らないようにし、出
力電圧が非常に小さくなつた領域では、ゲートバ
イアスVGが不十分となつて高インピーダンスを
呈し、発振周波数が低下するようにしたことを特
徴とするものである。 Figure 3 is a circuit diagram of an embodiment of the present invention, Figure 4a,
b is an operating conversion frequency characteristic diagram and an output voltage drooping characteristic diagram in the drooping region (the same symbols as in FIG. 1 indicate the same parts), and the features of the present invention are as follows. That is, as is clear from the comparison with FIG. 2 showing the conventional circuit, in the present invention, in the pulse width control signal generation circuit 7, if a resistor R5 is connected in series with the resistor R T that sets the oscillation frequency of the oscillator, At the same time, drain in parallel with R5 . A field effect transistor FET whose sources are connected is provided and connected to the output voltage detection circuit 8 so as to apply a positive bias to its gate. Then, select the divided voltage value of the output voltage and apply it to the drain. The gate bias is set so that the source-to-source impedance Z DS exhibits a sufficiently small value with respect to the resistance R T in the constant voltage region.
V G is maintained so that the oscillation frequency of the oscillator of the pulse width control signal generation circuit 7 does not change, and in the region where the output voltage becomes very small, the gate bias V G becomes insufficient and high impedance is generated. It is characterized in that the oscillation frequency is lowered.
このようにドレイン．ソース間インピーダンス
ZD-Sが、並列抵抗R5に対して十分小さい値になる
ようなゲートバイアスVGが与えられる定電圧領
域においては、パルス幅制御信号発生回路７がも
つ発振器の発振周波数は、ほぼ抵抗RTとコンデ
ンサCTによつて定まる第４図ａの0となる。しか
も電界効果トラジスタFETの入力インピーダン
スZGは周知のように非常に高いことから、ゲート
を出力電圧検出回路８の分圧点に直接接続して
も、スイツチング電源装置の動作および出力電圧
の設定値には殆ど影響を与えることがない。従つ
て定電圧領域では第２図に示した従来の回路と同
じ動作を行い、第４図ｂに示すように出力電圧を
E0に安定化する。また過負荷となつて電流の制
限領域に入ると出力電圧が低下するが、抵抗RT
と電界効果トランジスタFETのドレイン．ソー
ス間インピーダンスZD-Sの関係がRT≫ZD-Sの範囲
では電流の制限動作を行い、第４図ｂに示すよう
に第１図に示した特性と殆ど変ることがなくほぼ
定電流で垂下する。しかし電界効果トランジスタ
FETのゲートバイアスVGが不十分となつて、ド
レイン・ソース間インピーダンスZD-Sが高インピ
ーダンスに変化し始める点、例えば第４図ａ中の
E1になると、パルス幅制御信号発生回路７のも
つ発振器の発振周波数を定める抵抗値は、RTか
らRT＋R5・ZD-S／（R5＋ZD-S）によつて定まる
ものとなり、ZD-Sの増大と共に大きくなる。そし
てコンデンサCTとによつて定まる発振周波数を
次第に低下させ、R5≪ZD-Sになると第４図ａに示
すように、ほぼRT＋R5の値によつて定まる発振
周波数sとなる。 Drain like this. Source-to-source impedance
In a constant voltage region where a gate bias V G is applied such that Z DS becomes a sufficiently small value with respect to the parallel resistance R 5 , the oscillation frequency of the oscillator of the pulse width control signal generation circuit 7 is approximately equal to the resistance R T and the capacitor C T becomes 0 in Fig. 4a. Moreover, since the input impedance Z G of the field effect transistor FET is very high as is well known, even if the gate is connected directly to the voltage dividing point of the output voltage detection circuit 8, the operation of the switching power supply and the set value of the output voltage will be affected. has almost no influence. Therefore, in the constant voltage region, the same operation as the conventional circuit shown in Figure 2 is performed, and the output voltage is changed as shown in Figure 4b.
Stabilizes to E 0 . Also, if the current is overloaded and enters the current limit region, the output voltage will drop, but the resistance R T
and the drain of the field effect transistor FET. In the range where the relationship between source-to-source impedance Z DS is R T ≫ Z DS , the current is limited, and as shown in Figure 4b, the characteristics are almost unchanged from those shown in Figure 1, and the current drops at an almost constant current. . But field effect transistor
The point where the gate bias V G of the FET becomes insufficient and the drain-source impedance Z DS begins to change to high impedance, for example, as shown in Figure 4 a.
When E 1 , the resistance value that determines the oscillation frequency of the oscillator of the pulse width control signal generation circuit 7 is determined by R T + R 5 · Z DS / (R 5 + Z DS ), and Z DS It becomes larger as the value increases. Then, the oscillation frequency determined by the capacitor C T is gradually lowered, and when R 5 <<Z DS , the oscillation frequency s becomes approximately determined by the value of R T +R 5 as shown in FIG. 4a.
このように負荷短絡に近い領域において発振周
波数を急速に低下すれば、これに伴い主変圧器１
の２次側に生ずる交流出力の各周期が長くなるの
で、整流回路４などによつて整流平滑された直流
出力電圧は低下し、出力電流も低下する。その結
果前記したように負荷短絡に近い領域において主
スイツチング素子２のON時間が前記のように十
分短かくならなくても、出力電流は第４図ｂに示
すように出力電圧がE1まで垂下したところから
減少を始め、負荷短絡時においては第４図ａの周
波数sと、制御回路の遅れ時間、回路インピーダ
ンス等によつて定まる、従来回路より遥かに小さ
い電流Isとなる。しかもIsは抵抗R5の値の選定に
よる発振周波数の制御により変えることができる
ので、出力電圧が高い場合にも回路の部品を過電
流から保護することができる。 If the oscillation frequency is rapidly reduced in the region near the load short circuit, the main transformer 1
Since each period of the AC output generated on the secondary side of the AC output becomes longer, the DC output voltage rectified and smoothed by the rectifier circuit 4 or the like decreases, and the output current also decreases. As a result, as described above, even if the ON time of the main switching element 2 is not sufficiently short in the region close to the load short circuit, the output current drops to E1 as shown in Figure 4b. When the load is short-circuited, the current Is becomes much smaller than that of the conventional circuit, which is determined by the frequency s shown in FIG. 4a, the delay time of the control circuit, the circuit impedance, etc. Moreover, since Is can be changed by controlling the oscillation frequency by selecting the value of the resistor R5 , the circuit components can be protected from overcurrent even when the output voltage is high.
また更にこの本考案回路に第２図によつて説明
したと同様に、ダイオードD2を付加することに
より、出力電圧E0が高い場合にも電流の抑制を
効果的に行うことができる。即ち負荷短絡に近い
垂下領域では、本考案によつて設けられた抵抗
R5と電界効果トランジスタFETによる、パルス
幅制御信号発生回路７の発振器の発振周波数、即
ち動作周波数の低下に、更にダイオードD2によ
る前記した過電流制限レベルの低下による効果が
相加される。その結果負荷短絡時の電流は、第４
図ｂ中に点線によつて図示するようにIsより小さ
いI′sに減少する。しかもI′sは抵抗R5の値によつ
て変えることができるので、出力電圧が高く電流
が非常に過大になる場合においてもこれを低減す
ることができる。 Furthermore, by adding a diode D 2 to the circuit of the present invention, as explained with reference to FIG. 2, the current can be effectively suppressed even when the output voltage E 0 is high. In other words, in the droop region near the load short circuit, the resistor provided by the present invention
In addition to the reduction in the oscillation frequency, that is, the operating frequency, of the oscillator of the pulse width control signal generation circuit 7 due to R 5 and the field effect transistor FET, the effect of the reduction in the overcurrent limit level described above due to the diode D 2 is added. As a result, the current when the load is short-circuited is
It decreases to I's, which is smaller than Is, as illustrated by the dotted line in Figure b. Furthermore, since I's can be changed by changing the value of the resistor R5 , it can be reduced even when the output voltage is high and the current is extremely excessive.
なお第３図においては電界効果トランジスタ
FETのゲートを、出力電圧検出回路８の可変抵
抗VRと抵抗R4の接続点に接続したが、必要とす
る適当なバイアス電圧を得るため、可変抵抗VR
の中間タツプ或いはVRと抵抗R3の接続点に接続
しても本考案による効果は何ら変らないことは明
らかである。 In addition, in Fig. 3, a field effect transistor
The gate of the FET was connected to the connection point of the variable resistor VR of the output voltage detection circuit 8 and the resistor R4 , but in order to obtain the appropriate bias voltage required, the variable resistor VR
It is clear that the effect of the present invention will not change at all even if it is connected to the intermediate tap of VR and the connection point of resistor R3 .
以上の説明から明らかなように、本考案によれ
ば従来回路に抵抗と電界効果トランジスタを付加
するのみの簡単な方法により、定電圧特性などに
影響を与えることなく、負荷短絡領域近辺の垂下
特性を改善して過電流保護機能の向上を図ること
ができ、しかもその改善効果を出力電圧の高いス
イツチング電源装置にも発揮させうるもので、実
用に供してその効果は大である。 As is clear from the above explanation, according to the present invention, by simply adding a resistor and a field effect transistor to the conventional circuit, the drooping characteristics near the load short-circuit region can be improved without affecting the constant voltage characteristics etc. It is possible to improve the overcurrent protection function by improving the overcurrent protection function, and the improvement effect can also be exhibited in a switching power supply device with a high output voltage, and the effect is great in practical use.
第１図は電過流保護機能を備えた直流安定化ス
イツチング電源装置の出力垂下特性例図、第２図
は従来装置の回路図、第３図は本考案の一実施例
の基本回路図、第４図ａ，ｂは本考案による周波
数と垂下電圧の関係図および出力垂下特性図であ
る。
１……電圧変換用主変圧器、２……主スイツチ
ング素子、３……電流検出回路、CT……電流変
成器、R1，R2……抵抗、D1……ダイオード、４
……整流回路、５……平滑フイルタ回路、６……
主スイツチング素子駆動回路、７……パルス幅制
御信号発生回路、CT，RT……発振周波数を定め
るためのコンデンサと抵抗、８……出力電圧検出
回路、R3，R4，VR……その分圧抵抗、９……定
電圧制御のための誤差増幅器、Vr1……基準直流
電圧、１０……過電流制限用比較器、Vr2……基
準直流電圧、D2……過電流制限レベル低下用ダ
イオード。
Fig. 1 is a diagram showing an example of output droop characteristics of a DC stabilized switching power supply device equipped with a current overcurrent protection function, Fig. 2 is a circuit diagram of a conventional device, and Fig. 3 is a basic circuit diagram of an embodiment of the present invention. FIGS. 4a and 4b are diagrams showing the relationship between frequency and voltage droop and output droop characteristics according to the present invention. DESCRIPTION OF SYMBOLS 1...Main transformer for voltage conversion, 2...Main switching element, 3...Current detection circuit, CT...Current transformer, R1 , R2 ...Resistor, D1 ...Diode, 4
... Rectifier circuit, 5 ... Smoothing filter circuit, 6 ...
Main switching element drive circuit, 7... Pulse width control signal generation circuit, C T , RT ... Capacitor and resistor for determining oscillation frequency, 8... Output voltage detection circuit, R 3 , R 4 , VR... Voltage dividing resistor, 9...Error amplifier for constant voltage control, Vr 1 ...Reference DC voltage, 10...Comparator for overcurrent limiting, Vr 2 ...Reference DC voltage, D2 ...Overcurrent limiting Diode for level reduction.
Claims (1)
イツチング素子と、前記主変圧器の２次側に接続
された整流平滑回路と、前記主変圧器の１次側電
流検出回路と、過電流制限用比較回路と、出力電
圧検出回路と、誤差電圧検出回路と、コンデンサ
と抵抗により発振周波数が設定される発振回路を
有するパルス幅制御信号発生回路とを備え、前記
出力電圧の誤差電圧検出回路出力により前記パル
ス幅信号発生回路を介して前記主スイツチング素
子の動作を制御して出力電圧を安定化制御すると
共に、前記過電流制限用比較回路出力により前記
パルス幅制御信号発生回路を介して、前記主スイ
ツチング素子の動作を制御して、出力電圧に垂下
特性をもたせて過電流制御を行うようにした直流
安定化スイツチング電源装置において、前記発振
回路の発振周波数を設定する抵抗と直列に、電界
効果トランジスタと抵抗の並列回路を接続し、電
界効果トランジスタのゲートを前記出力電圧検出
回路の出力電圧検出用抵抗の分圧点に接続したこ
とを特徴とする直流安定化スイツチング電源装置
の過電流保護回路。 A main switching element connected to the primary side of the main transformer for voltage conversion, a rectifying and smoothing circuit connected to the secondary side of the main transformer, a primary current detection circuit of the main transformer, The circuit includes a comparison circuit for current limiting, an output voltage detection circuit, an error voltage detection circuit, and a pulse width control signal generation circuit having an oscillation circuit whose oscillation frequency is set by a capacitor and a resistor, and detects an error voltage of the output voltage. The circuit output controls the operation of the main switching element via the pulse width signal generation circuit to stabilize the output voltage, and the output of the overcurrent limiting comparison circuit controls the operation of the main switching element via the pulse width control signal generation circuit. , in a DC stabilized switching power supply device that controls the operation of the main switching element to give drooping characteristics to the output voltage and perform overcurrent control, in series with a resistor that sets the oscillation frequency of the oscillation circuit; Overcurrent of a DC stabilized switching power supply device, characterized in that a parallel circuit of a field effect transistor and a resistor is connected, and the gate of the field effect transistor is connected to a voltage dividing point of the output voltage detection resistor of the output voltage detection circuit. protection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17881983U JPS6089785U (en) | 1983-11-21 | 1983-11-21 | Overcurrent protection circuit for DC stabilized switching power supply equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17881983U JPS6089785U (en) | 1983-11-21 | 1983-11-21 | Overcurrent protection circuit for DC stabilized switching power supply equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6089785U JPS6089785U (en) | 1985-06-19 |
| JPH0127427Y2 true JPH0127427Y2 (en) | 1989-08-16 |
Family
ID=30388137
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17881983U Granted JPS6089785U (en) | 1983-11-21 | 1983-11-21 | Overcurrent protection circuit for DC stabilized switching power supply equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6089785U (en) |
-
1983
- 1983-11-21 JP JP17881983U patent/JPS6089785U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6089785U (en) | 1985-06-19 |
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