JPH01264264A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01264264A JPH01264264A JP9152688A JP9152688A JPH01264264A JP H01264264 A JPH01264264 A JP H01264264A JP 9152688 A JP9152688 A JP 9152688A JP 9152688 A JP9152688 A JP 9152688A JP H01264264 A JPH01264264 A JP H01264264A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- polycrystalline silicon
- gate electrode
- electrodes
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 230000005669 field effect Effects 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 10
- 238000009792 diffusion process Methods 0.000 abstract description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052721 tungsten Inorganic materials 0.000 abstract description 8
- 239000010937 tungsten Substances 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 229910052698 phosphorus Inorganic materials 0.000 abstract 1
- 239000011574 phosphorus Substances 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000000463 material Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000609 electron-beam lithography Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に係り、特に高集積化に好適な高信
頼度高速ＭＩＳ型半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a highly reliable and high speed MIS type semiconductor device suitable for high integration.
従来ゲートとソース・ドレインをオーバラップさせたＬ
ＤＤ （ライトリ ドープト ドレイン；Ｌｉｇｈｔｌ
ｙ Ｄｏｐｅｄ Ｄｒａｉｎ）型Ｍ Ｉ Ｓ （Ｍｅｔ
ａｌ −Ｉｎｓｕｌａｔｏｒ−Ｓｅｍｉｃｏｎｄｕｃｔ
ｏｒ） Ｆ Ｅ Ｔについては。Conventional L with overlapping gate, source and drain
DD (Lightly Doped Drain)
y Doped Drain) type M I S (Met
al-Insulator-Semiconductor
or) Regarding FET.
アイ・イー・デイ−・エム １９８６．テクニカル・ダ
イジェスト（１９８６年）第７４２頁から第７４５頁（
丁Ｅ Ｄ Ｍ １９８６ 、 ＴｅｃｈｎｉｃａｌＤ
ｉｇｅｓｔ（１９８６）ＰＰ７４２−７４５）において
論じられている。I.E.D.M. 1986. Technical Digest (1986) pp. 742-745 (
Ding EDM 1986, Technical D
(1986) PP742-745).
上記従来技術はソース抵抗の低減の効果について最−適
化が配慮されておらず、まだソース抵抗が高いという問
題があった。また、ゲートがオフの状態で起こるゲート
電極下のドレイン領域の表面反転層の゛形成及びそれに
起因する価電子帯、伝導帯間での電子のトンネル現象に
よるリーク電流の増大について配慮がなされておらず、
ダイナミック回路への適用が困難という問題があった。The above-mentioned conventional technology does not consider optimization of the effect of reducing source resistance, and there is still a problem in that the source resistance is high. In addition, no consideration has been given to the formation of a surface inversion layer in the drain region under the gate electrode that occurs when the gate is off, and the resulting increase in leakage current due to electron tunneling between the valence band and conduction band. figure,
There was a problem in that it was difficult to apply to dynamic circuits.
本発明の目的はこれらの問題を同時に解決することにあ
る。The purpose of the present invention is to simultaneously solve these problems.
上記目的は、ソース・ドレイン部にオーバラップした部
分のゲート電極の仕事関数を、チャネル部の電極のそれ
と異なるものにする事により、達成される。The above object is achieved by making the work function of the portion of the gate electrode that overlaps the source/drain portion different from that of the electrode in the channel portion.
第１図（ａ）は本発明をｎチャネルＭＯ３ＦＥＴを適用
した場合の基本的な構成を示す断面図である。FIG. 1(a) is a sectional view showing the basic configuration when the present invention is applied to an n-channel MO3FET.
第１電極５及び第２電極６をいずれもｐ型不純物である
ホウ素をドープした縮退した多結晶シリコンで形成した
場合１図中Ａ−Ａ’で示した断面のエネルギ帯のダイヤ
グラフは第１図（ｂ）の如くなる。但し、ここではフラ
ットバンド状態を想定している。今、Ｖ ａ ＝ Ｖ
ｇ ＝ ５ Ｖという高電流動作状態でのソース側を考
える。エネルギ帯のダイヤグラムは第１図（Ｑ）の様に
なるｍｎ−″ソース領域の表面は電荷の蓄積層が形成さ
れる。この蓄積層の形成によりソースのｎ−領域の寄生
抵抗が低減される。ここでゲート材料としてｎ型にドー
プした縮退した多結晶ポリシリコンを用いると仕事関数
がｐ型の場合に比べ約１ｖ低いので、ｎ−ソース領域の
エネルギ帯の曲がりが大きくなり、第１図（ｄ）の様に
蓄積電荷量が増大する。この様にゲート電極の仕事関数
を小さくすればソースの寄生抵抗を下げる事ができる。When both the first electrode 5 and the second electrode 6 are formed of degenerate polycrystalline silicon doped with boron, which is a p-type impurity, the energy band diagram of the cross section indicated by A-A' in Figure 1 is the first one. It will look like figure (b). However, a flat band state is assumed here. Now, V a = V
Consider the source side under high current operating conditions of g = 5 V. The energy band diagram is shown in Figure 1 (Q). A charge accumulation layer is formed on the surface of the mn-" source region. The formation of this accumulation layer reduces the parasitic resistance of the n- region of the source. If n-type doped degenerate polycrystalline polysilicon is used as the gate material, the work function is approximately 1V lower than that of p-type, so the energy band of the n-source region becomes more curved, as shown in Figure 1. The amount of accumulated charge increases as shown in (d).By reducing the work function of the gate electrode in this way, the parasitic resistance of the source can be lowered.
次に■「＝ｏ■、■、＝５ｖという状態でのドレイン側
を考える。まずｐ型にドープした多結晶シリコンゲート
な極の場合のエネルギ帯のダイヤグラムは第１図（ｅ）
の如くである。ｎ−シリコンのエネルギ帯の曲がりが大
きいため、ｎ−領域の表面は反転層を形成し１図中に矢
印で示した様に価電子帯から伝導帯への電子のトンネル
現象が起こり、これに起因する電流がもれ電流として観
測される事になる。−力筒１図（ｆ）に示した様にｎ型
にドープした多結晶シリコンゲート電極を用いた場合、
エネルギ帯の曲がりは抑えられ、このもれ電流が抑えら
れる。Next, consider the drain side in the state of ■=o■,■,=5V.First, the energy band diagram for a p-type doped polycrystalline silicon gate pole is shown in Figure 1(e).
It's like this. Because the energy band of n-silicon has a large bend, an inversion layer is formed on the surface of the n- region, and a tunneling phenomenon of electrons from the valence band to the conduction band occurs as shown by the arrow in Figure 1. The resulting current will be observed as a leakage current. - When using an n-type doped polycrystalline silicon gate electrode as shown in Figure 1(f),
The bending of the energy band is suppressed, and this leakage current is suppressed.
以上述べてきた様に、いずれの問題に関してもｎ′″ソ
ース・ドレイン領域上のゲート電極の仕事関数は小さい
方が好ましい。以上の説明では、ｐ＋ゲートとｎ＋ゲー
トでの比較を行なったが、その他の金属ゲートであって
も上の考察があてはまる。また、ｐチャネルＭＯ３の場
合は、電圧の極性が逆のため、ｐ−ソース・ドレイン領
域上のゲート電極の仕事関数は大きい方が良い事になる
。As mentioned above, for any problem, it is preferable that the work function of the gate electrode on the n''' source/drain region is smaller.In the above explanation, a comparison was made between a p+ gate and an n+ gate. The above considerations also apply to other metal gates.Also, in the case of p-channel MO3, since the voltage polarity is opposite, it is better to have a larger work function for the gate electrode on the p-source/drain region. become.
チャネル部のゲート電極も同じ指針でその材料を決めて
差しつかえないが、現実にはゲート電極の抵抗の観点か
ら仕事関数のある程度大きい材料。The material for the gate electrode in the channel section can be determined using the same guidelines, but in reality, it is a material with a somewhat large work function from the viewpoint of the resistance of the gate electrode.
例えばタングステンやモリブデン等の金属等が使われる
。こうした場合にソース・ドレイン部のオーバラップし
たゲート電極を仕事関数の低い材料に変える事により、
ソース抵抗、ゲート誘起のもれ電流の問題を両方改善で
きる。For example, metals such as tungsten and molybdenum are used. In such cases, by changing the overlapping gate electrodes in the source and drain regions to a material with a low work function,
Both source resistance and gate-induced leakage current problems can be improved.
以下１本発明の実施例を図を用いて、説明する。 An embodiment of the present invention will be described below with reference to the drawings.
実施例１
ｐ型Ｓｉ基板１上に熱酸化法で１０ｎｍ程度のＳ ｊ、
Ｏｚ膜２を成長し、その上にスパッタ法で第１のゲー
ト電極となるタングステン５を２５０ｎｍ堆積する。こ
の材料は、タングステンに限らずモリブデン等でも良い
。Example 1 S j of about 10 nm is formed on a p-type Si substrate 1 by thermal oxidation method.
An Oz film 2 is grown, and 250 nm of tungsten 5, which will become a first gate electrode, is deposited thereon by sputtering. This material is not limited to tungsten, but may also be molybdenum or the like.
写真蝕刻法あるいは電子線描画技術を用いてゲートをパ
タニングした後、低濃度のソース・ドレイン拡散層３を
形成する。この時の断面構造が第２図（ａ）である。After patterning the gate using photolithography or electron beam lithography, a low concentration source/drain diffusion layer 3 is formed. The cross-sectional structure at this time is shown in FIG. 2(a).
更に、ＣＶＤ法で全面に多結晶シリコン膜を２００ｎｍ
堆積し、８７５℃でリンを拡散してｎ型化する。異方性
エツチングでこの多結晶シリコンをエツチングするとゲ
ート側壁部にのみ多結晶シリコンが残り、第１のタング
ステンゲートと導通のとれた第２のゲートが形成される
（第２図（ｂ−））。Furthermore, a 200nm polycrystalline silicon film is deposited on the entire surface using the CVD method.
It is deposited and phosphorous is diffused at 875° C. to make it n-type. When this polycrystalline silicon is etched using anisotropic etching, the polycrystalline silicon remains only on the side walls of the gate, forming a second gate that is electrically connected to the first tungsten gate (Figure 2 (b-)). .
この後、第１及び第２のゲート電極をマスクに高濃度拡
散Ｍ４を形成する。これにより第２図（Ｑ）の如き構造
が得られる。Thereafter, high concentration diffusion M4 is formed using the first and second gate electrodes as masks. As a result, a structure as shown in FIG. 2(Q) is obtained.
本実施例により、ゲートの抵抗が低く、高耐圧であり且
つ、ソース抵抗が低く、ゲート誘起のもれ電流も少ない
デバイスが得られる。According to this embodiment, a device with low gate resistance, high breakdown voltage, low source resistance, and low gate-induced leakage current can be obtained.
実施例２
実施例１と同様に低濃度ソース・ドレイン領域までを形
成する。その後、Ｈｘ ＯとＨｚの雰囲気中で熱処理す
る事により拡散層上に５ｉＯｚ７を成長させる。この時
、タングステンの第１ゲート電極５は酸化されない。そ
の後は、実施例１と同様のプログラムを経て第３図の如
き構造が得られる。Example 2 Similar to Example 1, up to the low concentration source/drain regions are formed. Thereafter, 5iOz7 is grown on the diffusion layer by heat treatment in an atmosphere of HxO and Hz. At this time, the tungsten first gate electrode 5 is not oxidized. Thereafter, the same program as in Example 1 is run to obtain the structure shown in FIG. 3.
本実施例により、低濃度ソース・ドレイン拡散層３の形
成時の損傷を回復する事ができ、また、第２電極下のＳ
ｉ Ｏ２膜厚７が厚いのでゲートとソース・ドレイン
間のオーバラップ容量が低減できる。According to this embodiment, it is possible to recover from the damage caused during the formation of the low concentration source/drain diffusion layer 3, and also to recover the S under the second electrode.
Since the iO2 film thickness 7 is thick, the overlap capacitance between the gate and the source/drain can be reduced.
実施例３
Ｐ型Ｓｊ基板上に熱酸化法で１０ｎｍ程度の５ｉ（）ｚ
膜２を成長し、その上にスパッタ法で第１ゲート電極と
なるタングステン５を２５０ｎｍ堆積する。この材料は
モリブデン等でも良い、更にＣＶＤ法で全面に５ｉＯｚ
８を３００ｎｍ程度堆積する。写式蝕刻法あるいは電子
線描画技術を用いて、この２層膜を所望の形状にパタニ
ングする。その後は実施例２と同様のプロセスで第４図
の如き構造を得る。Example 3 Approximately 10 nm of 5i()z was deposited on a P-type Sj substrate by thermal oxidation method.
A film 2 is grown, and 250 nm of tungsten 5, which will become a first gate electrode, is deposited thereon by sputtering. This material may be molybdenum, etc., and furthermore, it is coated with 5iOz on the entire surface by CVD method.
8 is deposited to a thickness of about 300 nm. This two-layer film is patterned into a desired shape using photoetching or electron beam lithography. Thereafter, a structure as shown in FIG. 4 is obtained by the same process as in Example 2.
本実施例によれば、ソース・ドレイン形成の為のイオン
打込み時に、イオンが５ｉＯｚ中で停止するので、タン
グステンを突き抜ける心配がなくなる。According to this embodiment, when ions are implanted to form sources and drains, the ions stop at 5 iOz, so there is no fear of them penetrating tungsten.
本発明によれば、低ソース抵抗により大電流を流せ、も
れ電流も少ない高耐圧のＭＩＳＦＥＴが実現できるので
、ＭＴＳＦＥＴの微細化に極めて大きな効果を有する。According to the present invention, it is possible to realize a high breakdown voltage MISFET that allows a large current to flow with a low source resistance and has little leakage current, so it has an extremely large effect on the miniaturization of MTSFETs.
第１図は、本発明の基本構造断面とその原理を説明する
ためのバンド構造図、第２図は本発明の実施例になる半
導体装置の製造工程を説明する断面図、第３図、第４図
は本発明の他の実施例になる半導体装置の断面図である
。
１・・・ｐ型Ｓｉ、２・・・ゲート絶縁膜、コ３・・・
ｎ−拡散領域、４・・・ｎ十拡散領域、５・・・第１ゲ
ート電極、罵 １ 図
ｂ 物へ２ケ二−ト電イヨｋ
ｆ １ 図
ηＺ図
１ Ｐ−ｒｓ、基し）；ｉ：づ
ｚＳ、ρ２
３ｎ−→威
１１、 ｎ’領域
５ ７シフ′ステシ
乙 〆ｉｆ舌ｈ）９コン
Ｚ３図
不 ４ 層
７ Ｓｉρ２
Ｂ； ５ｔｌ）ｚFIG. 1 is a cross-sectional view of the basic structure of the present invention and a band structure diagram for explaining its principle. FIG. 2 is a cross-sectional diagram for explaining the manufacturing process of a semiconductor device according to an embodiment of the present invention. FIG. 4 is a sectional view of a semiconductor device according to another embodiment of the present invention. 1...p-type Si, 2...gate insulating film, 3...
n-diffusion region, 4...n10 diffusion region, 5...first gate electrode, ;i: zuzS, ρ2 3n-→Wei 11, n' area 5 7 shift 'steshi otsu 〆if tongue h) 9 con Z3 figure not 4 layer 7 Siρ2 B; 5tl) z
Claims (1)
：Ｍｅｔａｌ−Ｉｎｓｕｌａｔｏｒ−Ｓｅｍｉｃｏｎｄ
ｕｃｔｏｒ）型電界効果トランジスタにおいて、ゲート
電極が異なる仕事関数を有し、、互いに導通のとれた２
つの電極により構成され、第１のゲート電極がチャネル
部の上に存在し、第２のゲート電極が低濃度ソース・ド
レイン領域上に存在することを特徴とする半導体装置。1. MIS (Metal-Insulator-Semiconductor)
uctor) type field effect transistor, the gate electrodes have different work functions, and two
What is claimed is: 1. A semiconductor device comprising two electrodes, the first gate electrode being present on a channel portion, and the second gate electrode being present on a lightly doped source/drain region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9152688A JPH01264264A (en) | 1988-04-15 | 1988-04-15 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9152688A JPH01264264A (en) | 1988-04-15 | 1988-04-15 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01264264A true JPH01264264A (en) | 1989-10-20 |
Family
ID=14028872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9152688A Pending JPH01264264A (en) | 1988-04-15 | 1988-04-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01264264A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02116171A (en) * | 1988-10-25 | 1990-04-27 | Nec Corp | Manufacture of mos transistor |
| US6611031B2 (en) | 2000-09-28 | 2003-08-26 | Nec Corporation | Semiconductor device and method for its manufacture |
| KR100436287B1 (en) * | 2001-11-17 | 2004-06-16 | 주식회사 하이닉스반도체 | Transistor of a semiconductor device and method of manufacturing thereof |
-
1988
- 1988-04-15 JP JP9152688A patent/JPH01264264A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02116171A (en) * | 1988-10-25 | 1990-04-27 | Nec Corp | Manufacture of mos transistor |
| US6611031B2 (en) | 2000-09-28 | 2003-08-26 | Nec Corporation | Semiconductor device and method for its manufacture |
| KR100436287B1 (en) * | 2001-11-17 | 2004-06-16 | 주식회사 하이닉스반도체 | Transistor of a semiconductor device and method of manufacturing thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR0180066B1 (en) | Semiconductor device and fabrication thereof | |
| KR100495023B1 (en) | A semiconductor device and manufacturing method thereof | |
| US5272100A (en) | Field effect transistor with T-shaped gate electrode and manufacturing method therefor | |
| US5089863A (en) | Field effect transistor with T-shaped gate electrode | |
| JP2752991B2 (en) | Semiconductor device | |
| TW202030841A (en) | Gate structure of split-gate mosfet and manufacturing method thereof | |
| JPH0237777A (en) | Vertical type field-effect transistor | |
| JPS62126675A (en) | Semiconductor device and manufacture thereof | |
| JPH01264264A (en) | Semiconductor device | |
| US6150202A (en) | Method for fabricating semiconductor device | |
| JP2579954B2 (en) | MOS transistor | |
| JP2876866B2 (en) | Semiconductor device | |
| JPS5847860B2 (en) | Hand tie souchi | |
| JPS59231864A (en) | Semiconductor device | |
| JPH036060A (en) | Mis-type semiconductor device | |
| JPH0612826B2 (en) | Method of manufacturing thin film transistor | |
| JP2759472B2 (en) | Method of manufacturing high voltage MOS field effect transistor | |
| JPH02137372A (en) | Mos field-effect transistor | |
| JP2796655B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2904081B2 (en) | Method for manufacturing semiconductor device | |
| JPS6146990B2 (en) | ||
| JP3017838B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH04115538A (en) | Semiconductor device | |
| JPS5921191B2 (en) | Method for manufacturing field effect semiconductor device | |
| JP2719642B2 (en) | Semiconductor device and manufacturing method thereof |