JPH0126192B2 - - Google Patents
Info
- Publication number
- JPH0126192B2 JPH0126192B2 JP16608480A JP16608480A JPH0126192B2 JP H0126192 B2 JPH0126192 B2 JP H0126192B2 JP 16608480 A JP16608480 A JP 16608480A JP 16608480 A JP16608480 A JP 16608480A JP H0126192 B2 JPH0126192 B2 JP H0126192B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- gate
- semiconductor substrate
- mask material
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 64
- 239000000758 substrate Substances 0.000 claims description 53
- 239000012535 impurity Substances 0.000 claims description 36
- 239000000463 material Substances 0.000 claims description 27
- 238000004519 manufacturing process Methods 0.000 claims description 25
- 230000005669 field effect Effects 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 10
- 239000002184 metal Substances 0.000 description 15
- 238000000206 photolithography Methods 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 10
- 235000012431 wafers Nutrition 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Description
【発明の詳細な説明】
本発明はオフセツトゲート構造を持つ絶縁ゲー
ト型電界効果トランジスタの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an insulated gate field effect transistor having an offset gate structure.
以下では、簡単のためオフセツトゲートをOG
（Offset Gate）、絶縁ゲート型電界効果トランジ
スタをIGFET（Insulated Gate Field Effect
Transistrr）、オフセツトゲート構造のIGFETを
OG―IGFETと呼ぶ。OGのない通常のIGFETは
バイポーラ形のトランジスタに比べて、素子寸法
が小さい、入力インピーダンスが高い、製造方法
が簡単である、等の優れた特徴があるため、デイ
ジタルあるいはアナログ等各種の集積回路に広く
応用されている。集積度を増し、大規模集積回路
を実現させるためには、さらに微細化した
IGFET、所謂、HMOS（High performance
Metal―Oxide―Semiconductor）を使用する必
要がある。しかし、該HMOS―IGFETのドレイ
ンとソース間の破壊電圧、即ちドレイン耐圧は
高々10V前後である。またIGFETはデイスプレ
イ装置用駆動回路や高耐圧スイツチング回路等、
高耐圧素子への応用も考えられるが、従来の構造
ではその耐圧は高々数十Ｖ前後である。従つて、
これら大規模集積回路用の微細化IGFETやデイ
スプレイ装置用IGFETの高耐圧化が近年特に要
望されるようになつてきた。周知のように、
DSA（Diggusion Self―Alignment）構造の
IGFETあるいは第１図に示したOG―IGFET等
が開発され、素子の耐圧は飛躍的に向上してき
た。 Below, we will use the OG offset gate for simplicity.
(Offset Gate), IGFET (Insulated Gate Field Effect Transistor)
Transistrr), IGFET with offset gate structure
It is called OG-IGFET. Regular IGFETs without OG have superior characteristics compared to bipolar transistors, such as smaller element size, higher input impedance, and simpler manufacturing methods, so they are suitable for use in various integrated circuits such as digital and analog. Widely applied. In order to increase the degree of integration and realize large-scale integrated circuits, further miniaturization is required.
IGFET, so-called HMOS (High performance
Metal-Oxide-Semiconductor) must be used. However, the breakdown voltage between the drain and source of the HMOS-IGFET, ie, the drain breakdown voltage, is around 10V at most. IGFETs are also used in drive circuits for display devices, high voltage switching circuits, etc.
Application to high-voltage elements is also considered, but in conventional structures, the breakdown voltage is around several tens of volts at most. Therefore,
In recent years, there has been a particular demand for miniaturized IGFETs for large-scale integrated circuits and IGFETs for display devices to have higher voltage resistance. As is well known,
DSA (Diggusion Self-Alignment) structure
With the development of IGFETs or OG-IGFETs shown in Figure 1, the breakdown voltage of devices has improved dramatically.
第１図において、１は不純物濃度（以下簡単の
ために、単に「濃度」という）の低い半導体基板
２および３はそれぞれ該半導体基板１と異なる導
電形で高い濃度のドレイン領域およびソース領域
である。４はゲート絶縁膜、５はゲートであり、
ゲート電圧を変えることにより該ゲート直下で、
該ゲート絶縁膜と該半導体基板との境界近傍のチ
ヤネル領域６が反転層を形成し、その電気伝導が
制御される。該チヤネル領域と該ドレイン領域に
それぞれ接するように、半導体不純物層、即ち、
OG領域７が形成されている。該OG領域７は該
ドレイン領域２や該ソース領域３と同じ導電形で
あるが、濃度が異なる（通常低い濃度の）半導体
層であり、そのチヤネル方向への長さを８で示
す。 In FIG. 1, semiconductor substrates 2 and 3 with a low impurity concentration (hereinafter simply referred to as "concentration" for simplicity) 1 are a drain region and a source region, respectively, which have a conductivity type different from that of the semiconductor substrate 1 and have a high concentration. . 4 is a gate insulating film, 5 is a gate,
By changing the gate voltage, directly below the gate,
The channel region 6 near the boundary between the gate insulating film and the semiconductor substrate forms an inversion layer, and electrical conduction thereof is controlled. A semiconductor impurity layer, that is, in contact with the channel region and the drain region, respectively.
OG region 7 is formed. The OG region 7 is a semiconductor layer having the same conductivity type as the drain region 2 and the source region 3 but with a different concentration (usually a low concentration), and its length in the channel direction is indicated by 8.
９および１０はそれぞれドレイン領域およびソ
ース領域の電極である。ゲート５とソース電極１
０との間に適当な大きさのゲート電圧を印加し
て、チヤネル領域６に反転層を形成する。ドレイ
ン電極９とソース電極１０との間の電位差、即ち
ドレイン電圧が小さい場合には、ソース領域３よ
りチヤネル領域６に注入される荷電担体はさらに
OG領域７に流入し、ドレイン領域２へと流れ込
む。この場合OG領域７はドレイン領域２と全く
同じ機能を果す。ドレイン電圧が高くなると、半
導体基板１とOG領域７との接合から広がる空乏
層が該OG領域７内でピンチオフを起こす。この
ため、該OG領域７ではドレイン領域２およびソ
ース領域３方向に大きな電圧降下が生じ、チヤネ
ル領域６に加わる実効的な電圧が下がり、該チヤ
ネル領域の破壊電圧以下に制限することができ
る。このため、チヤネル領域６は破壊せず高耐圧
化が可能となる。このような構成のOG―IGFET
は、見掛け上、半導体基板１がゲート電極として
働き、OG領域７の電気伝導を制御する接合形電
界効果トランジスタとチヤネル領域６の部分に形
成されているIGFETが直列に接続された回路、
即ち、第２図に示した回路と等価であると見做せ
る。 9 and 10 are electrodes of the drain region and source region, respectively. Gate 5 and source electrode 1
An inversion layer is formed in the channel region 6 by applying a gate voltage of an appropriate magnitude between the channel region 6 and the channel region 6. When the potential difference between the drain electrode 9 and the source electrode 10, that is, the drain voltage is small, the charge carriers injected into the channel region 6 from the source region 3 are further
It flows into the OG region 7 and flows into the drain region 2. In this case, the OG region 7 performs exactly the same function as the drain region 2. When the drain voltage increases, the depletion layer expanding from the junction between the semiconductor substrate 1 and the OG region 7 causes pinch-off within the OG region 7. Therefore, a large voltage drop occurs in the OG region 7 in the direction of the drain region 2 and source region 3, and the effective voltage applied to the channel region 6 decreases, making it possible to limit the voltage to below the breakdown voltage of the channel region. For this reason, the channel region 6 is not destroyed and high voltage resistance can be achieved. OG-IGFET with this configuration
This is a circuit in which the semiconductor substrate 1 apparently acts as a gate electrode, and a junction field effect transistor that controls electrical conduction in the OG region 7 and an IGFET formed in the channel region 6 are connected in series,
That is, it can be considered to be equivalent to the circuit shown in FIG.
第２図において、１１および１２はそれぞれ前
記接合形電界効果トランジスタおよび前記
IGFETで、Ｍは両トランジスタの接続点を示し
ている。 In FIG. 2, 11 and 12 are the junction field effect transistor and the junction field effect transistor, respectively.
In the IGFET, M indicates the connection point between both transistors.
従つて、ドレイン電圧が大きくなると、接合形
電界効果トランジスタ１１がピンチオフを起し、
IGFET１２に加わる電圧、即ちＭ点とＳ（ソー
ス）端子間の電圧はそれ以後、ドレイン電圧、即
ちＤ（ドレイン）端の電圧の上昇に対してほぼ一
定となる。接合形電界効果トランジスタ１１のピ
ンチオフ電圧を適当に選べば、IGFET１２に加
わる電圧を該IGFET１２の破壊電圧以下に選ぶ
ことができる。これはドレイン電圧の増加を接合
形電界効果トランジスタ１１が吸収することによ
るものでOG―IGFETの高耐圧化が可能となる。 Therefore, when the drain voltage increases, the junction field effect transistor 11 will pinch off,
Thereafter, the voltage applied to the IGFET 12, that is, the voltage between the M point and the S (source) terminal, remains approximately constant as the drain voltage, that is, the voltage at the D (drain) terminal increases. If the pinch-off voltage of the junction field effect transistor 11 is appropriately selected, the voltage applied to the IGFET 12 can be selected to be below the breakdown voltage of the IGFET 12. This is because the junction field effect transistor 11 absorbs the increase in drain voltage, making it possible to increase the breakdown voltage of the OG-IGFET.
OG領域７（第１図）、即ち、接合形電界効果
トランジスタ１１（第２図）に流れる電流は、該
OG領域７がピンチオフを起しているか否かにか
かわらず、OG領域７の不純物量に比例し、OG
領域７のチヤネル方向への長さ８に反比例する。
従つて、OG―IGFETの高耐圧化、低オン抵抗化
を達成する目的はもとより、常に所望のデバイス
特性をばらつきなく実現させるために、OG領域
７の不純物量やチヤネル方向への長さ８を製造プ
ロセスに無関係に一定に保つことが重要である。 The current flowing through the OG region 7 (Fig. 1), that is, the junction field effect transistor 11 (Fig. 2), is
Regardless of whether or not OG region 7 is experiencing pinch-off, it is proportional to the amount of impurities in OG region 7, and OG
It is inversely proportional to the length 8 of the region 7 in the channel direction.
Therefore, in addition to achieving high breakdown voltage and low on-resistance of the OG-IGFET, in order to always achieve the desired device characteristics without variation, the amount of impurities in the OG region 7 and the length 8 in the channel direction must be adjusted. It is important to keep it constant regardless of the manufacturing process.
以上、第１図、第２図を用いてチヤネル領域６
とドレイン領域２との間にのみOG領域７を備え
たOG―IGFETを説明した。チヤネル領域６の両
側に、即ち、チヤネル領域６とドレイン領域２と
の間およびチヤネル領域６とソース領域３との間
にそれぞれOG領域７を備えたOG―IGFETの等
価回路を第３図に示す。同図において、１３はド
レイン領域とチヤネル領域間のOG領域に形成さ
れる見かけ上の接合形電界効果トランジスタ、１
４はチヤネル領域に形成されるIGFET、１５は
チヤネル領域とソース領域間のOG領域に形成さ
れる見かけ上の接合形電界効果トランジスタであ
る。該OG―IGFETは双方向性であるから、その
動作、機能は本質的に第１図あるいは第２図に示
したOG―IGFETと同様であるからここではその
説明を省略する。 As described above, using FIGS. 1 and 2, the channel area 6
An OG-IGFET with an OG region 7 only between the drain region 2 and the drain region 2 has been described. FIG. 3 shows an equivalent circuit of an OG-IGFET with OG regions 7 on both sides of the channel region 6, that is, between the channel region 6 and the drain region 2 and between the channel region 6 and the source region 3. . In the figure, 13 is an apparent junction field effect transistor formed in the OG region between the drain region and the channel region;
4 is an IGFET formed in the channel region, and 15 is an apparent junction field effect transistor formed in the OG region between the channel region and the source region. Since the OG-IGFET is bidirectional, its operation and function are essentially the same as those of the OG-IGFET shown in FIG. 1 or FIG. 2, so a description thereof will be omitted here.
第３図に示したOG―IGFETの従来用いられて
いた製造工程を、半導体基板のチヤネル方向への
断面図、第４図ａないし第４図ｅを用いて説明す
る。 The conventional manufacturing process of the OG-IGFET shown in FIG. 3 will be explained using FIGS. 4a to 4e, which are cross-sectional views of the semiconductor substrate in the channel direction.
第４図ａに示したように比較的低濃度の半導体
基板２１を準備し、該半導体基板２１の表面に絶
縁膜２２を形成する。次に第４図ｂのようにドレ
イン領域、OG領域、チヤネル領域、ソース領域
が形成される部分の絶縁膜２２を写真蝕刻技術に
より除去した後、露出した半導体基板２１の表面
に改めて絶縁膜２３を形成する。次に該絶縁膜２
３上に金属膜２４０例えば、高不純物濃度のポリ
シリコン層等を形成する。次にゲートおよびゲー
トバスラインとなる部分を残し、写真蝕刻技術を
用い、該金属膜２４０を除去すれば、第４図ｃの
ようになる。２４は該ゲートで、ゲートバスライ
ンは図示されていない。 As shown in FIG. 4a, a relatively low concentration semiconductor substrate 21 is prepared, and an insulating film 22 is formed on the surface of the semiconductor substrate 21. Next, as shown in FIG. 4b, the insulating film 22 in the portions where the drain region, OG region, channel region, and source region will be formed is removed by photolithography, and then an insulating film 23 is added on the exposed surface of the semiconductor substrate 21. form. Next, the insulating film 2
A metal film 240, such as a polysilicon layer with high impurity concentration, is formed on 3. Next, the metal film 240 is removed by photolithography, leaving the portions that will become the gates and gate bus lines, resulting in a structure as shown in FIG. 4c. 24 is the gate, and the gate bus line is not shown.
次に、半導体基板２１と異なる導電形の不純物
を拡散あるいはイオン打込み等で半導体基板２１
に導入し、半導体層２５０を形成する。該半導体
層２５０の一部が後述するOG領域２５１および
２５２となる。 Next, impurities of a conductivity type different from that of the semiconductor substrate 21 are diffused or implanted into the semiconductor substrate 21.
A semiconductor layer 250 is formed. A portion of the semiconductor layer 250 becomes OG regions 251 and 252, which will be described later.
この時、ゲート２４および厚い絶縁膜２２が該
不純物の選択マスクとして働く。次いで、ゲート
２４を含む半導体基板２１の表面に厚い絶縁膜２
６を形成し次に写真蝕刻技術を用いて第４図ｄに
示すようにドレイン領域およびゲート領域が形成
される部分の該厚い絶縁膜を除去する。次いで半
導体基板２１と異る導電形の高濃度不純物層を該
半導体基板２１中に形成し、ドレイン領域２７お
よびソース領域２８とする。なお、該ドレイン領
域およびソース領域の不純物濃度はOG領域２５
１および２５２の不純物濃度に比べ、通常は極め
て高い。次いで、絶縁膜２６の除去後、半導体基
板２１の表面に厚い絶縁膜２９を第４図ｅのよう
に形成し、写真蝕刻技術により、ドレイン領域２
７、ゲート取り出し部（図示しない）ソース領域
２８を露出する。次に、配線用金属膜を蒸着し、
再び写真蝕刻技術を用いてドレイン電極３１、ゲ
ート電極（図示しない）、ソース電極３２を形成
する。次いで、図示しないが、さらに保護用絶縁
膜を形成し、次にドレイン電極、ゲート電極ソー
ス電極が接続されているボンデイングパツドの金
属部分を露出させる。 At this time, the gate 24 and the thick insulating film 22 serve as a selective mask for the impurity. Next, a thick insulating film 2 is formed on the surface of the semiconductor substrate 21 including the gate 24.
6 is formed, and then the thick insulating film is removed by photolithography at the portions where the drain region and gate region will be formed, as shown in FIG. 4d. Next, a high concentration impurity layer of a conductivity type different from that of the semiconductor substrate 21 is formed in the semiconductor substrate 21 to serve as a drain region 27 and a source region 28 . Note that the impurity concentration of the drain region and source region is the same as that of the OG region 25.
The impurity concentration is usually extremely high compared to the impurity concentrations of 1 and 252. Next, after removing the insulating film 26, a thick insulating film 29 is formed on the surface of the semiconductor substrate 21 as shown in FIG.
7. Expose the source region 28 in the gate lead-out portion (not shown). Next, a metal film for wiring is deposited,
A drain electrode 31, a gate electrode (not shown), and a source electrode 32 are formed again using photolithography. Next, although not shown, a protective insulating film is further formed, and then the metal portion of the bonding pad to which the drain electrode, gate electrode, and source electrode are connected is exposed.
以上、従来の高耐圧化されたOG―IGFETの代
表的な製造工程を述べた。デバイス製造工程中に
生ずるウエハー間あるいはロツト間のデバイス特
性のばらつきを除去することが望ましい。このた
めには、第１図に示したOG領域７あるいは第４
図に示したOG領域２５１および２５２の不純物
量やチヤネル方向への長さを常に一定に保つこと
が必要である。該不純物量のばらつきの問題は、
イオン打込み技術を用いることにより比較的容易
に解決できる。ところが、第４図ｄで示した工程
より明らかなように、従来の製造方法ではOG領
域２５１および２５２のチヤネル方向への長さは
ゲート２４とドレイン領域２７あるいはソース領
域２８を形成するための２つの工程により決定さ
れる。このため、マスク目合せによる誤差がウエ
ハー毎に生ずるから、OG領域２５１および２５
２のチヤネル方向への長さもウエハー毎に異る値
に設定される。 The above is a typical manufacturing process for conventional high-voltage OG-IGFETs. It is desirable to eliminate wafer-to-wafer or lot-to-lot variations in device characteristics that occur during the device manufacturing process. For this purpose, the OG area 7 or the 4th area shown in FIG.
It is necessary to always keep the impurity amount and the length in the channel direction of the OG regions 251 and 252 shown in the figure constant. The problem of variation in the amount of impurities is
This problem can be solved relatively easily by using ion implantation technology. However, as is clear from the step shown in FIG. 4d, in the conventional manufacturing method, the length of the OG regions 251 and 252 in the channel direction is 2. It is determined by two steps. Therefore, since errors due to mask alignment occur for each wafer, the OG areas 251 and 25
The length of No. 2 in the channel direction is also set to a different value for each wafer.
この結果、同一駆動条件のもとでも、従来の製
造方法で作られた該OG―IGFETのドレイン電
流、ドレイン耐圧等諸特性は製造条件毎、ロツト
毎、あるいはウエハー毎に異る、という欠点、即
ち、デバイス間の特性のばらつきという重大な欠
点が生じていた。 As a result, even under the same driving conditions, the drain current, drain breakdown voltage, and other characteristics of the OG-IGFET manufactured using conventional manufacturing methods vary depending on manufacturing conditions, lots, or wafers. That is, a serious drawback arises in that characteristics vary between devices.
本発明の目的は上記欠点を取り除き、製造条件
に無関係で、かつウエハー間、ロツト間でデバイ
ス特性に差（ばらつき）のない高耐圧化された
OG―IGFETを実現するための製造方法を提供す
るものである。 The purpose of the present invention is to eliminate the above-mentioned drawbacks, and to achieve a high breakdown voltage that is independent of manufacturing conditions and has no difference (variation) in device characteristics between wafers or lots.
This provides a manufacturing method for realizing OG-IGFET.
本発明によれば、ドレイン領域とゲート電極直
下のチヤネル領域との間の半導体基板中（以下Ａ
領域という）およびソース領域と該チヤネル領域
との間の該半導体基板中（以下Ｂ領域という）に
不純物半導体層より成る第１のオフセツトゲート
領域と第２のオフセツトゲート領域をそれぞれ備
えた絶縁ゲート型電界効果トランジスタの製造方
法において、該ゲート電極の両側でドレイン領域
となる部分の該半導体基板（以下Ｃ領域という）
上およびソース領域となる部分の半導体基板（以
下Ｄ領域という）上にそれぞれ該ゲート電極と同
一の第１の導電性膜および第２の導電性膜を該ゲ
ート電極と同時に形成し、該Ａ領域および該Ｂ領
域上を絶縁膜等の第１のマスク材料でカバーした
後、該第１および該第２の導電性膜を除去し、該
Ｃ領域および該Ｄ領域を露出させるかあるいは該
第１のマスク材料より薄い膜厚の第２のマスク材
料でカバーするかして、該半導体基板中に不純物
を導入することにより、該ドレイン領域およびソ
ース領域を形成し、これと同時に、該第１および
該第２のマスク材料の膜厚の差あるいは第２のマ
スク材料の有無を用いて、該ドレイン領域および
該ソース領域の不純物濃度より低濃度の該第１の
オフセツトゲート領域および該第２のオフセツト
ゲート領域をそれぞれ該Ａ領域および該Ｂ領域に
形成することにより、該第１および該第２のオフ
セツトゲート領域のチヤネル方向への長さを該ゲ
ート電極に対し自己整合させることを特徴とした
オフセツトゲート領域を備えた絶縁ゲート型電界
効果トランジスタの製造方法が得られる。 According to the present invention, in the semiconductor substrate (hereinafter referred to as A) between the drain region and the channel region directly under the gate electrode,
an insulator comprising a first offset gate region and a second offset gate region each made of an impurity semiconductor layer in the semiconductor substrate between the source region and the channel region (hereinafter referred to as region B); In the method for manufacturing a gated field effect transistor, a portion of the semiconductor substrate that becomes a drain region on both sides of the gate electrode (hereinafter referred to as C region)
A first conductive film and a second conductive film, which are the same as the gate electrode, are respectively formed on the semiconductor substrate in the upper and source regions (hereinafter referred to as the D region) at the same time as the gate electrode, and the A region After covering the B region with a first mask material such as an insulating film, the first and second conductive films are removed to expose the C region and the D region, or The drain region and the source region are formed by introducing impurities into the semiconductor substrate by covering the semiconductor substrate with a second mask material having a thickness thinner than that of the first mask material, and at the same time, the drain region and the source region are formed. By using the difference in film thickness of the second mask material or the presence or absence of the second mask material, the first offset gate region and the second offset gate region have an impurity concentration lower than that of the drain region and the source region. By forming offset gate regions in the A region and the B region, respectively, the lengths of the first and second offset gate regions in the channel direction are self-aligned with the gate electrode. A method for manufacturing an insulated gate field effect transistor having an offset gate region having the following characteristics is obtained.
さらに本発明によれば、ドレイン領域とゲート
直下のチヤネル領域との間の半導体基板中（以下
Ａ領域という）あるいはソース領域と該チヤネル
領域との間の該半導体基板中（以下Ｂ領域とい
う）のいずれか一方に不純物半導体層より成るオ
フセツトゲート領域を備えた絶縁ゲート型電界効
果トランジスタの製造方法において、該ゲート電
極の両側で、ドレイン領域となる部分の該半導体
基板（以下Ｃ領域という）上およびソース領域と
なる部分の半導体基板（以下Ｄ領域という）上に
それぞれ該ゲート電極と同一の第１の導電性膜お
よび第２の導電性膜を該ゲート電極と同時に形成
し、該Ａ領域および該Ｂ領域上を絶縁膜等の第１
のマスク材料でカバーした後、該第１および該第
２の導電性膜を除去し、該Ｃ領域および該Ｄ領域
を露出させるかあるいは該第１のマスク材料より
薄い膜厚の第２のマスク材料でカバーするかし
て、さらに該Ａ領域上あるいは該Ｂ領域上のいず
れか一方の該第１のマスク材料を除去し、該半導
体基板中に不純物を導入することにより、該ドレ
イン領域およびソース領域を形成し、さらに該Ａ
領域あるいは該Ｂ領域のうち、該第１のマスク材
料が除去されているいずれか一方を該ドレイン領
域あるいは該ソース領域の一部とし、これと同時
に、該第１および該第２のマスク材料の膜厚の差
あるいは該第２のマスク材料の有無を利用して、
該ドレイン領域および該ソース領域の不純物濃度
より低濃度の該オフセツト領域を該第１のマスク
材料でカバーされている該Ａ領域あるいは該Ｂ領
域のいずれか一方に形成することにより、該オフ
セツトゲート領域のチヤネル方向への長さを該ゲ
ート電極に対し自己整合させることを特徴とした
オフセツトゲート領域を備えた絶縁ゲート型電界
効果トランジスタの製造方法が得られる。 Furthermore, according to the present invention, the semiconductor substrate between the drain region and the channel region directly under the gate (hereinafter referred to as A region) or the semiconductor substrate between the source region and the channel region (hereinafter referred to as B region) In a method for manufacturing an insulated gate field effect transistor having an offset gate region made of an impurity semiconductor layer on either side, a portion of the semiconductor substrate (hereinafter referred to as C region) that will become a drain region is formed on both sides of the gate electrode. A first conductive film and a second conductive film, which are the same as the gate electrode, are respectively formed on the semiconductor substrate in a portion that will become the source region (hereinafter referred to as the D region) at the same time as the gate electrode. A first film such as an insulating film is placed over the B region.
After covering with a mask material, the first and second conductive films are removed to expose the C region and the D region, or a second mask having a film thickness thinner than that of the first mask material is applied. The first mask material on either the A region or the B region is removed, and impurities are introduced into the semiconductor substrate, thereby forming the drain region and the source region. A region is formed, and the A
Either the region or the B region from which the first mask material has been removed is made a part of the drain region or the source region, and at the same time, the first and second mask materials are removed. Utilizing the difference in film thickness or the presence or absence of the second mask material,
By forming the offset region having an impurity concentration lower than that of the drain region and the source region in either the A region or the B region covered with the first mask material, the offset gate is formed. A method for manufacturing an insulated gate field effect transistor having an offset gate region is obtained, in which the length of the region in the channel direction is self-aligned with the gate electrode.
以下では、チヤネル方向への断面図を第５図ａ
ないし第５図ｆを用いて本発明の製造方法の実施
例を説明する。本実施例では一例としてゲート電
極の両側にOG領域を備えたOG―IGFET（第３図
参照）を用いることにする。 Below, a cross-sectional view in the channel direction is shown in Figure 5a.
An embodiment of the manufacturing method of the present invention will be described using FIGS. In this embodiment, an OG-IGFET (see FIG. 3) having OG regions on both sides of the gate electrode is used as an example.
まず、第５図ａに示すように、比較的低濃度の
半導体基板、例えば不純物濃度が１立方cm当り
1015程度のシリコン基板を準備し、該半導体基板
４１の表面に、例えば厚さ１ミクロンの絶縁膜４
２を形成する。 First, as shown in Figure 5a, a semiconductor substrate with a relatively low concentration, for example, an impurity concentration per cubic cm.
A silicon substrate of about 10 15 is prepared, and an insulating film 4 with a thickness of 1 micron, for example, is placed on the surface of the semiconductor substrate 41.
form 2.
次に、第５図ｂに示すように、ドレイン領域、
OG領域、チヤネル領域、ソース領域が形成され
る部分の絶縁膜４２を写真蝕刻技術により除去す
る。 Next, as shown in FIG. 5b, the drain region,
The portions of the insulating film 42 where the OG region, channel region, and source region will be formed are removed by photolithography.
次に、露出した半導体基板４１の表面に絶縁膜
４３例えば厚さ400ないし1000オングストローム
のシリコン酸化膜を形成した後、該絶縁膜４３上
に、厚さ約5000オングストロームの金属膜４４、
例えば高濃度に不純物が導入され電気導通性の優
れたポリシリコン層を形成する。さらに、該金属
膜４４に絶縁膜４５、例えばシリコン酸化膜ある
いはシリコン窒化膜等を形成する。 Next, an insulating film 43, for example, a silicon oxide film with a thickness of 400 to 1000 angstroms, is formed on the exposed surface of the semiconductor substrate 41, and then a metal film 44 with a thickness of about 5000 angstroms is formed on the insulating film 43.
For example, impurities are introduced at a high concentration to form a polysilicon layer with excellent electrical conductivity. Furthermore, an insulating film 45, such as a silicon oxide film or a silicon nitride film, is formed on the metal film 44.
次に、第５図ｃに示したように、写真蝕刻技術
を用い、ゲート電極４４１と図示されないゲート
バスラインとされる部分の導電性膜、第１の導電
性膜４４２、第２の金属膜４４３およびこれら導
電性膜の上下にある絶縁膜４３および４５を除去
する。 Next, as shown in FIG. 5c, a photolithography technique is used to remove the gate electrode 441, the conductive film at the gate bus line (not shown), the first conductive film 442, and the second metal film. 443 and the insulating films 43 and 45 above and below these conductive films are removed.
次に、第５図ｄに示すように、半導体基板４１
の露出した表面にのみ絶縁膜４８を形成する。該
絶縁膜４８と該絶縁膜４３が共に同一絶縁材料、
例えば、シリコン酸化膜であつてもよい。この場
合、該絶縁膜４８の膜厚を該絶縁膜４３のそれに
比べ大きい値とする。写真蝕刻技術を用いて、絶
縁膜４５２，４５３該第１の導電性膜４４２と第
２の導電性膜４４３を順次除去すれば第５図ｅに
示すようになる。この時、絶縁膜４５１も除去し
てもかまわない。 Next, as shown in FIG. 5d, the semiconductor substrate 41
An insulating film 48 is formed only on the exposed surface. Both the insulating film 48 and the insulating film 43 are made of the same insulating material,
For example, it may be a silicon oxide film. In this case, the thickness of the insulating film 48 is made larger than that of the insulating film 43. If the insulating films 452, 453, the first conductive film 442 and the second conductive film 443 are sequentially removed using photolithography, the result will be as shown in FIG. 5e. At this time, the insulating film 451 may also be removed.
次に、薄い絶縁膜４３および厚い絶縁膜４８を
介して該絶縁膜直下の半導体基板４１の表面近傍
に該半導体基板４１と異なる導電形の不純物を導
入し、薄い絶縁膜４３直下に高濃度の、例えば１
平方cm当り５×1015の不純物半導体層、即ちドレ
イン領域４９とソース領域５０および厚い絶縁膜
４８直下に、低濃度の、例えば１平方cm当り１×
1012の不純物半導体層即ち、第１のOG領域４６
と第２のOG領域４７を同時に形成する。この
時、ゲート４４１、十分厚い絶縁膜４２が該不純
物の選択マスクとして働くから、これら４４１、
４２直下の半導体基板中には該不純物半導体層は
形成されない。 Next, an impurity of a conductivity type different from that of the semiconductor substrate 41 is introduced into the vicinity of the surface of the semiconductor substrate 41 directly under the insulating film through the thin insulating film 43 and the thick insulating film 48, and a high concentration impurity is introduced directly under the thin insulating film 43. , for example 1
An impurity semiconductor layer of 5×10 15 per square cm, that is, directly under the drain region 49, source region 50, and thick insulating film 48, has a low concentration of, for example, 1×
10 12 impurity semiconductor layers, that is, the first OG region 46
and the second OG region 47 are formed at the same time. At this time, since the gate 441 and the sufficiently thick insulating film 42 act as selective masks for the impurities, these 441,
The impurity semiconductor layer is not formed in the semiconductor substrate immediately below 42.
次に、第５図ｆに示すように、絶縁膜４５１を
除去した後、表面に厚い絶縁膜５１を形成し、写
真蝕刻技術により、該絶縁膜に穴をあけ、ドレイ
ン領域４９、図示しないゲート取り出し部分、ソ
ース領域５０を露出させる。次に配線用金属膜を
蒸着し、再び写真蝕刻技術によりドレイン電極５
２、図示しないゲート電極、ソース電極５３を形
成する。次いで、図示しない絶縁膜をさらに形成
した後、該ドレイン電極５２、ゲート電極、ソー
ス電極５３が接続されているボンデイングパツド
の金属部分を露出させる。 Next, as shown in FIG. 5f, after removing the insulating film 451, a thick insulating film 51 is formed on the surface, and a hole is made in the insulating film by photolithography to form a drain region 49 and a gate (not shown). The extraction portion, the source region 50, is exposed. Next, a metal film for wiring is deposited, and the drain electrode 5 is again formed by photolithography.
2. Form a gate electrode and source electrode 53 (not shown). Next, after further forming an insulating film (not shown), the metal portion of the bonding pad to which the drain electrode 52, gate electrode, and source electrode 53 are connected is exposed.
以上の説明では、OG領域がゲートの両側に各
１個ずつ設けられた構造のOG―IGFET（第３図
参照）の製造方法を説明した。ゲート電極の左側
にのみOG領域を備えたOG―IGFET（第１図参
照）の場合も、第５図ｅにおいて絶縁膜４８１あ
るいは４８２のいずれか一方を写真蝕刻技術を用
いて除去することにより、上記と全く同様な製造
方法が適用される。今、例えば絶縁膜４８１を除
去するとする。次に、前記同様該半導体基板４１
と異なる導電形の不純物を導入すれば、第５図ｅ
において、既に除去された該絶縁膜４８１直下の
半導体基板中にもドレイン領域が形成される。一
方、ソース領域５０および除去しない絶縁膜４８
２直下に該第２のOG領域４７は前記と同様に形
成される。 In the above explanation, a method for manufacturing an OG-IGFET (see FIG. 3) having a structure in which one OG region is provided on each side of the gate has been described. Even in the case of an OG-IGFET with an OG region only on the left side of the gate electrode (see Figure 1), by removing either the insulating film 481 or 482 using photolithography in Figure 5e, The same manufacturing method as above is applied. Now, for example, assume that the insulating film 481 is to be removed. Next, as above, the semiconductor substrate 41
If we introduce an impurity with a conductivity type different from
In this step, a drain region is also formed in the semiconductor substrate immediately below the insulating film 481 that has already been removed. On the other hand, the source region 50 and the insulating film 48 that are not removed
The second OG region 47 is formed directly below the second OG region 47 in the same manner as described above.
以上本発明の実施例を説明した。 The embodiments of the present invention have been described above.
本発明によれば、ゲート電極の両側に第１およ
び第２の金属膜を該ゲート電極と同時に形成し、
該ゲート電極と第１の金属膜および該ゲート電極
と第２の金属膜との間の半導体基板中の両方に第
１および第２のオフセツトゲート領域を形成し、
次に第１の導電性膜および第２の導電性膜直下の
半導体基板中にそれぞれドレイン領域およびソー
ス領域を形成することにより、ゲート電極とドレ
イン領域およびゲート電極とソース領域に対しそ
れぞれ自己整合された第１および第２のOG領域
が形成される。従つて、OG領域のチヤネル方向
への長さは常に設計値通りとなり、製造条件の違
いによるばらつきは全く生じない。 According to the present invention, the first and second metal films are simultaneously formed on both sides of the gate electrode,
forming first and second offset gate regions in both the semiconductor substrate between the gate electrode and the first metal film and between the gate electrode and the second metal film;
Next, by forming a drain region and a source region in the semiconductor substrate directly under the first conductive film and the second conductive film, respectively, self-alignment is achieved with respect to the gate electrode and the drain region and the gate electrode and the source region, respectively. First and second OG regions are formed. Therefore, the length of the OG region in the channel direction is always the same as the designed value, and there is no variation due to differences in manufacturing conditions.
言い換えれば、デバイス相互間、ウエハー間、
ロツト間で、OG領域のチヤネル方向への長さの
ばらつきは全く生じることがないから、特性が均
一で、かつ優れ、歩留りの高いデバイスを実現で
きる。さらに、本発明によれば、OG領域のチヤ
ネル方向への長さはゲート電極と第１の導電性膜
およびゲート電極と第２の導電性膜との距離で与
えられるから、OG領域の長さを自由に選択・設
計ができる。さらに該ゲート電極と該導電性膜と
の間隔距離は加工技術の向上に伴い飛躍的に小さ
くすることができるから高耐圧大電力用OG―
IGFETのみばかりか、大規模集積回路用の微細
素子として極めて有利である。さらに本発明によ
れば、前記の様にOG領域の長さは各デバイス間
で全く等しい上、OG領域の不純物濃度もイオン
打込み等により極めて正確に得られるから、デバ
イス特性のばらつきに対するマージンをあまり考
慮する必要はない。従つてデバイスのスイツチン
グスピード、周波特性、オフセツト電圧、歪特性
等も設計値と等しいか、極めて近い値が得られ
る。なお、ゲート電極の片側にのみOG領域を備
えたOG―IGFETにおいても前記特徴が達成され
ることは明らかである。 In other words, between devices, between wafers,
Since there is no variation in the length of the OG region in the channel direction between lots, it is possible to realize devices with uniform and excellent characteristics and a high yield. Further, according to the present invention, since the length of the OG region in the channel direction is given by the distance between the gate electrode and the first conductive film and between the gate electrode and the second conductive film, the length of the OG region can be freely selected and designed. Furthermore, the distance between the gate electrode and the conductive film can be dramatically reduced as processing technology improves.
It is extremely advantageous not only as an IGFET but also as a fine element for large-scale integrated circuits. Furthermore, according to the present invention, as mentioned above, the length of the OG region is exactly the same for each device, and the impurity concentration of the OG region can be obtained extremely accurately by ion implantation, etc., so there is little margin for variations in device characteristics. There is no need to consider it. Therefore, the switching speed, frequency characteristics, offset voltage, distortion characteristics, etc. of the device can be equal to or extremely close to the designed values. Note that it is clear that the above characteristics can also be achieved in an OG-IGFET having an OG region only on one side of the gate electrode.
なお、以上述べた実施例で用いて絶縁膜や金属
膜の材質および膜厚、不純物の種類や濃度等は一
例であつて、これらの値に限定されず本発明の機
能が達成されれば、どのような値でもかまわな
い。 Note that the materials and thicknesses of the insulating films and metal films used in the embodiments described above, the types and concentrations of impurities, etc. are merely examples, and are not limited to these values, as long as the functions of the present invention are achieved. It can be any value.
さらに絶縁膜、金属膜、ドレイン領域、ソース
領域、OG領域の形成方法あるいは写真蝕刻技術
の方法も上記目的が達成されればどのような方法
を用いてもかまわない。 Furthermore, any method of forming the insulating film, metal film, drain region, source region, OG region, or photolithography may be used as long as the above object is achieved.
第１図は高耐圧化されたオフセツトゲート
（OG）構造の絶縁ゲート型電界効果トランジス
タ（IGFET）の構造を示す模式図で、ゲート電
極の片側にのみOG領域がある場合の一例、第２
図は第１図に示したOG―IGFETの等価回路であ
る。第３図はゲート電極の両側にOG領域を持つ
OG形IGFETの等価回路である。第４図ａないし
第４図ｅは第３図に示したOG―IGFETを形成す
るための製造工程を示した従来例である。第５図
ａないし第５図ｆはOG―IGFETを形成するため
の製造工程を示す本発明の一実施例で、第３図に
示したOG―IGFETを一例に用いている。
第１図において、１は半導体基板、２はドレイ
ン領域、３はソース領域、４はゲート絶縁膜、５
はゲート電極、６はチヤネル領域、７はオフセツ
トゲート領域、８はオフセツトゲート領域のチヤ
ネル方向への長さ、９および１０はそれぞれドレ
イン電極およびゲート電極である。
第２図および第３図において、１１，１３，１
５は接合形電界効果トランジスタ、１２，１４は
絶縁ゲート型電界効果トランジスタである。
第４図において、２１は半導体基板、２２，２
３，２６，２９は絶縁膜、２４０，２４は金属
膜、２５１，２５２はオフセツトゲート領域、２
７はドレイン領域、２８はソース領域、３１はド
レイン電極、３２はソース電極である。
第５図において、４１は半導体基板、４２，４
３，４５，４８１，４８２，５１は絶縁膜、４
４，４４１，４４２，４４３は導電性膜、特に４
４１はゲート電極、４９はドレイン領域、５０は
ソース領域、４６，４７はオフセツトゲート領
域、５２はドレイン電極、５３はソース電極であ
る。
Figure 1 is a schematic diagram showing the structure of an insulated gate field effect transistor (IGFET) with a high withstand voltage offset gate (OG) structure.
The figure is an equivalent circuit of the OG-IGFET shown in Figure 1. Figure 3 has OG regions on both sides of the gate electrode.
This is an equivalent circuit of an OG type IGFET. FIGS. 4a to 4e show a conventional example of a manufacturing process for forming the OG-IGFET shown in FIG. 3. FIGS. 5a to 5f show an embodiment of the present invention showing a manufacturing process for forming an OG-IGFET, using the OG-IGFET shown in FIG. 3 as an example. In FIG. 1, 1 is a semiconductor substrate, 2 is a drain region, 3 is a source region, 4 is a gate insulating film, and 5 is a semiconductor substrate.
is a gate electrode, 6 is a channel region, 7 is an offset gate region, 8 is the length of the offset gate region in the channel direction, and 9 and 10 are a drain electrode and a gate electrode, respectively. In Figures 2 and 3, 11, 13, 1
5 is a junction field effect transistor, and 12 and 14 are insulated gate field effect transistors. In FIG. 4, 21 is a semiconductor substrate, 22, 2
3, 26, 29 are insulating films, 240, 24 are metal films, 251, 252 are offset gate regions, 2
7 is a drain region, 28 is a source region, 31 is a drain electrode, and 32 is a source electrode. In FIG. 5, 41 is a semiconductor substrate, 42, 4
3, 45, 481, 482, 51 are insulating films, 4
4,441,442,443 are conductive films, especially 4
41 is a gate electrode, 49 is a drain region, 50 is a source region, 46 and 47 are offset gate regions, 52 is a drain electrode, and 53 is a source electrode.
Claims (1)
域との間の半導体基板中（以下Ａ領域という）お
よびソース領域と該チヤネル領域との間の該半導
体基板中（以下Ｂ領域という）に不純物半導体層
より成る第１のオフセツトゲート領域と第２のオ
フセツトゲート領域をそれぞれ備えた絶縁ゲート
型電界効果トランジスタの製造方法において、該
ゲート電極の両側でドレイン領域となる部分の該
半導体基板（以下Ｃ領域という）上およびソース
領域となる部分の半導体基板（以下Ｄ領域とい
う）上にそれぞれ該ゲート電極と同一の第１の導
電性膜および第２の導電性膜を該ゲート電極と同
時に形成し、該Ａ領域および該Ｂ領域上を絶縁膜
等の第１のマスク材料でカバーした後、該第１お
よび該第２の導電性膜を除去し、該Ｃ領域および
該Ｄ領域を露出させるかあるいは該第１のマスク
材料より薄い膜厚の第２のマスク材料でカバーす
るかして、該半導体基板中に不純物を導入するこ
とにより、該ドレイン領域およびソース領域を形
成し、これと同時に、該第１および該第２のマス
ク材料の膜厚の差あるいは第２のマスク材料の有
無を用いて、該ドレイン領域および該ソース領域
の不純物濃度より低濃度の該第１のオフセツトゲ
ート領域および該第２のオフセツトゲート領域を
それぞれ該Ａ領域および該Ｂ領域に形成すること
により、該第１および該第２のオフセツトゲート
領域のチヤネル方向への長さを該ゲート電極に対
し自己整合させることを特徴としたオフセツトゲ
ート領域を備えた絶縁ゲート型電界効果トランジ
スタの製造方法。 ２ ドレイン領域とゲート直下のチヤネル領域と
の間の半導体基板中（以下Ａ領域という）あるい
はソース領域と該チヤネル領域との間の該半導体
基板中（以下Ｂ領域という）のいずれか一方に不
純物半導体層より成るオフセツトゲート領域を備
えた絶縁ゲート型電界効果トランジスタの製造方
法において、該ゲート電極の両側で、ドレイン領
域となる部分の該半導体基板（以下Ｃ領域とい
う）上およびソース領域となる部分の半導体基板
（以下Ｄ領域という）上にそれぞれ該ゲート電極
と同一の第１の導電性膜および第２の導電性膜を
該ゲート電極と同時に形成し、該Ａ領域および該
Ｂ領域上を絶縁膜等の第１のマスク材料でカバー
した後、該第１および該第２の導電性膜を除去
し、該Ｃ領域および該Ｄ領域を露出させるかある
いは該第１のマスク材料より薄い膜厚の第２のマ
スク材料でカバーするかして、さらに該Ａ領域上
あるいは該Ｂ領域上のいずれか一方の該第１のマ
スク材料を除去し、該半導体基板中に不純物を導
入することにより、該ドレイン領域およびソース
領域を形成し、さらに該Ａ領域あるいは該Ｂ領域
のうち、該第１のマスク材料が除去されているい
ずれか一方を該ドレイン領域あるいは該ソース領
域の一部とし、これと同時に、該第１および該第
２のマスク材料の膜厚の差あるいは該第２のマス
ク材料の有無を利用して、該ドレイン領域および
該ソース領域の不純物濃度より低濃度の該オフセ
ツト領域を該第１のマスク材料でカバーされてい
る該Ａ領域あるいは該Ｂ領域のいずれか一方に形
成することにより、該オフセツトゲート領域のチ
ヤネル方向への長さを該ゲート電極に対し自己整
合させることを特徴としたオフセツトゲート領域
を備えた絶縁ゲート型電界効果トランジスタの製
造方法。[Claims] 1. In the semiconductor substrate between the drain region and the channel region directly under the gate electrode (hereinafter referred to as A region) and in the semiconductor substrate between the source region and the channel region (hereinafter referred to as B region) In a method of manufacturing an insulated gate field effect transistor having a first offset gate region and a second offset gate region each made of an impurity semiconductor layer, the semiconductor in a portion to become a drain region on both sides of the gate electrode. A first conductive film and a second conductive film, which are the same as the gate electrode, are provided on the substrate (hereinafter referred to as C region) and on the semiconductor substrate in a portion that will become the source region (hereinafter referred to as D region), respectively. After covering the A region and the B region with a first mask material such as an insulating film, the first and second conductive films are removed, and the C region and the D region are covered with a first mask material such as an insulating film. forming the drain region and the source region by introducing impurities into the semiconductor substrate by exposing them or covering them with a second mask material having a thickness thinner than that of the first mask material; At the same time, by using the difference in film thickness between the first and second mask materials or the presence or absence of the second mask material, the first offset having an impurity concentration lower than that of the drain region and the source region is formed. By forming the gate region and the second offset gate region in the A region and the B region, respectively, the lengths of the first and second offset gate regions in the channel direction are made similar to the gate electrode. A method for manufacturing an insulated gate field effect transistor having an offset gate region characterized by self-alignment. 2. An impurity semiconductor is added to either the semiconductor substrate between the drain region and the channel region directly under the gate (hereinafter referred to as A region) or the semiconductor substrate between the source region and the channel region (hereinafter referred to as B region). In a method of manufacturing an insulated gate field effect transistor having an offset gate region consisting of a layer, on both sides of the gate electrode, a portion of the semiconductor substrate that will become a drain region (hereinafter referred to as C region) and a portion that will become a source region. A first conductive film and a second conductive film, each of which is the same as the gate electrode, are formed on the semiconductor substrate (hereinafter referred to as D region) at the same time as the gate electrode, and the A region and the B region are insulated. After covering with a first mask material such as a film, the first and second conductive films are removed to expose the C region and the D region, or a film with a thinner film thickness than the first mask material. By covering the semiconductor substrate with a second mask material, and then removing the first mask material on either the A region or the B region, and introducing impurities into the semiconductor substrate, The drain region and the source region are formed, and either the A region or the B region from which the first mask material has been removed is made a part of the drain region or the source region, and At the same time, by utilizing the difference in film thickness between the first and second mask materials or the presence or absence of the second mask material, the offset region having an impurity concentration lower than that of the drain region and the source region is targeted. By forming the offset gate region in either the A region or the B region covered with the first mask material, the length of the offset gate region in the channel direction can be self-aligned with the gate electrode. A method for manufacturing an insulated gate field effect transistor with a characteristic offset gate region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16608480A JPS5789257A (en) | 1980-11-25 | 1980-11-25 | Manufacture of insulation gate type field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16608480A JPS5789257A (en) | 1980-11-25 | 1980-11-25 | Manufacture of insulation gate type field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5789257A JPS5789257A (en) | 1982-06-03 |
| JPH0126192B2 true JPH0126192B2 (en) | 1989-05-22 |
Family
ID=15824681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16608480A Granted JPS5789257A (en) | 1980-11-25 | 1980-11-25 | Manufacture of insulation gate type field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5789257A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6064473A (en) * | 1983-09-20 | 1985-04-13 | Seiko Epson Corp | Mos type transistor |
-
1980
- 1980-11-25 JP JP16608480A patent/JPS5789257A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5789257A (en) | 1982-06-03 |
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