JPH01248510A - Semiconductor chip and semiconductor device using same - Google Patents
Semiconductor chip and semiconductor device using sameInfo
- Publication number
- JPH01248510A JPH01248510A JP63077575A JP7757588A JPH01248510A JP H01248510 A JPH01248510 A JP H01248510A JP 63077575 A JP63077575 A JP 63077575A JP 7757588 A JP7757588 A JP 7757588A JP H01248510 A JPH01248510 A JP H01248510A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- resin
- semiconductor
- semiconductor device
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 239000011347 resin Substances 0.000 claims abstract description 27
- 229920005989 resin Polymers 0.000 claims abstract description 27
- 239000000853 adhesive Substances 0.000 abstract description 3
- 230000001070 adhesive effect Effects 0.000 abstract description 3
- 230000005496 eutectics Effects 0.000 abstract description 3
- 229910015365 Au—Si Inorganic materials 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 238000000465 moulding Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体チップおよびこの半導体チップを用い
たプラスチックパッケージ型の半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor chip and a plastic package type semiconductor device using the semiconductor chip.
従来の技術
従来、樹脂モールドによる１チツプＬＳＩの実装法とし
ては、第３図に示すようにリードフレーム１１のダイア
タッチ部１２の上に半導体チップ１３をＡＵ−Ｓ；共晶
あるいはＡ（Ｊペーストなどの接着材によりマウントし
た後、半導体チップ１３の端子とリードフレーム１１の
リード部１１ａの端子間をワイヤボンディングし、その
後、半導体チップ１３をマウントしたリードフレーム１
１を金型にセットし、樹脂１４を注入し、半導体チップ
１３をモールドして第４図に示すようなプラスチックパ
ッケージ型の半導体装置を形成するものである。第４図
は樹脂モールド後の第３図Ｂ−Ｂ断面図である。2. Description of the Related Art Conventionally, as shown in FIG. 3, a semiconductor chip 13 is mounted on a die attach portion 12 of a lead frame 11 using an AU-S; eutectic or A (J paste) for mounting a one-chip LSI using a resin mold. After mounting the semiconductor chip 13 with an adhesive such as, wire bonding is performed between the terminals of the semiconductor chip 13 and the terminals of the lead part 11a of the lead frame 11, and then the lead frame 1 on which the semiconductor chip 13 is mounted.
1 is set in a mold, a resin 14 is injected, and a semiconductor chip 13 is molded to form a plastic package type semiconductor device as shown in FIG. FIG. 4 is a sectional view taken along line BB in FIG. 3 after resin molding.
発明が解決しようとする課題
近年、微細加工技術の進歩により、ＬＳＩチップの集積
度が向上し、ＬＳＩチップ自身が大チップ化の方向にあ
るが、モールド樹脂１４の大きさは従来と同じである。Problems to be Solved by the Invention In recent years, with advances in microfabrication technology, the degree of integration of LSI chips has improved, and LSI chips themselves are becoming larger in size, but the size of the molding resin 14 remains the same as before. .
すなわち、ＩＣパッケージの大きさは従来の規格に従う
ものであるが、半導体チップ１３のサイズのみが大きく
なったため、モールド樹脂１４と半導体チップ１３の熱
膨張率の相違により、従来では生じなかったような、樹
脂モールド部のクラックまたは半導体チップ上のパター
ンシフト、ワイヤ断線などが発生する不都合が生じた。In other words, although the size of the IC package complies with conventional standards, only the size of the semiconductor chip 13 has increased, and due to the difference in thermal expansion coefficient between the mold resin 14 and the semiconductor chip 13, a However, problems such as cracks in the resin mold, pattern shifts on the semiconductor chip, and wire breakage occurred.
本発明は、このような問題を解決するもので、上記熱膨
張率の相違により発生する不都合を解消した半導体チッ
プおよび半導体装置の提供を目的とするものである。The present invention is intended to solve such problems, and aims to provide a semiconductor chip and a semiconductor device that eliminate the disadvantages caused by the difference in thermal expansion coefficients.
課題を解決するための手段
上記課題を解決するために本発明は、半導体チップの周
辺部に消を設けたものである。また本発明の半導体装置
は上記半導体チップを樹脂封止したものである。Means for Solving the Problems In order to solve the above problems, the present invention provides an eraser in the periphery of a semiconductor chip. Further, the semiconductor device of the present invention is one in which the above-mentioned semiconductor chip is sealed with a resin.
作用
上記構成により、半導体チップに設けた溝に樹脂がくい
込み、樹脂と半導体チップ間に生じる応力のミスマツチ
ングを緩和するように作用し、樹脂モールド部のクラッ
クや半導体チップ上のパターンシフト、ワイヤ断線など
は発生しなくなる。Effect: With the above configuration, the resin sinks into the grooves provided in the semiconductor chip, and acts to alleviate stress mismatching that occurs between the resin and the semiconductor chip, thereby preventing cracks in the resin mold, pattern shifts on the semiconductor chip, wire breakage, etc. will no longer occur.
実施例 以下、本発明の一実施例を図面に基づき説明する。Example Hereinafter, one embodiment of the present invention will be described based on the drawings.
第１図は本発明の一実施例を示すモールド前の半導体装
置の平面図である。第１図において、１はリードフレー
ム２のダイアタッチ部３の上にＡｕ−３ｉ共晶あるいは
Ａｇペーストなどの接着材によりマウントされた半導体
チップで、従来のものより大型化されている。この半導
体チップ１の周辺部上面には凹形の渭４が形成されてい
る。FIG. 1 is a plan view of a semiconductor device before molding, showing one embodiment of the present invention. In FIG. 1, a semiconductor chip 1 is mounted on a die attach portion 3 of a lead frame 2 with an adhesive such as Au-3i eutectic or Ag paste, and is larger than the conventional chip. A concave edge 4 is formed on the upper surface of the peripheral portion of the semiconductor chip 1.
５は半導体チップ１の端子とリードフレーム２のリード
部２ａの端子との間をワイヤボンディングにより接続す
るリードワイヤである。６は第２図に示すようにこれら
をモールドした樹脂で、第１図における点線部はモール
ドされた樹脂６の外形を示す、この樹脂６には、半導体
チップ１の涌４にくい込むことによりその位置に突部７
が形成される。5 is a lead wire that connects the terminal of the semiconductor chip 1 and the terminal of the lead portion 2a of the lead frame 2 by wire bonding. 6 is a resin in which these are molded as shown in FIG. 2, and the dotted line in FIG. Protrusion 7 at position
is formed.
上記構成によれば、半導体チップ１の？ＩＩ４と樹脂６
の突部７とが係合するため、熱膨張率の相違により半導
体チップ１と樹脂６との相対的なずれが防止される。し
たがって樹脂６と半導体チップ１の間に生じる応力のミ
スマツチングを緩和するように作用し、樹脂モールド部
のクラックや半導体チップ１のパターンシフト、ワイヤ
断線などの発生は防止される。According to the above configuration, the ? II4 and resin 6
Since the protrusions 7 engage with each other, relative displacement between the semiconductor chip 1 and the resin 6 is prevented due to the difference in coefficient of thermal expansion. Therefore, it acts to alleviate stress mismatching occurring between the resin 6 and the semiconductor chip 1, and prevents cracks in the resin mold, pattern shifts in the semiconductor chip 1, wire breakage, etc.
なお、渭４の位置は半導体チップ１の周辺部に近い箇所
はど効果があり、消４の断面形状は角形状、Ｖ字状、円
弧状、などいずれでもよく、消４の形状や深さなどは効
果が大きくなるように選択するとよい。Note that the position of the cross section 4 is close to the periphery of the semiconductor chip 1 due to the effect, and the cross-sectional shape of the cross section may be square, V-shaped, arc-shaped, etc., and the shape and depth of the cross section may vary. etc. should be selected to maximize the effect.
発明の詳細
な説明したように、本発明によれば半導体チップの周辺
部に溝を設けたため、樹脂と半導体チップ間にかかる応
力のミスマツチングを緩和するように作用し、半導体チ
ップが大型化しても樹脂モールドクラックや半導体チッ
プ上のパターンシフト、ワイヤ断線などの発生を防ぐこ
とができる。As described in detail, according to the present invention, the grooves are provided at the periphery of the semiconductor chip, which acts to alleviate stress mismatching between the resin and the semiconductor chip, and even when the semiconductor chip becomes larger. It is possible to prevent the occurrence of resin mold cracks, pattern shifts on semiconductor chips, wire breaks, etc.
第１図は本発明の一実施例を示す樹脂モールド前の半導
体装置の平面図、第２図は樹脂モールド後の同半導体装
置の第１図におけるＡ−Ａ断面図、第３図は従来の樹脂
モールド前の半導体装置の平面図、第４図は従来樹脂モ
ールド後の半導体装置の第３図におけるＢ−Ｂ断面図で
ある。
１・・・半導体チップ、２・・・リードフレーム、３・
・・ダイアタッチ部、４・・・清、５・・・リードワイ
ヤ、６・・・樹脂、７・・・突部。
代理人 森 本 義 弘
第１図
第２図
第３図
第４図
１’；） ／４FIG. 1 is a plan view of a semiconductor device before resin molding showing an embodiment of the present invention, FIG. 2 is a sectional view taken along line A-A in FIG. 1 of the same semiconductor device after resin molding, and FIG. 3 is a conventional FIG. 4 is a plan view of the semiconductor device before resin molding, and a sectional view taken along line BB in FIG. 3 of the semiconductor device after conventional resin molding. 1... Semiconductor chip, 2... Lead frame, 3...
...Die attach portion, 4...Clear, 5...Lead wire, 6...Resin, 7...Protrusion. Agent Yoshihiro Morimoto Figure 1 Figure 2 Figure 3 Figure 4 Figure 1';) /4
Claims (1)
半導体装置。[Claims] 1. A semiconductor chip having a groove in its periphery. 2. A semiconductor device in which the semiconductor chip according to claim 1 is sealed with a resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63077575A JPH01248510A (en) | 1988-03-29 | 1988-03-29 | Semiconductor chip and semiconductor device using same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63077575A JPH01248510A (en) | 1988-03-29 | 1988-03-29 | Semiconductor chip and semiconductor device using same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01248510A true JPH01248510A (en) | 1989-10-04 |
Family
ID=13637797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63077575A Pending JPH01248510A (en) | 1988-03-29 | 1988-03-29 | Semiconductor chip and semiconductor device using same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01248510A (en) |
-
1988
- 1988-03-29 JP JP63077575A patent/JPH01248510A/en active Pending
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