KR0119764Y1 - Semiconductor package - Google Patents

Semiconductor package

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Publication number
KR0119764Y1
KR0119764Y1 KR2019910022567U KR910022567U KR0119764Y1 KR 0119764 Y1 KR0119764 Y1 KR 0119764Y1 KR 2019910022567 U KR2019910022567 U KR 2019910022567U KR 910022567 U KR910022567 U KR 910022567U KR 0119764 Y1 KR0119764 Y1 KR 0119764Y1
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KR
South Korea
Prior art keywords
chip
lead frame
semiconductor package
semiconductor
lead
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KR2019910022567U
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Korean (ko)
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KR930016250U (en
Inventor
고준수
Original Assignee
문정환
금성일렉트론주식회사
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Priority to KR2019910022567U priority Critical patent/KR0119764Y1/en
Publication of KR930016250U publication Critical patent/KR930016250U/en
Application granted granted Critical
Publication of KR0119764Y1 publication Critical patent/KR0119764Y1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

본 고안은 반도체 패키지 구조에 관한것으로, 반도체 칩과 그 반도체 칩이 부착고정되는 패들이 구비됨과 아울러 인너리드 및 아웃리드가 구비된 리드프레임과, 상기 반도체 칩의 다이어래치를 위한 접착제와, 다이어래치된 칩의 본드패드와 상기 리드프레임의 인너리드를 연결하는 금속와이어, 와이어본딩된 칩을 밀폐시키는 에폭시 몰딩 컴파운드로 구성된 반도체 패키지에 있어서, 반도체 칩이 고정되는 상기 리드프레임의 패들중심부에 방열공을 형성하고, 가장자리에는 칩안착을 위한 단턱을 형성하여 열적안정 및 방열효과를 도모한 것임을 특징으로 하는 반도체 패키지이다.The present invention relates to a semiconductor package structure, including a semiconductor chip and a paddle to which the semiconductor chip is attached and fixed, a lead frame provided with an inner lead and an out lead, an adhesive for the die latch of the semiconductor chip, and a die latch A semiconductor package comprising a metal wire connecting a bond pad of a chip and an inner lead of the lead frame, and an epoxy molding compound to seal a wire bonded chip, wherein a heat dissipation hole is provided in a paddle center portion of the lead frame to which the semiconductor chip is fixed. The semiconductor package is characterized in that a step for forming a chip is formed at the edge thereof to achieve thermal stability and heat dissipation effect.

Description

반도체 패키지Semiconductor package

제1도는 통상적인 반도체 패키지의 구성을 보이는 단면도.1 is a cross-sectional view showing the configuration of a conventional semiconductor package.

제2도는 본 고안에 의한 반도체 패키지의 구성을 보이는 단면도.2 is a cross-sectional view showing the configuration of a semiconductor package according to the present invention.

제3도의 (a)(b)는 본 고안에 사용되는 리드 프레임의 구성을 상세하게 보이는 평면도 및 단면도.Figure 3 (a) (b) is a plan view and a cross-sectional view showing in detail the configuration of the lead frame used in the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1: 반도체 칩1a: 본드패드1: Semiconductor Chip 1a: Bond Pad

2: 리드프레임2a: 패들2: leadframe 2a: paddle

2b, 2c: 인, 아웃리드3: 접착제2b, 2c: In, Outlead 3: Adhesive

4: 금속와이어5: 에폭시 몰딩 컴 파운드4: metal wire 5: epoxy molding compound

10: 방열공11: 단턱10: radiator 11: step

본 고안은 반도체 패키지 구조에 관한것으로 특히, 칩이 고정되는 리드프레임의 패들중심부에 방열공을 형성하고 칩 안착을 위한 턱을 가진 2단구조로 하여 패키지의 열적 특성 향상에 적합하도록 한 반도체 패키지에 관한것이다.The present invention relates to a semiconductor package structure, and more particularly, to a semiconductor package in which a heat dissipation hole is formed in a paddle center of a lead frame to which a chip is fixed, and a two-stage structure having a jaw for seating a chip is suitable for improving the thermal characteristics of the package. It's about.

종래의 일반적인 플라스틱 반도체 패키지는 제1도에 도시한 바와같이 복수개의 본드패드(bond pad)(1a)가 구비된 반도체 칩(chip)(1)과, 그 반도체 칩(1)이 고정되는 사각형의 패들(paddle)(2a)이 구비됨과 아울러 상기 반도체 칩(1)의 본드 패드(1a)에 와이어 본딩(wire bonding)되는 복수개의 인너리드(inner lead)(2b)와 아웃리드(out lead)(2c)가 구비된 리드프레임(lead frame)(2)과, 그 리드프레임(2)의 패들(2a)에 반도체 칩(1)을 부착고정하기 위한 접착제(adhesive)(3)와, 다이어래치(Die attach)된 칩(1a)의 본드패드(1a)와 상기 리드프레임(2)의 인너리드(2b)를 전기적으로 접속연결 시키는 복수개의 금속와이어(4)와, 와이어본딩된 칩(1)과, 상기 리드프레임(2)의 아웃리드(2c)를 포함하는 일정부위를 밀폐시키는 에폭시 몰딩 컴파운드(EMC: Epoxy Molding Comound)(5)로 구성되어 있다.A conventional plastic semiconductor package has a semiconductor chip 1 having a plurality of bond pads 1a as shown in FIG. 1, and a quadrangle to which the semiconductor chip 1 is fixed. A paddle 2a and a plurality of inner leads 2b and out leads that are wire bonded to the bond pad 1a of the semiconductor chip 1 are provided. A lead frame 2 provided with 2c, an adhesive 3 for attaching the semiconductor chip 1 to the paddle 2a of the lead frame 2, and a die latch A plurality of metal wires 4 electrically connecting and connecting the bond pad 1a of the die attached chip 1a and the inner lead 2b of the lead frame 2 to the wire bonded chip 1; And an epoxy molding compound (EMC) 5 which seals a predetermined portion including the out lead 2c of the lead frame 2.

이와같이 구성된 종래의 반도체 패키지는 소잉(sawing)공정에 의해 개개로 분리된 반도체 칩(1)은 리드프레임(2)의 패들(2a)에 접착제(3)를 이용하여 부착고정하는 다이어래치공정과, 다이어래치된 칩(1)의 본드패드(1a)와 상기 리드프레임(2)의 인너리드(2b)를 금속와이어(4)를 이용하여 전기적으로 접속연결시키는 와이어 본딩 공정과, 와이어 본딩된 상기 칩(1)과, 리드프레임(2)이 아웃리드(2c)를 포함하는 일정부위를 에폭시 몰딩 컴파운드(5)로 밀폐시키는 몰딩공정과, 상기 리드프레임(2)의 타이바(Tie bar) 및 댐바(Dam bar)(도시되지 않음)를 절단하는 트리밍(Trimming)공정과, 패키지 외부로 돌출된 리드프레임(2)의 아웃리드(2c)를 소정의 모양으로 절곡형성하는 포밍(forming)공정과, 통상적인 플래팅(plating)공정의 순으로 제작된다.The conventional semiconductor package configured as described above includes a die latch process in which the semiconductor chips 1 separately separated by a sawing process are attached and fixed to the paddles 2a of the lead frame 2 by using an adhesive 3; A wire bonding process for electrically connecting the bond pad 1a of the die-etched chip 1 and the inner lead 2b of the lead frame 2 with a metal wire 4, and the wire bonded chip. (1) and a molding process in which the lead frame 2 seals a predetermined portion including the outlead 2c with an epoxy molding compound 5, a tie bar and a dam bar of the lead frame 2; A trimming process of cutting (Dam bar) (not shown), a forming process of bending the outlead 2c of the lead frame 2 protruding out of the package into a predetermined shape, It is manufactured in the order of a conventional plating process.

그러나, 상기한 바와같은 종래의 플라스틱 반도체 패키지는 반도체 소자에 고온이 지속적으로 가해지거나, 서멀 사이클링(Thermal Cycling)이 가해질 경우, 각 구성물질 예컨데, 칩(1), 리드프레임(2), 접착제(3) 및 에폭시 몰딩 컴파운드(5)들간의 열팽창 계수(CTE: Coefficient of Thermal Expansion)차이로 인해 패키지 크랙(PKG Crack) 및 칩이 얇은 조각으로 갈라지는 딜래머네이션(delamination)현상이 발생하는 것이었다.However, in the conventional plastic semiconductor package as described above, when the high temperature is continuously applied to the semiconductor device or the thermal cycling is applied, each of the components, for example, the chip 1, the lead frame 2, the adhesive ( 3) PKG Crack and chip delamination due to the difference in the coefficient of thermal expansion (CTE) between the epoxy molding compounds (5) and the epoxy molding compound (5).

즉, 아래표에서 보는바와같이 상기한 각 구성물질들의 열팽창계수값이 매우 큰 차이를 보이므로 상술한 바와같은 여러결합이 발생하는 것이다.In other words, as shown in the table below, the coefficient of thermal expansion of each of the above-described constituents exhibits a very large difference, and thus, various coupling as described above occurs.

따라서, 본 고안은 상기한 바와같은 종래의 결함을 해소하기 위하여 안출한 것으로, 반도체 칩이 고정되는 리드프레임의 패들에 방열공을 형성하고 패들을 칩 안착을 위한 턱을 가진 2단 구조로 하여 열팽창 계수값이 큰 접착제의 면적을 줄이고, 에폭시 몰딩 컴파운드와 실리콘 칩(Si-chip)과의 접촉면적을 크게하여 방열효과를 증대시킴과 아울러 칩을 열적으로 안정화 시킬수 있도록 구성한 것인바, 이를 첨부한 도면에 의하여 보다 상세히 보다 설명하면 다음과 같다.Therefore, the present invention has been devised to solve the conventional defects as described above, thermal expansion of the paddle of the lead frame to which the semiconductor chip is fixed and a two-stage structure having a jaw for seating the paddle It is designed to increase the heat dissipation effect by increasing the contact area between the epoxy molding compound and the silicon chip (Si-chip) and to thermally stabilize the chip. When described in more detail by the following.

제2도는 본 고안에 의한 반도체 패키지의 구성을 보이는 단면도이고, 제3도의 (a)(b)는 본 고안에 사용되는 리드프레임의 패들 구조도로서 이에 도시한바와 같이 본 고안에 의해 반도체 패키지는 반도체 칩(1)과 그 반도체 칩(1)이 부착고정되는 패들(2a)이 구비됨과 아울러 인너리드(2b) 및 아웃리드(2c)가 구비된 리드프레임(2)과, 상기 반도체 칩(1)을 다이어래치 하기 위한 접착제(3)와, 다이어래치된 칩(1)의 본드패드(1a)와 상기 리드프레임(2)의 인너리드(2b)를 연결하는 금속와이어(4)와, 와이어 본딩된 칩(1)을 밀폐시키는 에폭시 몰딩 컴파운드(5)로 구성된 반도체 패키지에 있어서, 반도체 칩(1)이 고정되는 상기 리드프레임(2)의 패들(2a)중심부에 방열공(10)을 형성하고, 가장자리에는 칩(1)안착을 위한 단턱(11)을 형성하여 열팽창계수(CTE)값이 큰 접착제(3)의 면적을 줄이고, 에폭시 몰딩 컴파운드(5)와, 상기 칩(1)과의 접촉면적을 증대시켜 패키지의 방열효과를 높일수 있도록 구성한 것으로 도면에서 종래구성과 동일한 부분에 동일 부호를 부여 하였다.2 is a cross-sectional view showing the configuration of a semiconductor package according to the present invention, Figure 3 (a) (b) is a structure of the paddle of the lead frame used in the present invention as shown in the semiconductor package is a semiconductor package according to the present invention The lead frame 2 is provided with the chip 1 and the paddle 2a to which the semiconductor chip 1 is fixed, and the inner lead 2b and the outlead 2c are provided, and the semiconductor chip 1 A metal wire (4) connecting the adhesive (3) for die latching, the bond pad (1a) of the die-etched chip (1) and the inner lead (2b) of the lead frame (2), and wire bonding In the semiconductor package consisting of an epoxy molding compound (5) for sealing the chip (1), a heat dissipation hole (10) is formed in the center of the paddle (2a) of the lead frame (2) to which the semiconductor chip (1) is fixed, The surface of the adhesive 3 having a large coefficient of thermal expansion (CTE) is formed at the edge by forming a step 11 for seating the chip 1. The same reference numerals are given to the same parts as in the prior art in order to reduce the number and to increase the heat dissipation effect of the package by increasing the contact area between the epoxy molding compound 5 and the chip 1.

이와같이 구성된 본 고안에 의한 반도체 패키지의 제작과정을 종래와 동일 유사하나, 칩(1) 다이어래치시 열팽창 계수 값이 큰 접착제(3)의 면적을 줄일수 있으므로 패키지가 열적으로 안정되고 몰딩시 실리콘 칩(1)과, 에폭시 몰딩 컴파운드(5)와의 접촉 면적이 증대되므로 패키지의 열방출 효과를 높일수 있는 것이다.The manufacturing process of the semiconductor package according to the present invention configured as described above is similar to the conventional one, but since the area of the adhesive 3 having a large coefficient of thermal expansion during die etching can be reduced, the package is thermally stable and the silicon chip when molding Since the contact area between (1) and the epoxy molding compound 5 is increased, the heat dissipation effect of the package can be enhanced.

즉, 본 고안에 의한 반도체 패키지는 도시하고 상술한 바와같이 칩이 고정되는 리드프레임의 패들중심부에 방열공을 형성함과 아울러 가장자리에는 칩안착을 위한 단턱을 형성함으로써 칩과 에폭시 몰딩 컴파운드 사이에 위치하는 열팽창 계수(CTE) 값이 큰 접착제의 면적을 줄일수 있으므로 패키지가 열적으로 안정되고, 또한 실리콘 칩과 에폭시 몰딩 컴파운드와의 접촉면적이 증대되므로 보다 효율적인 열방출 효과를 기대할수 있는 것이다.That is, the semiconductor package according to the present invention is located between the chip and the epoxy molding compound by forming a heat dissipation hole in the center of the paddle of the lead frame to which the chip is fixed as shown and described above, and forming a step at the edge for chip mounting. Since the area of the adhesive having a large coefficient of thermal expansion (CTE) can be reduced, the package is thermally stable, and the contact area between the silicon chip and the epoxy molding compound is increased, so that more efficient heat dissipation effect can be expected.

아울러 다이어래치 재질의 사용감소로 패키지의 제조원가를 다운 시킬수 있는 효과도 있다.In addition, the use of the die-latch material can reduce the manufacturing cost of the package.

Claims (2)

반도체 칩(1)과, 그 반도체 칩(1)이 부착고정되는 패들(2a)이 구비됨과 아울러 인너리드(2b) 및 아웃리드(2c)가 구비된 리드프레임(2)과, 상기 반도체 칩(1)의 다이어래치를 위한 접착제(3)와, 다이어래치 된 칩(1)의 본드패드(1a)와 상기 리드프레임(2)의 인너리드(2b)를 연결하는 금속와이어(4)와, 와이어 본딩된 칩(1)를 밀폐시키는 에폭시 몰딩 컴파운드(5)로 구성된 반도체 패키지에 있어서, 반도체 칩(1)이 고정되는 상기 리드프레임(2)의 패들(2a) 중심부에 방열공(10)을 형성하고, 가장자리에는 칩(1)안착을 위한 단턱(11)을 형성하여 열적안정 및 방열효과를 도모한 것임을 특징으로 하는 반도체 패키지.The semiconductor chip 1, a paddle 2a to which the semiconductor chip 1 is attached and fixed, a lead frame 2 provided with an inner lead 2b and an out lead 2c, and the semiconductor chip ( A metal wire 4 for connecting the adhesive 3 for the die latch of 1), the bond pad 1a of the die-etched chip 1, and the inner lead 2b of the lead frame 2; In the semiconductor package consisting of an epoxy molding compound (5) for sealing the bonded chip (1), the heat dissipation hole 10 is formed in the center of the paddle (2a) of the lead frame (2) to which the semiconductor chip (1) is fixed The edge of the semiconductor package, characterized in that the step (11) for mounting the chip (1) to achieve thermal stability and heat dissipation effect. 제1항에 있어서, 상기 접착제(3)는 에폭시계 또는 플리이미드계인것을 특징으로 하는 반도체 패키지.The semiconductor package according to claim 1, wherein the adhesive (3) is epoxy or plyimide.
KR2019910022567U 1991-12-17 1991-12-17 Semiconductor package KR0119764Y1 (en)

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KR0119764Y1 true KR0119764Y1 (en) 1998-07-01

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