JPH01245169A - Integrated circuit - Google Patents

Abstract

PURPOSE:To obtain an integrated circuit whose maintenance can be executed easily by providing a test information generating part and a test result deciding part on the inside of an LSI and executing a self-diagnosis. CONSTITUTION:An input signal 1i (i=0-n) and a test pattern output signal 2i of a test information generating part 1 are inputted to a test switching part 2, respectively. An output signal 3i of the test switching part 2 is inputted to a logic circuit 3. An output signal 4i of the logic circuit 3 becomes an output of a terminal To, and also, inputted to a test result deciding part 4. A test start instructing input Sr is inputted to the test information generating part 1, the test switching part 2 and the test result deciding part 4. An output S'T of the test result deciding part 4 is outputted from a test output terminal T'T. Subsequently, when a test start instructing input ST becomes effective, the test pattern signal 2i is outputted from the test information generating part 1, outputted as input signals 2i, 3i by the test switching part 2, and the test result deciding part 4 decides the quality of an input signal 4i, and thereafter, outputs it as the output S'T to the test output terminal T'T.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はａＷｔ回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to aWt circuits.

〔従来の技術〕[Conventional technology]

従来は装置実装後の複数の集積回路（以下ＬＳＩという
）を保守する場合は、特殊な知識を有した技術者が測定
器を用いてＬＳＩに入出力する信号情報を収集後、前記
入出力信号情報を検討して、不良のＬＳＩを限定してい
た。Conventionally, when maintaining multiple integrated circuits (hereinafter referred to as LSI) after device implementation, an engineer with special knowledge uses a measuring instrument to collect signal information input and output from the LSI, and then The information was examined to limit the number of defective LSIs.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の集積回路は、特殊な知識を有した技術者
が複数のＬＳＩの入出力信号情報を測定・収集後、不良
ＬＳＩ部分の判断を行なうので専門の知識と多大な時間
を必要とするという欠点を有していた。The conventional integrated circuits described above require specialized knowledge and a large amount of time because engineers with special knowledge measure and collect input/output signal information of multiple LSIs and then determine which LSI parts are defective. It had the following drawback.

本発明の目的は、保守の容易な集積回路を提供すること
にある。An object of the present invention is to provide an integrated circuit that is easy to maintain.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の集積回路は、ＬＳＩ内部に試験パターンの生成
を行なう試験情報生成部と試験結果の判定を行なう試験
結果判定部とさらに該試験情報生成部・試験結果判定部
と入出力信号を切替える試験切替部と試験指示結果表示
用の試験指示端子及び試験出力端子を有している。The integrated circuit of the present invention includes a test information generation section that generates a test pattern inside an LSI, a test result judgment section that judges test results, and a test information generation section/test result judgment section that switches input/output signals. It has a switching section, a test instruction terminal for displaying test instruction results, and a test output terminal.

〔実施例〕〔Example〕

次に図面を用いて実施例について説明する。 Next, embodiments will be described using the drawings.

第１図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

入力信号１＋　　（ｉ＝ｏ〜ｎ）と試験情報生成部１の
試験パターン出力信号２１は各々試験切替部２に入力さ
れる。The input signal 1+ (i=on) and the test pattern output signal 21 of the test information generation section 1 are each input to the test switching section 2.

試験切替部２の出力信号３Ｉは論理回路３に入力される
。The output signal 3I of the test switching section 2 is input to the logic circuit 3.

論理回路３の出力信号４Ｉは端子ＴＯの出力となるとと
もに試験結果判定部４に入力される。The output signal 4I of the logic circuit 3 becomes the output of the terminal TO and is also input to the test result determination section 4.

試験開始指示人力ＳＴは試験情報生成部１、試験切替部
２、試験結果判定部４へ入力される。The test start instruction manual ST is input to the test information generation section 1, the test switching section 2, and the test result determination section 4.

試験結果判定部４の出力３丁は試験出力端子Ｔｔから出
力される。Three outputs of the test result determination section 4 are output from the test output terminal Tt.

試験開始指示入力ｓｒが有効でない場合、試験切替部２
は端子入力信号１１を試験切替部２の出力信号３１とし
て出力しておりＬＳＩは通常の動作を行なっている。If the test start instruction input sr is not valid, the test switching unit 2
outputs the terminal input signal 11 as the output signal 31 of the test switching section 2, and the LSI is operating normally.

試験開始指示入力ｓｒが有効になると試験情報生成部１
から試験パターン信号２．が出力され、試験切替部２で
入力信号２．と３１として出力し、試験結果判定部４は
入力信号４１の良否を判定後試験出力端子ＴＴへ出力Ｓ
Ｔとして出力する。When the test start instruction input sr becomes valid, the test information generation unit 1
Test pattern signal 2. is output, and the test switching unit 2 inputs the input signal 2. and 31, and after determining whether the input signal 41 is good or bad, the test result determination section 4 outputs S to the test output terminal TT.
Output as T.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ＬＳＩ内部で自己診断を
行なうことによりＬＳＩＩＩ害時の保守を特殊な知識及
び技術を必要とすることなく又保守作業時間短縮できる
効果がある。As described above, the present invention has the advantage that by performing self-diagnosis within the LSI, maintenance work when the LSI is damaged can be performed without requiring special knowledge or skills, and the maintenance work time can be shortened.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明のブロック図である。 １・・・試験情報生成部、２・・・試験切替部、３・・
・論理回路、４・・・試験結果判定部。 代理人　弁理士　　内　原　　音FIG. 1 is a block diagram of the present invention. 1... Test information generation section, 2... Test switching section, 3...
- Logic circuit, 4... test result determination section. Agent Patent Attorney Oto Uchihara

Claims (1)

【特許請求の範囲】[Claims] 　試験パターンの生成を行なう試験情報生成部と、試験
結果の判定を行なう試験結果判定部と、前記試験情報生
成部及び試験結果判定部と端子入出力信号を切替える試
験切替部と試験及び結果表示用の試験指示端子と試験出
力端子とを有し、前記試験指示端子に試験指示入力を与
えることにより端子入力と試験パターンを切替えて、出
力信号を前記試験結果判定部で良否判定後前記試験出力
端子に指示することを特徴とする集積回路。A test information generation section that generates a test pattern, a test result judgment section that judges test results, the test information generation section and the test result judgment section, a test switching section that switches terminal input/output signals, and a test and result display section. The test instruction terminal has a test instruction terminal and a test output terminal, and the terminal input and the test pattern are switched by giving a test instruction input to the test instruction terminal, and the output signal is passed to the test output terminal after being judged pass/fail by the test result judgment section. An integrated circuit characterized in that it instructs.