JPH01243586A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01243586A JPH01243586A JP63069552A JP6955288A JPH01243586A JP H01243586 A JPH01243586 A JP H01243586A JP 63069552 A JP63069552 A JP 63069552A JP 6955288 A JP6955288 A JP 6955288A JP H01243586 A JPH01243586 A JP H01243586A
- Authority
- JP
- Japan
- Prior art keywords
- concentration diffusion
- silicon substrate
- diffusion layer
- low concentration
- high concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 25
- 238000009792 diffusion process Methods 0.000 claims abstract description 48
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 25
- 239000010703 silicon Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000002955 isolation Methods 0.000 claims abstract description 12
- 230000001681 protective effect Effects 0.000 claims abstract description 11
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 230000002265 prevention Effects 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000000034 method Methods 0.000 description 10
- 239000012535 impurity Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に関し、特に、MO3形半導体装
置の静電破壊防止に適用して有効な技術に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a technique that is effective when applied to prevent electrostatic damage in MO3 type semiconductor devices.
CMO3形半導体装置のウェル構造については、例えば
、株式会社サイエンスフォーラム、昭和58年11月2
8日発行、「超LSIデバイスハンドブック」P50〜
P51に記載がある。Regarding the well structure of CMO3 type semiconductor devices, see, for example, Science Forum Co., Ltd., November 2, 1982.
Published on the 8th, "Ultra LSI Device Handbook" P50~
There is a description on page 51.
CMO3形半導体装置には、外部からの静電ノイズによ
る集積回路の破壊の防止を目的として、入力端子(また
は出力端子)と集積回路との間にウェル間のパンチスル
ーを利用した静電破壊防止用保護素子を設けたものが知
られている。CMO3 type semiconductor devices have an electrostatic damage prevention method that utilizes a punch-through between wells between the input terminal (or output terminal) and the integrated circuit in order to prevent damage to the integrated circuit due to external electrostatic noise. A device equipped with a protective element for protection is known.
上記静電破壊防止用保護素子の構成は、素子分離領域で
囲まれた活性領域内に同じ導電形の一対のウェルを対向
形成したものであり、入力端子(出力端子)に電源電圧
よりも高圧の静電ノイズか加わった際、ウェル間にパン
チスルーが生じて電流が流れ、内部集積回路の静電破壊
を防止するようになっている。The structure of the above protection element for preventing electrostatic damage is that a pair of wells of the same conductivity type are formed facing each other in an active region surrounded by an element isolation region, and a voltage higher than the power supply voltage is applied to the input terminal (output terminal). When electrostatic noise is applied, punch-through occurs between the wells and current flows, preventing electrostatic damage to the internal integrated circuit.
しかしながら、ウェル間のパンチスルーを利用した上記
CMO3形半導体装置の静電破壊防止用保護素子には、
下記のような欠点がある。However, the protection element for preventing electrostatic damage of the CMO3 type semiconductor device using punch-through between wells has
It has the following drawbacks.
すなわち、シリコン基板内に形成されるウェルの深さは
、通常、2〜10μm程度と深く、ウェルを形成する際
に基板内に注入される不純物の横方向の拡散も大きいこ
とから、基板内に占めるウェルの容積が大きくなり、そ
の結果、半導体装置の高集積化を妨げてしまうことにな
る。In other words, the depth of a well formed in a silicon substrate is usually about 2 to 10 μm, and the lateral diffusion of impurities injected into the substrate when forming the well is also large. The volume occupied by the well becomes large, and as a result, high integration of semiconductor devices is hindered.
また、MO3形半導体装置においてウェルを形成するプ
ロセスは、CMO3形半導体装置に限られるため、ウェ
ルを形成しないpチャネル形素子またはnチャネル形素
子のみからなるMO3形半導体装置には、適用すること
ができない。Furthermore, since the process for forming wells in MO3 type semiconductor devices is limited to CMO3 type semiconductor devices, it cannot be applied to MO3 type semiconductor devices consisting only of p-channel type elements or n-channel type elements that do not form wells. Can not.
本発明は、上記した問題点に着目してなされたものであ
り、その目的は、静電破壊防止用保護素子の微細化を図
ることができる技術を提供することにある。The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a technique that can miniaturize a protective element for preventing electrostatic damage.
本発明の前記並びにその他の目的と新規な特徴とは、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、シリコン基板内に所定の間隔を置いて対向形
成された一対の高濃度拡散層と、それらの周囲に形成さ
れた低濃度拡散層とからなる静電破壊防止用保護素子を
上記シリコン基板と異なる導電形で形成し、この静電破
壊防止用保護素子を集積回路と入力または出力端子との
間に接続した半導体装置である。That is, a protective element for preventing electrostatic discharge damage consisting of a pair of high concentration diffusion layers formed facing each other at a predetermined distance in a silicon substrate and a low concentration diffusion layer formed around them is attached to the silicon substrate. This is a semiconductor device in which a protective element for preventing electrostatic damage is connected between an integrated circuit and an input or output terminal, which are formed with different conductivity types.
上記した手段によれば、シリコン基板内に形成される拡
散層の容積がウェルの容積よりも小さいため、静電破壊
防止用保護素子の微細化が達成される。According to the above means, since the volume of the diffusion layer formed in the silicon substrate is smaller than the volume of the well, miniaturization of the protection element for preventing electrostatic damage is achieved.
第1図は、本発明の一実施例である半導体装置における
静電破壊防止用保護素子を示すシリコン基板の要部断面
図、第2図は、この静電破壊防止用保護素子の配置を示
す回路図である。FIG. 1 is a sectional view of a main part of a silicon substrate showing a protection element for preventing electrostatic damage in a semiconductor device according to an embodiment of the present invention, and FIG. 2 shows the arrangement of this protection element for preventing electrostatic damage. It is a circuit diagram.
以下、MO3形半導体集積回路の一部に形成された静電
破壊防止用保護素子1の構成を説明する。The structure of the electrostatic breakdown prevention protection element 1 formed in a part of an MO3 type semiconductor integrated circuit will be described below.
第1図に示すように、所定の不純物濃度を有するp形シ
リコン単結晶からなるシリコン基板20表面には、Si
n、からなる素子分離領域3a。As shown in FIG. 1, the surface of a silicon substrate 20 made of p-type silicon single crystal with a predetermined impurity concentration
An element isolation region 3a consisting of n.
3b、3cが所定の間隔を置いて形成され、中央の素子
分離領域3cを挟んだ両側の活性領域内には、高濃度拡
散層4a、4bがそれぞ゛れ形成されている。3b and 3c are formed at a predetermined interval, and high concentration diffusion layers 4a and 4b are formed in the active regions on both sides of the central element isolation region 3c, respectively.
高濃度拡散層4a、4bは、シリコン基板2とは異なる
導電形、すなわち、n′″形拡散拡散層なり、例えば、
ヒ素(As)などの不純物を1020/cl″以上の高
濃度で拡散したものである。The high concentration diffusion layers 4a and 4b are of a conductivity type different from that of the silicon substrate 2, that is, are n'' type diffusion layers, for example,
Impurities such as arsenic (As) are diffused at a high concentration of 1020/cl'' or higher.
高濃度拡散層4a、4bは、リンケイ酸ガラス(P S
G)などからなる絶縁膜5の一部に開口形成されたコ
ンタクトホール6を介してAJ配線7a、7bに接続さ
れている。The high concentration diffusion layers 4a and 4b are made of phosphosilicate glass (PS
It is connected to AJ wirings 7a and 7b through a contact hole 6 formed in a part of an insulating film 5 made of G) or the like.
一方、シリコン基板2の内部において、高濃度拡散層4
a、4bの周囲には、リン(P)などの不純物を低濃度
で拡散したn−形の低濃度拡散層3a、3bが形成され
ている。On the other hand, inside the silicon substrate 2, a high concentration diffusion layer 4
Around the layers a and 4b, n-type low concentration diffusion layers 3a and 3b in which impurities such as phosphorus (P) are diffused at a low concentration are formed.
低濃度拡散層3a、3bは、いずれも素子分離領域3a
、3b、3cの下方に形成されており、中央の素子分離
領域3Cの下方において、一方の低濃度拡散層8aと他
方の低濃度拡散層8bとの間が所定の距離りだけ離れて
いる。The low concentration diffusion layers 3a and 3b are both element isolation regions 3a.
, 3b, 3c, and below the central element isolation region 3C, one low concentration diffusion layer 8a and the other low concentration diffusion layer 8b are separated by a predetermined distance.
以上の構成からなる静電破壊防止用保護素子1において
、例えば、低濃度拡散層3a、3bの形成は、このシリ
コン基板2にチャネルストッパ領域を形成する際、同時
に行われる。In the protection element 1 for preventing electrostatic discharge damage having the above structure, for example, the formation of the low concentration diffusion layers 3a and 3b is performed at the same time as the formation of the channel stopper region in the silicon substrate 2.
高濃度拡散層4a、−4bの形成には、ソースおよびド
レイン領域を形成する不純物イオン打ち込み工程や熱処
理工程が、また、素子分離領域3a。The formation of the high concentration diffusion layers 4a and -4b includes an impurity ion implantation process and a heat treatment process for forming the source and drain regions, and also the element isolation region 3a.
3b、3cの形成には、LOCO3法を用いたフィール
ド酸化膜形成工程などがそれぞれ利用される。3b and 3c are formed using a field oxide film forming process using the LOCO3 method, respectively.
従って、静電破壊防止用保護素子1は、MO3形半導体
集積回路の製造工程を増加させることなく作成すること
ができる。Therefore, the protection element 1 for preventing electrostatic damage can be produced without increasing the manufacturing process of MO3 type semiconductor integrated circuits.
次に、静電破壊防止用保護素子10機能を説明する。Next, the function of the protection element 10 for preventing electrostatic damage will be explained.
第2図に示すように、静電破壊防止用保護素子1は、静
電破壊から保護される内部集積回路9と入力端子(また
は出力端子、以下同じ) 10との間にAl配線7aを
介して接続され、もう一方のAIl配線7bが電源11
に接続されている。As shown in FIG. 2, the protection element 1 for preventing electrostatic damage has an Al wiring 7a between an internal integrated circuit 9 to be protected from electrostatic damage and an input terminal (or output terminal, the same applies hereinafter) 10. and the other AIl wiring 7b is connected to the power supply 11.
It is connected to the.
そこで、入力端子lOに電源電圧よりも高圧の静電ノイ
ズが加わると、Al配線7aを介して静電破壊防止用保
護素子1に電圧が印加され、一方の低濃度拡散層8aか
らシリコン基板2内に広がった空乏層がもう一方の低濃
度拡散層8bに到達する(パンチスルー)。Therefore, when electrostatic noise with a voltage higher than the power supply voltage is applied to the input terminal IO, a voltage is applied to the protection element 1 for preventing electrostatic damage via the Al wiring 7a, and from one low concentration diffusion layer 8a to the silicon substrate 2. The inwardly expanded depletion layer reaches the other low concentration diffusion layer 8b (punch through).
すると、低濃度拡散層8aからシリコン基板2を経て低
濃度拡散層8bに流れた電流がへβ配線7bを経て電源
11に流れ込み、これにより、内部集積回路9の静電破
壊が有効に防止される。Then, the current flowing from the low concentration diffusion layer 8a to the low concentration diffusion layer 8b via the silicon substrate 2 flows into the power supply 11 via the beta wiring 7b, thereby effectively preventing electrostatic damage to the internal integrated circuit 9. Ru.
なお、パンチスルーが生ずる電圧は、低濃度拡散層8a
から低濃度拡散層8bまでの距離りによって決まるが、
パンチスルー電圧が高すぎると、空乏層が低濃度拡散層
8bに到達する前に内部集積回路9が破壊されてしまう
ため、パンチスルー電圧は、電源電圧よりも高圧で、か
つ、高すぎないことが要求される。Note that the voltage at which punch-through occurs is
It is determined by the distance from to the low concentration diffusion layer 8b,
If the punch-through voltage is too high, the internal integrated circuit 9 will be destroyed before the depletion layer reaches the low concentration diffusion layer 8b, so the punch-through voltage must be higher than the power supply voltage and not too high. is required.
従って、静電破壊防止用保護素子1の製造に際しては、
距離りの制御が重要となり、例えば、低濃度拡散層8a
と低濃度拡散層8bとを同一のホトリソグラフィ工程で
形成する、などの配慮が必要である。Therefore, when manufacturing the protective element 1 for preventing electrostatic damage,
Controlling the distance is important, for example, the low concentration diffusion layer 8a
Consideration must be given to forming the low concentration diffusion layer 8b and the low concentration diffusion layer 8b in the same photolithography process.
以上、本実施例によれば、下記のような効果を得ること
ができる。As described above, according to this embodiment, the following effects can be obtained.
〔1)、静電破壊防止用保護素子1を高濃度拡散層4a
、4bと、それらの周囲に形成された低濃度拡散層3a
、低濃度拡散層8bとによって構成したので、一対のウ
ェルによって構成される従来の静電破壊防止用保護素子
に比べ、その容積を微細化することができる。[1) The protective element 1 for preventing electrostatic damage is formed by a high concentration diffusion layer 4a.
, 4b and the low concentration diffusion layer 3a formed around them.
, and the low concentration diffusion layer 8b, the volume can be miniaturized compared to a conventional protection element for preventing electrostatic discharge damage that is composed of a pair of wells.
(2)、上記(1]により、MOS形半導体装置の高集
積化を妨げることなく、内部集積回路の静電破壊を有効
に防止することができる。(2) According to the above (1), electrostatic damage to the internal integrated circuit can be effectively prevented without hindering the high integration of MOS type semiconductor devices.
(2)、上記(1)により、CMOS形半導体装置のみ
ならず、ウェルを形成しないpチャネル形素子やnチャ
ネル形素子のみからなるMOS形半導体装置にも適用す
ることができる。(2) Due to (1) above, the present invention can be applied not only to CMOS type semiconductor devices but also to MOS type semiconductor devices consisting only of p-channel type elements or n-channel type elements without forming wells.
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は、前記実施例に限定され
るものではなく、その要旨を逸脱しない範囲で種々変更
可能であることはいうまでもない。As above, the invention made by the present inventor has been specifically explained based on Examples, but the present invention is not limited to the above-mentioned Examples, and it is understood that various changes can be made without departing from the gist thereof. Needless to say.
例えば、実施例では、低濃度拡散層を素子分離領域の下
方に形成したが、第3図に示すように、低濃度拡散層8
a、8bを活性領域の内部に形成した静電破壊防止用保
護素子構造とすることもできる。For example, in the embodiment, the low concentration diffusion layer was formed below the element isolation region, but as shown in FIG.
It is also possible to have a protective element structure for preventing electrostatic discharge damage in which elements a and 8b are formed inside the active region.
また、実施例では、p形シリコン基板内にn゛形の高濃
度拡散層およびn−形の低濃度拡散層を形成したが、n
形シリコン基板内やn形つェル内にp゛形の高濃度拡散
層およびp−形の低濃度拡散層を形成した静電破壊防止
用保護素子構造とすることもできる。In addition, in the example, an n-type high concentration diffusion layer and an n-type low concentration diffusion layer were formed in a p-type silicon substrate.
A protection element structure for preventing electrostatic discharge damage may be provided in which a p-type high concentration diffusion layer and a p-type low concentration diffusion layer are formed in a silicon substrate or an n-type well.
以上の説明では、主として本発明者によってなされた発
明をその利用分野であるMOS形半導体装置に適用した
場合について説明したが、これに限定されるものではな
く、基板と異なる導電形の低濃度拡散層を形成するホ)
IJソゲラフイエ程を追加することにより、全ての半導
体装置に適用可能となる。In the above explanation, the invention made by the present inventor is mainly applied to a MOS type semiconductor device, which is the field of application of the invention, but the invention is not limited to this. forming a layer)
By adding the IJ Sogerahuie process, it becomes applicable to all semiconductor devices.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記の通りである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
すなわち、シリコン基板内に所定の間隔を置いて対向形
成された一対の高濃度拡販層と、それらの周囲に形成さ
れた低濃度拡散層とからなる静電破壊防止用保護素子を
上記シリコン基板と異なる導電形で形成し、これを集積
回路と入力または出力端子との間に接続した半導体装置
構造とすることにより、半導体装置の高集積化を妨げる
ことなく、集積回路の静電破壊を有効に防止することが
可能となる。That is, a protective element for preventing electrostatic discharge damage consisting of a pair of high-concentration sales promotion layers formed facing each other at a predetermined distance in a silicon substrate and a low-concentration diffusion layer formed around them is attached to the silicon substrate. By creating a semiconductor device structure in which different conductivity types are formed and connected between the integrated circuit and the input or output terminal, electrostatic damage to the integrated circuit can be effectively prevented without hindering the high integration of semiconductor devices. It becomes possible to prevent this.
第1図は本発明の一実施例である半導体装置における静
電破壊防止用保護素子を示すシリコン基板の要部断面図
、
第2図はこの静電破壊防止用保護素子の配置を示す回路
図、
第3図は本発明の他の実施例である半導体装置における
静電破壊防止用保護素子を示すシリコン基板の要部断面
図である。
1・・・静電破壊防止用保護素子、2・・・シリコン基
板、3a、3b、3c・・・素子分離領域、4a、4b
・・・高濃度拡散層、5・・・絶縁膜、6・・・コンタ
クトホール、7a、7b・・・A1配線、3a、3b・
・・低濃度拡散層、9・・・内部集積回路、10・・・
入力(出力)端子、11・・・電源。
第3図FIG. 1 is a sectional view of a main part of a silicon substrate showing a protection element for preventing electrostatic damage in a semiconductor device according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing the arrangement of this protection element for preventing electrostatic damage. FIG. 3 is a sectional view of a main part of a silicon substrate showing a protection element for preventing electrostatic damage in a semiconductor device according to another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Protective element for preventing electrostatic damage, 2... Silicon substrate, 3a, 3b, 3c... Element isolation region, 4a, 4b
...High concentration diffusion layer, 5...Insulating film, 6...Contact hole, 7a, 7b...A1 wiring, 3a, 3b.
...Low concentration diffusion layer, 9...Internal integrated circuit, 10...
Input (output) terminal, 11...power supply. Figure 3
Claims (1)
た、前記シリコン基板と異なる導電形を有する一対の高
濃度拡散層と、前記一対の高濃度拡散層の各々の周囲に
形成された、前記高濃度拡散層と同一の導電形を有する
低濃度拡散層とからなる静電破壊防止用保護素子を、集
積回路と入力または出力端子との間に接続したことを特
徴とする半導体装置。 2、低濃度拡散層を活性領域の内部、または、素子分離
領域の下方に形成することを特徴とする請求項1記載の
半導体装置。[Claims] 1. A pair of high concentration diffusion layers having a conductivity type different from that of the silicon substrate, which are formed facing each other at a predetermined distance in a silicon substrate, and each of the pair of high concentration diffusion layers. A protective element for preventing electrostatic damage caused by a low concentration diffusion layer formed around the high concentration diffusion layer and having the same conductivity type as the high concentration diffusion layer is connected between the integrated circuit and the input or output terminal. semiconductor device. 2. The semiconductor device according to claim 1, wherein the low concentration diffusion layer is formed inside the active region or below the element isolation region.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63069552A JPH01243586A (en) | 1988-03-25 | 1988-03-25 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63069552A JPH01243586A (en) | 1988-03-25 | 1988-03-25 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01243586A true JPH01243586A (en) | 1989-09-28 |
Family
ID=13406008
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63069552A Pending JPH01243586A (en) | 1988-03-25 | 1988-03-25 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01243586A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6787400B2 (en) * | 1998-09-02 | 2004-09-07 | Micron Technology, Inc. | Electrostatic discharge protection device having a graded junction and method for forming the same |
JP2009049296A (en) * | 2007-08-22 | 2009-03-05 | Seiko Instruments Inc | Semiconductor device |
-
1988
- 1988-03-25 JP JP63069552A patent/JPH01243586A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6787400B2 (en) * | 1998-09-02 | 2004-09-07 | Micron Technology, Inc. | Electrostatic discharge protection device having a graded junction and method for forming the same |
JP2009049296A (en) * | 2007-08-22 | 2009-03-05 | Seiko Instruments Inc | Semiconductor device |
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