JPH01241840A - Substrate processor - Google Patents

Substrate processor

Info

Publication number
JPH01241840A
JPH01241840A JP63068202A JP6820288A JPH01241840A JP H01241840 A JPH01241840 A JP H01241840A JP 63068202 A JP63068202 A JP 63068202A JP 6820288 A JP6820288 A JP 6820288A JP H01241840 A JPH01241840 A JP H01241840A
Authority
JP
Japan
Prior art keywords
wafer
section
substrate
hand
carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63068202A
Other languages
Japanese (ja)
Other versions
JP2559617B2 (en
Inventor
Yoshiki Iwata
岩田　義樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Canon Marketing Japan Inc
Original Assignee
Canon Inc
Canon Marketing Japan Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc, Canon Marketing Japan Inc filed Critical Canon Inc
Priority to JP6820288A priority Critical patent/JP2559617B2/en
Priority to DE19893909669 priority patent/DE3909669A1/en
Priority to GB8906751A priority patent/GB2217107B/en
Publication of JPH01241840A publication Critical patent/JPH01241840A/en
Application granted granted Critical
Publication of JP2559617B2 publication Critical patent/JP2559617B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67178—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers vertical arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • H01L21/67748—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber horizontal transfer of a single workpiece

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To reduce a floor occupied area and to decrease the cost, shape and size of a substrate processor as a whole by disposing components of the processor vertically. CONSTITUTION:A duct AD for feeding air, a filter AF for further purifying the fed air, a recovery or discharge duct RD for the purified air, a wiring pipe duct HD, a carrier CA and a wafer cassette placing unit IDX are formed. The carrier CA has a mechanism for rotating a stage. Wafer cleaning unit SC coating devices CT1, CT2 form ovens OV1, OV2, and four independent hot plates are provided in the ovens OV1, OV2. Further, developing devices DEV1, DEV2 form wafer conveying inlets WW, WW1-4 and carrier conveying inlet CW to components, which are disposed vertically from a floor for mounting a semiconductor manufacturing apparatus.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、ウェハ等の基板を処理する基板処理装置に関
し、例えば半導体製造工程においてフォトリソグラフィ
用のレジスト膜を塗布により生成する装置、露光後の現
像を行なう装置、ウェハへの不純物をドーピングさせる
膜を塗布により生成する装置、またはウェハ上の素子の
層間絶縁膜もしくはバシヘーション膜を塗布により生成
する装置等に関するものである。Detailed Description of the Invention [Industrial Application Field] The present invention relates to a substrate processing apparatus for processing a substrate such as a wafer, and for example, an apparatus for forming a resist film for photolithography by coating in a semiconductor manufacturing process, The present invention relates to an apparatus for developing a wafer, an apparatus for forming a film for doping a wafer with impurities by coating, or an apparatus for forming an interlayer insulating film or a vacillation film for elements on a wafer by coating.

［従来技術］ 第８図は、塗布部、オープン部、現像部あるいはウェハ
カセット載置部か平面配置された従来の半導体製造装置
の平面配置図である。同図において、ＳＥｌ、ＳＥ２は
ウェハ送出側のウェハカセット載置部、ＰＥＢは露光後
のレジスト膜を強固にするオープン部、ＤＢは塗布前に
ウェハ上の水分を除去するためのオープン部、ＤＥＶは
現像部、ＣＴはレジスト塗布部、ＤＰＢは現像後のレジ
ストを引き締めるためのオープン部、ＣＰＢは塗布後の
レジスト乾燥オープン部、ＲＥＩ。[Prior Art] FIG. 8 is a plan layout diagram of a conventional semiconductor manufacturing apparatus in which a coating section, an open section, a developing section, or a wafer cassette mounting section are arranged on a plane. In the same figure, SEl and SE2 are wafer cassette placement parts on the wafer delivery side, PEB is an open part to strengthen the resist film after exposure, DB is an open part to remove moisture on the wafer before coating, and DEV is the developing section, CT is the resist coating section, DPB is the open section for tightening the resist after development, CPB is the resist drying open section after coating, and REI.

ＲＥ２はウェハ収納側のウェハカセット載置部、ＯＰは
操作パネルを示す。RE2 indicates a wafer cassette mounting section on the wafer storage side, and OP indicates an operation panel.

［発明か解決しようとする課題］ このように従来のこの種の基板処理装置では、装置の各
構成部は平面配置されており、半導体製造工場の高価な
りリーンルームでの床占有面積か大きくなる欠点があっ
た。また、処理手順に従って各部が一列に配置されてい
るため、各部か専有化され共通化による装置の低価格化
や形状寸法の縮小化が計れないという欠点があった。さ
らに、処理手順に依存した構成となるため、複数の処理
工程に対する融通性に欠けるという問題点かあった。[Problem to be solved by the invention] As described above, in the conventional substrate processing apparatus of this type, each component of the apparatus is arranged in a plane, which increases the cost of the semiconductor manufacturing factory and the floor space occupied in the lean room. There were drawbacks. In addition, since each part is arranged in a line according to the processing procedure, each part is proprietary and it is difficult to reduce the cost and size of the device by making it common. Furthermore, since the structure is dependent on the processing procedure, there is a problem in that it lacks flexibility for a plurality of processing steps.

本発明は、上述の従来例の問題点に鑑み、床占有面積を
より少なくし、装置全体として低価格化や形状寸法の縮
小化を計ることかでき、また種々の処理工程に対応でき
るような融通性を有する基板処理装置を提供することを
目的とする。In view of the above-mentioned problems of the conventional method, the present invention has been developed to reduce the floor area, reduce the cost and size of the entire device, and adapt to various processing steps. An object of the present invention is to provide a flexible substrate processing apparatus.

同時に、基板処理装置を装置の各構成部へ清浄な空気ま
たは温調された清浄な空気を送れる構造とし、クリーン
ルーム内の他の装置と基板受は渡しをする部分のみクリ
ーンルームに開口し、さらに装置全体はクリーンルーム
外へ設置することも可能となるようにして、クリーンル
ーム内の占有面積の著しい縮小を計ることを目的とする
。At the same time, the substrate processing equipment is structured so that clean air or temperature-controlled clean air can be sent to each component of the equipment, and other equipment in the clean room and the substrate holder are opened into the clean room only at the parts where they are transferred, and the equipment The purpose is to significantly reduce the area occupied within the clean room by making it possible to install the entire system outside the clean room.

［課題を解決するための手段および作用コ上記の目的を
達成するため、本発明に係る基板処理装置は、膜塗布部
、現像部、オープン部、洗浄部、遠紫外光照射部、膜厚
測定部、現像結果測定部、基板識別記号読取り部、また
は基板カセット載置部等の装置構成部を垂直方向に配置
することとしている。[Means and effects for solving the problem] In order to achieve the above object, the substrate processing apparatus according to the present invention includes a film coating section, a developing section, an open section, a cleaning section, a deep ultraviolet light irradiation section, and a film thickness measurement section. The apparatus components such as a development result measuring section, a substrate identification symbol reading section, and a substrate cassette mounting section are arranged vertically.

これにより、床占有面積が縮小される。This reduces the floor space.

各構成部へのウェハ等の基板の搬入あるいは各構成部か
らの基板搬出はウェハハンド等で行なうとよい。また、
各部の基板搬出入の順序を、一連の組み合せられる処理
手順により任意に設定できるようにし、あるいは一連の
処理手順を複数設定して同時または切替えて動作させら
れるようにすれば便宜である。It is preferable that a wafer hand or the like be used to carry a substrate such as a wafer into or out of each component. Also,
It would be convenient if the order in which the substrates are carried in and out of each part could be arbitrarily set by a series of combined processing procedures, or if a plurality of series of processing procedures could be set and operated simultaneously or by switching.

さらに、各構成部に対してクリーンフィルタを通した清
浄な空気を送れるようにするとよい。Furthermore, it is preferable to send clean air through a clean filter to each component.

［実施例］ 以下、図面を用いて本発明の詳細な説明する。[Example] Hereinafter, the present invention will be explained in detail using the drawings.

第１図は、本発明の一実施例に係る基板処理装置の概略
構成を示す斜視図である。これは本発明の基板処理装置
を半導体製造装置に適用した例である。同図において、
ＡＤは清浄空気または温調空気を送り込むダクト、ＡＦ
は送られた空気をさらに清浄化するフィルタ、ＲＤは清
浄空気の回収または排気ダクト、ＨＤは配線配管ダクト
、ＣＡはキャリア、ＩＤＸはウェハカセット載置部であ
る。なお、キャリアＣＡはステージか回転する機構を有
する。また、ウェハカセット載置部ＩＤＸはカセットエ
レヘータになっていてもよい。あるいは、後述するハン
ド部ＷＨＵのハンドＷＨによってウェハカセット載置部
ＩＤＸの各段のキャリアに収納されたウェハを直接取り
出してもよい。FIG. 1 is a perspective view showing a schematic configuration of a substrate processing apparatus according to an embodiment of the present invention. This is an example in which the substrate processing apparatus of the present invention is applied to a semiconductor manufacturing apparatus. In the same figure,
AD is a duct that sends clean air or temperature-controlled air, AF
is a filter that further cleans the sent air, RD is a clean air recovery or exhaust duct, HD is a wiring piping duct, CA is a carrier, and IDX is a wafer cassette mounting section. Note that the carrier CA has a mechanism for rotating the stage. Moreover, the wafer cassette placement part IDX may be a cassette electric heater. Alternatively, the wafers stored in the carriers at each stage of the wafer cassette placement unit IDX may be directly taken out by the hand WH of the hand unit WHU, which will be described later.

ＳＣはウェハ洗浄ユニット、ＣＴＩ、ＣＴ２は塗布装置
、ＯＶＩ、ＯＶ２はオープン部である。SC is a wafer cleaning unit, CTI and CT2 are coating devices, and OVI and OV2 are open parts.

本実施例においては、オープン部ＯＶＩ、ＯＶ２に独立
したホットプレートが４枚設けられている。なお、この
中の一つを強制ウェハ冷却プレートとして使用すること
もできる。ＤＥＶＩ、ＤＥＶ２は現像装置、ＷＷ、ＷＷ
１〜４は各構成部へのウェハ搬出入口、ＣＷはキャリア
搬出入口である。In this embodiment, four independent hot plates are provided in the open portions OVI and OV2. Note that one of them can also be used as a forced wafer cooling plate. DEVI, DEV2 are developing devices, WW, WW
1 to 4 are wafer loading/unloading ports to each component, and CW is a carrier loading/unloading port.

以上の各構成部は半導体製造装置を設置する床面から垂
直方向に配置されている。Each of the above components is arranged in a direction perpendicular to the floor surface on which the semiconductor manufacturing equipment is installed.

次に、ＷＨＵはウェハを各構成部間で移動するハンド部
全体を示す。このハンド部ＷＨＵは、−点鎖線て示され
ているように上記の垂直配置各部に面して配置される。Next, WHU indicates the entire hand unit that moves the wafer between the components. This hand unit WHU is arranged facing the above-mentioned vertically arranged parts as shown by the dashed line.

ＷＨはウェハを構成部へ出し入れするハンドで矢印Ａ、
Ｂ、Ｃのように前後、左右、上下に動く。なお、ハンド
ＷＨか複数個設けられる場合には、ハンドの機構干渉が
ない構造となっている。WH is the hand that takes the wafer in and out of the component;
Move back and forth, left and right, and up and down like B and C. Note that when a plurality of hands WH are provided, the structure is such that there is no mechanical interference between the hands.

ハンドＷＨの前後方向く矢印Ａの方向）への動作はハン
ド機構ＷＨＢにより行なわれ、このハンド機構ＷＨＢは
さらにウェハを収納てきるボックスになっている。ＷＨ
ＤＩはハンドＷＨを左右方向（矢印Ｂの方向）へ動作さ
せるハンド駆動機構である。ハンド駆動機構ＷＨＤＩは
スライドＳＲに沿ってハンドＷＨを駆動ボールネジＤＳ
により動作させる。ＷＨＤ２はハンドＷＨをスライドＳ
Ｒおよび駆動ポールネジＤＳとともに上下方向（矢印Ｃ
の方向）へ動作させる垂直駆動機構である。The movement of the hand WH in the front-rear direction (in the direction of arrow A) is performed by a hand mechanism WHB, and this hand mechanism WHB is further formed into a box in which a wafer can be stored. W.H.
DI is a hand drive mechanism that moves the hand WH in the left-right direction (in the direction of arrow B). The hand drive mechanism WHDI drives the hand WH along the slide SR using a ball screw DS.
Operate by. WHD2 slides hand WH S
R and drive pole screw DS in the vertical direction (arrow C
This is a vertical drive mechanism that moves the robot in the direction of

なお、各ユニットのウェハ取り出し口は、ハンド方向の
一方向を向いている。ただし、左端・右端ツユニットに
ついては、さらに左・右の側に何らかのウェハ搬送機が
ある場合、取り出し口はそこにも持たせることが可能で
ある。Note that the wafer ejection port of each unit faces one direction, which is the hand direction. However, regarding the left end and right end units, if there is some kind of wafer transport device on the left or right side, the ejection port can also be provided there.

また、各構成部はダクトＡＤ、フィルタＡＦおよび排気
ダクトＲＤにより、常に確実な清浄度を得ることができ
る。In addition, each component can always maintain reliable cleanliness due to the duct AD, filter AF, and exhaust duct RD.

第２図は、第１図の装置のダクトＡＤ、フィルタＡＦお
よび排気ダクトＲＤ等の部分の断面図である。空気（温
調された空気ても良い）は、タクトＡＤからエアフィル
タＡＦを介して矢印のようにユニット内に送られる。こ
のとき、図のようにエアフィルタＡＦの上にファンモー
タＤＭを有していても良い。空気は、ユニット内を層流
状態で通過するように配慮されている。また、空気は排
気ダクトＲＤに回収されるようになっている。さらに、
配線配管ダクトはタクトＡＤ−ＲＤとは隔離されてダク
トＡＤ　−ＲＤの後部に用意されており、この部分は送
風排気は特に実施されていない。FIG. 2 is a cross-sectional view of parts such as the duct AD, filter AF, and exhaust duct RD of the apparatus shown in FIG. Air (temperature-controlled air may be used) is sent into the unit from the tact AD through the air filter AF as shown by the arrow. At this time, a fan motor DM may be provided above the air filter AF as shown in the figure. Air is designed to pass through the unit in a laminar flow. Moreover, air is collected into the exhaust duct RD. moreover,
The wiring piping duct is isolated from the tact AD-RD and is provided at the rear of the duct AD-RD, and this part is not particularly blown and exhausted.

さらに、オープン部０■１．○Ｖ２ては各オープン（ヒ
ーター）の温度設定が自由であり、２つのヒーターをブ
リベータ用、他の２つをボストベーク用として使用する
ことも可能である。Furthermore, open part 0■1. ○In V2, the temperature setting of each open (heater) can be freely set, and it is also possible to use two heaters for bribator and the other two for boss bake.

以下、本実施例に係る装置による塗布処理と現像処理の
手順を説明する。Hereinafter, the procedure of coating processing and developing processing using the apparatus according to this embodiment will be explained.

先ず、ウェハの塗布処理において、ウェハはウェハカセ
ット載置部ＩＤＸに置かれたキャリアＣＡからハンドＷ
Ｈにより取出される。そして、ウェハ洗浄が必要な場合
には、ウェハ洗浄ユニットＳＣに運ばれ洗浄される。そ
の後、ウェハ洗浄ユニットＳＣからハンドＷＨにより取
出され、オープンＯＶ２に運ばれ乾燥される。このよう
にしてハンド部ＷＨＵのハンドＷＨにより次々と各処理
ユニットに運ばれていき、乾燥以後は順次、塗布装置Ｃ
ＴＩにて塗膜され、オープンＯ■１にて焼成され、さら
に塗布が必要であれば塗布装置ＣＴ２にて塗膜され、再
度オープンＯＶ１にて焼成され、キャリアＣＡに戻され
る。First, in the wafer coating process, the wafer is transferred from the carrier CA placed on the wafer cassette placement part IDX to the hand W.
It is taken out by H. If wafer cleaning is required, the wafer is transported to the wafer cleaning unit SC and cleaned. Thereafter, the wafer is taken out from the wafer cleaning unit SC by the hand WH, carried to the open OV2, and dried. In this way, it is carried to each processing unit one after another by the hand WH of the hand unit WHU, and after drying, it is sequentially transferred to the coating device C.
It is coated with a TI, fired with an open O1, and if further coating is required, coated with a coating device CT2, fired again with an open OV1, and returned to the carrier CA.

その後、キャリアＣＡからウェハが取出され、本装置外
の露光ユニットにて露光され再びキャリアＣＡに戻され
る。Thereafter, the wafer is taken out from the carrier CA, exposed to light in an exposure unit outside the apparatus, and returned to the carrier CA again.

次に現像処理のため、露光済のウェハは再度ハンドＷＨ
により取出され現像ユニットＤＥＶＩまたはＤＥＶ２に
運ばれ現像される。現像後は再ひハンドＷＨによりウェ
ハをオープンＯＶＩまたはＯＶ２に運び入れて焼成し、
その後最終キャリアＣＡに戻し、全工程を終了する。Next, for development processing, the exposed wafer is placed in the hand WH again.
is taken out and carried to developing unit DEVI or DEV2, where it is developed. After development, the wafer is carried to the open OVI or OV2 again using the hand WH and baked.
Thereafter, the carrier is returned to the final carrier CA, and the entire process is completed.

なお、本実施例はフォトリングラフィにおけるスピン式
装置およびヘーキング装置等のユニ・ントレイアウトに
よる例として示したか、これ以外にも適用可能であり、
例えばエツチングやＣＶＤ等のユニットレイアウトに対
しても同様の構成を成立たせることが可能である。Note that this embodiment is shown as an example of a unit layout such as a spin type device and a haking device in photolithography, but it is also applicable to other types of devices.
For example, a similar configuration can be established for unit layouts such as etching and CVD.

なお、第１図の装置では、洗浄部ＳＣ，塗布部ＣＴ、オ
ープン部ＯＶＩ、ＯＶ２および現像部ＤＥＶ１．ＤＥＶ
２を組み込んで記載したが、例えば第３図のように構成
することもてきる。同図の構成においては、まずキャリ
アＣＡＩから第１枚目のウェハを取り出し、基板識別記
号読み取り部ＲＥＡＤＩに入れる。そして第１枚目のウ
ェハの識別記号の内容を読み取り、テスト用のウェハで
あることを認識し、塗布部ＣＴＩからオープン部ＯＶＩ
を経由して膜厚測定部ｓｐｔへと入る。これにより膜厚
を測定し、膜厚か基準値内にある場合は、そのまま第２
枚目のウニへの処理へと移っても良いので、第２枚目か
らの処理へと移る。テスト用ウェハの膜厚が基準値内に
ない場合は、塗布部ＣＴＩの回転数を自動的に変更して
第２枚目のウェハからの処理へと穆る。また、この第２
枚目のウェハからの処理に穆るときも、基板識別記号読
み取り部ＲＥＡＤＩにおける読み取りにより、ウェハが
ＣＴ１→ＯＶＩ→ＣＴ２→ＯＶ２と経由するか、それと
もＣＴｌ−０ＶＩまたはＣＴ２→ＯＶ２と経由するかを
認識し、これによりウェハの処理をしていく。In the apparatus shown in FIG. 1, cleaning section SC, coating section CT, open sections OVI, OV2, and developing section DEV1. D.E.V.
2 has been described, but it may also be configured as shown in FIG. 3, for example. In the configuration shown in the figure, the first wafer is first taken out from the carrier CAI and placed in the substrate identification symbol reading section READI. Then, it reads the content of the identification symbol of the first wafer, recognizes that it is a test wafer, and moves it from the coating section CTI to the open section OVI.
It enters the film thickness measuring section spt via . This measures the film thickness, and if the film thickness is within the standard value, the second
You can move on to processing the second sea urchin, so move on to processing from the second sea urchin. If the film thickness of the test wafer is not within the standard value, the rotation speed of the coating section CTI is automatically changed and processing starts from the second wafer. Also, this second
When starting processing from the first wafer, the reading by the substrate identification symbol reading unit READI determines whether the wafer passes through CT1 → OVI → CT2 → OV2, or CTl-0VI or CT2 → OV2. It is recognized and the wafer is processed accordingly.

さらに、第４図のように構成した場合、まずキャリアＣ
ＡＩから第１枚目のウェハを取り出し、基板識別記号読
み取り部ＲＥＡＤＩに入れる。そして、第１枚目のウェ
ハの識別記号の内容を読み取り、ウェハが、ＤＥＶＩま
たはＤＥＶ２→０■１またはＯＶ２→ＤＵＶＩまたはＤ
ｔＪＶ２と経由して処理をするか、ＤＥＶＩまたはＤＥ
Ｖ２→ＯＶ１またはＯＶ２のみの処理をするかを判断し
、処理を進めていく。なお、ここでＤＵＶＩ、ＤＩ■２
は現像処理後のパターンの耐熱性を向上させるための遠
紫外線照射部である。また、この現像部ＤＥＶＩ、ＤＥ
Ｖ２は、現像結果測定部（現像終点検出部）を内蔵して
おり、毎ウニへの現像か適切になるように光学的に検出
てきる部分を有している。Furthermore, if the configuration is as shown in Fig. 4, first the carrier C
The first wafer is taken out from the AI and placed into the substrate identification symbol reading section READI. Then, the contents of the identification symbol of the first wafer are read and the wafer is DEVI or DEV2→0■1 or OV2→DUVI or D.
Process via tJV2 or DEVI or DE
It is determined whether to process V2→OV1 or only OV2, and the process proceeds. In addition, here DUVI, DI■2
is a far ultraviolet irradiation part for improving the heat resistance of the pattern after development processing. In addition, this developing section DEVI, DE
The V2 has a built-in development result measurement section (development end point detection section), and has a part that optically detects the appropriate development for each sea urchin.

本実施例の装置では、オペレータが操作することによっ
て一連の組み合わせられる処理手順か任意に設定できる
。この処理手順に従いホストコンピュータは、ウェハの
搬出入の順序を制御する。In the apparatus of this embodiment, a series of combined processing procedures can be arbitrarily set by an operator's operation. According to this processing procedure, the host computer controls the order of loading and unloading of wafers.

例えは、オペレータか指定可能な処理手順には以下のよ
うなものかある。For example, processing procedures that can be specified by an operator include the following.

■インデクサＩＤＸに置かれたキャリアＣＡ中のウェハ
を次のように移動し処理する。(2) The wafer in the carrier CA placed on the indexer IDX is moved and processed as follows.

キャリアＣＡ→塗布部ＣＴＩ→オープン部ＯＶ１→キャ
リアＣＡ これは塗布後ヘーキングするのみの処理を指定したもの
である。Carrier CA→Coating part CTI→Open part OV1→Carrier CA This designates the process of only haking after coating.

■インデクサＩＤＸに置かれたキャリアＣＡ中のウェハ
を次のように移動し処理する。(2) The wafer in the carrier CA placed on the indexer IDX is moved and processed as follows.

キャリアＣＡ→塗布部ＣＴＩ→オープン部ＯＶＩ→塗布
部ＣＴ２→オープン部ＯＶ２→キャリアＣＡ ■インデクサＩＤＸに置かれたキャリアＣＡ中のウェハ
を次のように移動し処理する。Carrier CA→coating section CTI→open section OVI→coating section CT2→open section OV2→carrier CA ■The wafer in carrier CA placed on indexer IDX is moved and processed as follows.

キャリアＣＡ−洗浄部ｓｃ−オープン部ＯＶ２→塗布部
ＣＴＩ→オープン部ＯＶＩ→キャリアＣＡ ■インデクサＩＤＸに置かれたキャリアＣＡ中のウェハ
を次のように移動し処理する。Carrier CA - Cleaning section sc - Open section OV2 -> Coating section CTI -> Open section OVI -> Carrier CA (1) The wafer in carrier CA placed on indexer IDX is moved and processed as follows.

キャリアＣＡ→現像部ＤＥＶＩまたはＤＥＶ２→オープ
ン部ＯＶＩまたはＯＶ２→キャリアＣＡ 以上のようにオペレータの操作によってウェハのプロセ
ス順序を指定し、ホストコンピュータはその指定された
プロセスに従ってウェハを処理していく。Carrier CA→Developing section DEVI or DEV2→Open section OVI or OV2→Carrier CA As described above, the operator specifies the process order of the wafer, and the host computer processes the wafer according to the specified process.

さらに、本実施例の装置では、一連の処理手順を複数設
定し同時あるいは切替えて動作させることもてきる。例
えば、キャリアが複数個設置されていた場合に、Ａキャ
リアのウェハは塗布部ＣＴ１からオープン部ＯＶＩを経
由した処理へ、Ｂキャリアのウェハは現像部ＤＥＶＩま
たはＤＥＶ２からオープン部ＯＶ２を経由した処理へ、
というように設定すれは、各ユニットのレディまたはヒ
ジー状態をホストコンピュータが判断しながらハンドＷ
Ｈか各キャリアのウェハを自動的に移動しつつ処理を進
めていくことかできる。Furthermore, in the apparatus of this embodiment, a plurality of series of processing procedures can be set and operated simultaneously or in a switched manner. For example, if multiple carriers are installed, wafers in carrier A will be processed from coating section CT1 via open section OVI, and wafers on carrier B will be processed from developing section DEVI or DEV2 via open section OV2. ,
In this setting, the host computer determines whether each unit is ready or not and when the hand W is
It is possible to proceed with processing while automatically moving the wafers in each carrier.

また、第５図に示すように、本実施例の装置の各部を集
中的に制御する集中コントロールモニタＨＣを、ホスト
ＣＰＵと接続した状態で制御室（装置の入っている場所
とは違う室）にもっていき制御監視用として用いること
もてきる。In addition, as shown in FIG. 5, the central control monitor HC, which centrally controls each part of the device of this embodiment, is connected to the host CPU in a control room (a room different from where the device is located). It can also be used for control and monitoring purposes.

また、各構成部にはサブハンドをもたせることができる
。第６図（ａ）　、　（ｂ）　、　（ｃ）は、第１図に
示す装置の塗布装置ＣＴｌ内にサブハンドをもたせた様
子を示す要部の斜視図および断面図である。Further, each component can have a sub-hand. 6(a), 6(b), and 6(c) are a perspective view and a sectional view of the main parts of the apparatus shown in FIG. 1, showing a state in which the sub-hand is placed in the coating device CTl.

同図（ａ）　、　（ｂ）　、　（ｃ）においで、ＨＤは
ハンド、ＣＨはチャック、ＣＰはカップ、ＣＢＨはサブ
ハンド、ＳＲはスライドレール、ＲＧはラックギヤ、Ｐ
Ｇはピニオンギヤ、ＣＹＩ〜３はシリンダ、Ｗｌ、Ｗ２
はウェハを示す。シリンダＣＹ２は第３図（ｃ）に示す
ようにベースに固定されており、シリンダＣＹＩとシリ
ンダＣＹ２はリンク固定されている。In (a), (b), and (c) of the same figure, HD is the hand, CH is the chuck, CP is the cup, CBH is the subhand, SR is the slide rail, RG is the rack gear, and P
G is pinion gear, CYI~3 is cylinder, Wl, W2
indicates a wafer. Cylinder CY2 is fixed to the base as shown in FIG. 3(c), and cylinder CYI and cylinder CY2 are linked and fixed.

本サブハンドは、ウェハセンタリング機能前クエハハッ
ファ機能を有する。すなわち、第６図（ｂ）に示すよう
にサブハンドＣＢＨの上部はバッファ域になり処理済の
ウェハＷ２を保持することができ、また処理前のウェハ
Ｗ１をチャックＣＨ上に載置する際にそのセンタリング
を行なうことができる。This sub-hand has a quench huffer function before a wafer centering function. That is, as shown in FIG. 6(b), the upper part of the sub-hand CBH becomes a buffer area that can hold the processed wafer W2, and when placing the unprocessed wafer W1 on the chuck CH. Centering can be performed.

この動作を説明する。先ず、チャックＣＨ上に載置され
ている処理済ウェハＷ２をチャックＣＨにより紙面の上
方に突ぎ上げる。その後、シリンダＣＹＩを縮め、ラッ
クギヤＲＧおよびピニオンギヤＰＧの働きによりサブハ
ンドＣＢＨの２つのアームの幅を狭める。そして、チャ
ックＣＨを下げることによりサブハンドＣＢＨ上にウェ
ハｗ２を載せる。これが終わるとシリンダＣＹ３により
サブハンドＣＢＨを紙面の上方に上昇させる。これによ
りウェハＷ２かバッファリングされる。This operation will be explained. First, the processed wafer W2 placed on the chuck CH is pushed up above the plane of the paper by the chuck CH. Thereafter, the cylinder CYI is contracted, and the width of the two arms of the sub-hand CBH is narrowed by the action of the rack gear RG and pinion gear PG. Then, by lowering the chuck CH, the wafer w2 is placed on the sub-hand CBH. When this is finished, the cylinder CY3 raises the sub-hand CBH above the plane of the paper. As a result, wafer W2 is buffered.

次に、処理前ウェハＷ１をハンドＨＤによりカップＣＰ
上に運び入れる。そして、再びチャックＣＨを上昇させ
ウェハＷ１をチャックＣＨ上に受は取る。ハンドＨＤは
カップＣＰ上から一度逃げる。この時シリンダＣＹ２か
縮むことにより、わずかにハンドＣＢＨのアームが挟ま
り、ウェハＷ１のセンタとチャックセンタが完全に合致
する。Next, the unprocessed wafer W1 is transferred to the cup CP by hand HD.
carry it upstairs. Then, the chuck CH is raised again and the wafer W1 is placed on the chuck CH. Hand HD once escaped from above cup CP. At this time, as the cylinder CY2 contracts, the arm of the hand CBH is slightly pinched, and the center of the wafer W1 and the chuck center are completely aligned.

第６図（ｂ）はこのときの状態を示している。次に、チ
ャックＣ）（は真空によりウェハＷ１を吸着する。そし
て、再びシリンダＣＹ２か動作しわずかにサブハンドＣ
ＢＨか開き、チャックＣＨはウェハＷ１を吸着したまま
下降する。再ひハンドＨＤがカップＣＰ上に差し入れら
れ、その後シリンダＣＹ３によりサブハンドＣＢＨが下
降しハンドＨＤ上にウェハＷ２を受は渡し、ハンドＨＤ
は再び縮み次の処理へ移行する。なお、これと同時にシ
リンダＣＹＩが開きサブハンドＣＢＨはカップＣＰ上か
ら逃げ、ウェハＷ１の処理を始める状態となる。FIG. 6(b) shows the state at this time. Next, the chuck C) (holds up the wafer W1 by vacuum. Then, the cylinder CY2 operates again and the sub-hand C)
BH opens, and chuck CH descends while holding wafer W1. The hand HD is again inserted onto the cup CP, and then the sub hand CBH is lowered by the cylinder CY3 and the wafer W2 is transferred onto the hand HD.
shrinks again and moves on to the next process. Incidentally, at the same time, the cylinder CYI opens and the sub-hand CBH escapes from above the cup CP, and is in a state to start processing the wafer W1.

第７図は、第１図の装置のオープン部例えばＯ■１０１
つのユニットを示す。これはオープン内にサブハンドを
設け、ウェハがオーバーベークされないようにホットプ
レートを設けた加熱室から一定時間の後にサブハンドに
てウェハを取り出すようにした例である。FIG. 7 shows the open part of the device shown in FIG.
Shows two units. This is an example in which a sub-hand is provided in an open space, and the wafer is taken out by the sub-hand after a certain period of time from a heating chamber provided with a hot plate to prevent the wafer from being overbaked.

同図において、ハンドＨＤからオープンチャックＣＨＯ
にウェハを受は取ると、シリンダＣＹ４が駆動してユニ
ット全体をアップしサブハンドＳＢＨ上にウェハを受は
取る。サブハンドＳＢＨはモータＭ１の駆動により左に
動作し、オープン０■上にウェハを搬入しシリンダＣＹ
４によるユニット全体のダウンでウェハをオープン０■
上に置く。そして、サブハンドＳＢＨは再びモータＭ１
の駆動により元の位置へ戻る。オープンＯ■でのベーキ
ングがある一定時間たつと、サブハンドＳＢＨは前記の
逆動作によりウェハをオープンチャックＣＨＤ上に戻す
ことかてぎる。In the same figure, from the hand HD to the open chuck CHO
When the wafer is picked up, the cylinder CY4 is driven to raise the entire unit and pick up the wafer onto the sub hand SBH. The sub hand SBH moves to the left by the drive of the motor M1, carries the wafer onto the open 0■, and moves the wafer to the cylinder CY.
The wafer is opened when the entire unit is down due to 4.0■
put on top. Then, the sub hand SBH is operated by the motor M1 again.
Returns to the original position by driving. After a certain period of time of baking in the open O2, the subhand SBH returns the wafer onto the open chuck CHD by the reverse operation described above.

スピン式処理装置による塗布のプロセスおよびベータ等
のプロセスが重複する場合、横列配置のものでは第８図
に示すように非常に膨大な装置専有面積をとる必要があ
る。しかし、上記実施例に示すような装置によれは、装
置を縦に延ばすため、ある限られた小面積に配置するこ
とができ、装置占有面積が小さくなる。When the coating process using the spin-type processing apparatus and the process such as beta are overlapped, the horizontally arranged apparatus needs to occupy a very large area as shown in FIG. However, with the device shown in the above embodiment, since the device is extended vertically, it can be placed in a small, limited area, reducing the area occupied by the device.

また、従来は横列配置てあったため、例えは第９図の平
面配置図に示すような装置配列で、ＳＯＧ　ＣＴ　（５
ＰＩＮ　ＯＮ　ＧＬＡＳＳコーター）のみ使用したい場
合には、Ｂ３．Ｂ、をセンダ、Ｂ５．Ｂ６をレシーバと
して使わなければならないというような制約があった。In addition, since conventionally the equipment was arranged in rows, for example, the SOG CT (5
If you want to use only PIN ON GLASS coater, use B3. Send B, B5. There were restrictions such as having to use B6 as a receiver.

しかし、上記実施例に示すような装置によれは、このよ
うな制約はなく、途中でプロセスを変更したい場合ても
同一キャリアステーションからウェハの取り出しが可能
である。However, with the apparatus shown in the above embodiment, there is no such restriction, and even if it is desired to change the process midway through, wafers can be taken out from the same carrier station.

本実施例の装置によれは、無駄なバッファステーション
（第９図の８１〜Ｂ６）がなくなり、各ユニット間（例
えば第９図のＳからＣ７間）にハンドを必要としないた
め、低価格化か図れる。また、装置自体か清浄度を上げ
ることかできるため、ユーザクリーンルームの価格を下
げることかできる。The device of this embodiment eliminates unnecessary buffer stations (81 to B6 in FIG. 9) and does not require a hand between each unit (for example, between S and C7 in FIG. 9), resulting in lower costs. It can be planned. Furthermore, since the cleanliness of the equipment itself can be increased, the cost of the user's clean room can be reduced.

さらに、各ユニットにおいてクリーンネス、温調の必要
な部分を局所的にコントロールすることができるため、
常にコンスタントの条件を実現できる。また、ハンドリ
ング中のウェハは常に収納ケース内に納って搬送される
ため、ウェハ上へ異物が乗る心配もない。Furthermore, since it is possible to locally control areas that require cleanliness and temperature control in each unit,
Constant conditions can always be achieved. Furthermore, since the wafer being handled is always transported while being stored in the storage case, there is no fear of foreign matter getting on the wafer.

［発明の効果コ 以上説明したように、本発明によれば、基板処理装置の
各構成部を垂直方向に配置しているので、床占有面積が
縮小でき、装置全体として低価格化や形状寸法の縮小化
を計ることができる。[Effects of the Invention] As explained above, according to the present invention, since each component of the substrate processing apparatus is arranged vertically, the floor area occupied can be reduced, and the overall cost of the apparatus can be reduced and the shape and size can be reduced. It is possible to reduce the size of

また、比較的清浄度の低いクリーンルーム内でも、本発
明による装置内は清浄度を高く保つことができ、ウェハ
に対する汚染を少なくすることが可能となる。Moreover, even in a clean room with relatively low cleanliness, the inside of the apparatus according to the present invention can maintain a high level of cleanliness, making it possible to reduce contamination of wafers.

さらに、処理工程に関して非常に融通性が向上し、半導
体の試作や研究を行なうような研究所、工場、あるいは
多品種少量生産の工場ての多目的使用等が可能となる。Furthermore, the flexibility of the processing process is greatly improved, allowing multi-purpose use in laboratories and factories for prototyping and research of semiconductors, and factories for high-mix, low-volume production.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本発明の一実施例に係る基板処理装置の概略
構成を示す斜視図、 第２図は、第１図に示す装置のダクトＡＤ、フィルタＡ
Ｆおよび排気タクトＲＤ等の部分の断面図、 第３図および第４図は、本発明の他の実施例に係る基板
処理装置の概略構成を示す正面図、第５図は、集中コン
トロールモニタＨＣを制御室に配置する例を示すブロッ
ク図、 第６図は、第１図に示す装置の塗布装置内にサブハンド
をもたせた様子を示す要部の斜視図および断面図、 第７図は、第１図の装置のオープン部の１つのユニット
を示す斜視図、 第８図および第９図は、各構成部が平面配置された従来
の半導体製造装置の平面配置図である。 ＡＤ、ＲＤ・ダクト、　　　ＡＦ：フィルタ、ＨＤ　　
配線配管ダクト、　ＣＡ・キャリア、ＩＤＸ：ウニへカ
セット載置部、 ＳＣ＋ウェハ洗浄ユニット、 ＣＴ１．ＣＴ２：塗布装置、 ＯＶｌ、ＯＶ２・オープン部、 ＤＥＶｌ、ＤＥＶ２：現像装置、 ＷＷ、ＷＷＩ〜ＷＷ４：ウェハ搬出入口、ＣＷ：キャリ
ア搬出入口、 ＷＨＵ：ハンド部全体、　ＷＨ；ハンド上Ｃ：集中コン
トロールモニタ ＨＤ：ハンド、　　　　ＣＨ，チャック、ｃｐ・カップ
、　　　　ＣＢＨ：サブハンド、ＳＲニスライドレール
、ＲＧニラツクギヤ、ＰＧ　　ピニオンギヤ、　　ＣＹ
１〜４ニジリンダ、Ｗｌ、Ｗ：ｌウェハ、 ＣＨＯ：オープンチャック、 ＳＢＨサブハンド、　　ＯＶ、オープン、Ｍｌ・駆動モ
ータ。 ５ＰＩｌ　　　凶 第３図 Ｑｐ 第４図 （ｂ） （Ｃ） 第６図FIG. 1 is a perspective view showing a schematic configuration of a substrate processing apparatus according to an embodiment of the present invention, and FIG. 2 shows a duct AD and a filter A of the apparatus shown in FIG.
3 and 4 are front views showing a schematic configuration of a substrate processing apparatus according to another embodiment of the present invention, and FIG. 5 is a sectional view of parts such as F and exhaust tact RD. FIG. 6 is a perspective view and a cross-sectional view of the main parts of the apparatus shown in FIG. FIG. 1 is a perspective view showing one unit of the open part of the apparatus, and FIGS. 8 and 9 are plan layout diagrams of a conventional semiconductor manufacturing apparatus in which each component is arranged in a plane. AD, RD/Duct, AF: Filter, HD
Wiring piping duct, CA/carrier, IDX: Sea urchin cassette loading section, SC+wafer cleaning unit, CT1. CT2: Coating device, OVl, OV2/open section, DEVl, DEV2: Developing device, WW, WWI~WW4: Wafer loading/unloading entrance, CW: Carrier loading/unloading entrance, WHU: Entire hand section, WH: Above hand C: Centralized control monitor HD: Hand, CH, Chuck, CP/Cup, CBH: Sub-hand, SR Ni-Ride Rail, RG Nirakku Gear, PG Pinion Gear, CY
1 to 4 Niji cylinder, Wl, W: l wafer, CHO: open chuck, SBH sub hand, OV, open, Ml/drive motor. 5PIl Figure 3 Qp Figure 4 (b) (C) Figure 6

Claims (5)

【特許請求の範囲】[Claims] （１）膜塗布部、現像部、オープン部、洗浄部、遠紫外
光照射部、膜厚測定部、現像結果測定部、基板識別記号
読取り部、または基板カセット載置部等の各装置構成部
を垂直方向に配置したことを特徴とする基板処理装置。(1) Each device component such as film application section, development section, open section, cleaning section, far ultraviolet light irradiation section, film thickness measurement section, development result measurement section, substrate identification symbol reading section, or substrate cassette mounting section. 1. A substrate processing apparatus characterized in that: are arranged in a vertical direction. （２）前記各構成部への基板搬入あるいは各構成部から
の基板搬出を基板ハンドで行なう特許請求の範囲第１項
に記載の基板処理装置。(2) The substrate processing apparatus according to claim 1, wherein a substrate hand is used to carry a substrate into or take out a substrate from each component. （３）前記各構成部の基板搬出入の順序を、一連の組み
合せられる処理手順により任意に設定できる特許請求の
範囲第１項または第２項に記載の基板処理装置。(3) The substrate processing apparatus according to claim 1 or 2, wherein the order in which substrates are carried in and out of each component can be arbitrarily set by a series of combined processing procedures. （４）一連の処理手順を複数設定し、同時あるいは切替
えて動作させられる特許請求の範囲第１項ないし第３項
のいずれか１つに記載の基板処理装置。(4) The substrate processing apparatus according to any one of claims 1 to 3, wherein a plurality of series of processing procedures can be set and operated simultaneously or in a switched manner. （５）前記各構成部に対しクリーンフィルタを通した清
浄な空気を送る手段を具備する特許請求の範囲第１項な
いし第４項のいずれか１つに記載の基板処理装置。(5) The substrate processing apparatus according to any one of claims 1 to 4, further comprising means for sending clean air through a clean filter to each of the constituent parts.
JP6820288A 1988-03-24 1988-03-24 Substrate processing equipment Expired - Lifetime JP2559617B2 (en)

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JP6820288A JP2559617B2 (en) 1988-03-24 1988-03-24 Substrate processing equipment
DE19893909669 DE3909669A1 (en) 1988-03-24 1989-03-23 DEVICE FOR MACHINING WORKPIECES
GB8906751A GB2217107B (en) 1988-03-24 1989-03-23 Workpiece processing apparatus

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JP6820288A JP2559617B2 (en) 1988-03-24 1988-03-24 Substrate processing equipment

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JPH01241840A true JPH01241840A (en) 1989-09-26
JP2559617B2 JP2559617B2 (en) 1996-12-04

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Also Published As

Publication number Publication date
GB2217107A (en) 1989-10-18
JP2559617B2 (en) 1996-12-04
GB8906751D0 (en) 1989-05-10
GB2217107B (en) 1992-09-23
DE3909669C2 (en) 1992-06-04
DE3909669A1 (en) 1989-10-05

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