JPH012343A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPH012343A JPH012343A JP62-158227A JP15822787A JPH012343A JP H012343 A JPH012343 A JP H012343A JP 15822787 A JP15822787 A JP 15822787A JP H012343 A JPH012343 A JP H012343A
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- semiconductor element
- conductor wiring
- semiconductor
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 48
- 239000000758 substrate Substances 0.000 claims description 33
- 239000004020 conductor Substances 0.000 claims description 22
- 229920005989 resin Polymers 0.000 claims description 13
- 239000011347 resin Substances 0.000 claims description 13
- 238000005476 soldering Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 description 13
- 230000000694 effects Effects 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229910015365 Au—Si Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置に関し、特にマルチチップモジュー
ルの高密度パッケージング構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor devices, and more particularly to high-density packaging structures for multi-chip modules.
従来の技術
マルチチップモジュールに半導体素子を実装する従来法
としては、ワイヤボンディング、フィルムキャリア方式
やフィリップチップ方式が公知であるが、ワイヤボンデ
ィングやフィルムキャリア方式では、配線部の面積ロス
が大きい為、高密度に半導体素子を実装する場合には、
現在フィリップチップ方式が主に用いられている５、こ
の方式では第２図に示した様に半導体素子２１の電！侃
パッド上に形成した突起電極２２と、Ｐ、縁性」、（仮
２３上の導体配線２４とが位置合わせされた状態のま１
加圧されて半田づけされていることにより、半導体素子
２２と導体配線２４とが電気的に接続されている。この
ため、この方式ではワイヤを必要とせず、しかも接続が
一括して行えるといった長所を有する。Conventional technology Wire bonding, film carrier method, and Philips chip method are known as conventional methods for mounting semiconductor elements on multi-chip modules. When mounting semiconductor elements at high density,
At present, the Philip chip method is mainly used.5 In this method, as shown in FIG. The protruding electrode 22 formed on the side pad and the conductor wiring 24 on the temporary 23 are aligned.
The semiconductor element 22 and the conductor wiring 24 are electrically connected by being pressurized and soldered. Therefore, this method has the advantage that it does not require wires and can be connected all at once.
発明が解決しようとする問題点
しかしながらフィリップチップ方式では以下に示す問題
点を有する。Problems to be Solved by the Invention However, the Philips chip method has the following problems.
（１）熱拡散がバンプからの熱伝導のみであるので熱抵
抗は高く、チップ裏面に放熱板を取り付ける等の工夫を
してやらねばならない。(1) Thermal resistance is high because heat is diffused only through heat conduction from the bumps, so it is necessary to take measures such as attaching a heat sink to the back of the chip.
（２）半導体素子の配線基板への固定が電極部のみで行
うため、外部からの熱や機械的歪により絶縁性基板が膨
張したりそったりした場合に、接続部での破壊が生じや
すい。(2) Since the semiconductor element is fixed to the wiring board only by the electrode portion, if the insulating substrate expands or warps due to external heat or mechanical strain, the connection portion is likely to be damaged.
（３）半導体素子が外部にむき出しの構造を取るため、
コーティングやモールド等の保護処理を行わねばならな
い。(3) Since the semiconductor element has a structure exposed to the outside,
Protective treatments such as coating and molding must be applied.
問題点を解決するための手段
本発明は前記問題点を解決するために、半導体素子を裏
面より絶縁性基板に固着し、これを２ｍくみ合わせ、半
導体素子の電極をそれと向かい合う反対側の基板の導体
配線と接触により電気的に接続させ、そのままの状態で
位置ずれせぬ様に固定するといった方法を用いるもので
ある。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention fixes a semiconductor element to an insulating substrate from the back side, joins them together by 2 m, and connects the electrodes of the semiconductor element to the opposite substrate. A method is used in which the wire is electrically connected by contact with the conductor wiring and fixed in that state so as not to shift.
作 用
本発明は前記構造を取ることにより半導体素子の絶縁性
基板への接続が半導体素子の裏面を一面に使って行われ
るため、半導体素子の内部で生じた熱が裏面より速やか
に放散され、しかも接続部では高い機械的強度が得られ
る。更に半導体素子及び導体配線を外側に配した構造で
あるため、半導体素子及び導体配線が保護される。Function The present invention employs the above structure so that the semiconductor element is connected to the insulating substrate using the entire back surface of the semiconductor element, so that heat generated inside the semiconductor element is dissipated more quickly from the back surface. Moreover, high mechanical strength can be obtained at the connection portion. Furthermore, since the semiconductor element and the conductor wiring are arranged on the outside, the semiconductor element and the conductor wiring are protected.
実施例
本発明の実施例を第１図を用いてその工程とともに説明
する。まず第１図ａに示した様に第１の半導体素子２を
第１の絶縁性基板４の所定の位置にダイボンディングに
より固着する。更に第２の絶縁性基板９にも同様の方法
で第２の半導体素子７を固着するうダイボンディングの
方法にはＡｕ −Ｓ ｉ用品接合やはんだ接合等の手法
を用いる。更に第１の絶縁性基板４の導体配線６と第２
絶縁性基板９の導体配線５をフレキシブル基板で接続し
た後、第１図すに示した様に第１の半導体素子２の電極
１を有する面から絶縁性基板４の導体配線６を有する面
にわたって絶縁性の接続樹脂１１を塗布する。接続樹脂
１１には熱硬化型、又は紫外線硬化型のエポキシ系、シ
リコン系、アクリル系等の樹脂を用いる。接続樹脂１１
の塗布方法としてはデイスペンサー等を用いる。EXAMPLE An example of the present invention will be described with reference to FIG. 1, together with its steps. First, as shown in FIG. 1a, the first semiconductor element 2 is fixed at a predetermined position on the first insulating substrate 4 by die bonding. Further, the second semiconductor element 7 is fixed to the second insulating substrate 9 in a similar manner using a die bonding method such as Au-Si component bonding or solder bonding. Furthermore, the conductor wiring 6 of the first insulating substrate 4 and the second
After connecting the conductor wiring 5 of the insulating substrate 9 with the flexible substrate, as shown in FIG. An insulating connection resin 11 is applied. For the connection resin 11, a thermosetting or ultraviolet curing resin such as epoxy, silicone, or acrylic resin is used. Connection resin 11
A dispenser or the like is used as the application method.
次にフレキシブル基板を折り曲げ第１図Ｃに示す様に第
１の半導体素子２の電極１を第２の絶縁性基板９の導体
配線１ｏ第２の半導体素子７の電極６を第１の絶縁性基
板４の導体配線６にそれぞれ位置合わせ１−１位置ずれ
せぬ様加圧ツール１２を用いて加圧する。この際、第１
の半導体素子２の電極１の上や、第２の半導体素子７の
電極ｅ下に存在する接続樹脂１１は加圧により周囲に押
し出され、第１の半導体素子２の電１と第２の絶縁性基
板９の導体配線１０及び、第２の半導体素子７の電極６
と第１の絶縁性基板４の導体配線５とはそれぞれ接触に
より電気的に接続することとなる。この状態のまま接続
樹脂１１を硬化させると、第１図ｄに示した様に加圧ツ
ール１２による加圧を解除した後も各電極と導体配線と
の電気的接続が保持されることになる。接続樹脂１１の
硬化は、接続樹脂１１が熱硬化型である場合には加圧ツ
ール１２に取り付けた加熱部により加熱して行い、樹脂
が紫外線硬化型である場合には側面の間隙より紫外線を
照射することにより行う。Next, the flexible substrate is folded and as shown in FIG. Positioning 1-1 is applied to each of the conductor wirings 6 on the substrate 4 using a pressure tool 12 so as not to shift the position. At this time, the first
The connecting resin 11 existing on the electrode 1 of the semiconductor element 2 and under the electrode e of the second semiconductor element 7 is pushed out to the surroundings by pressure, and the electrode 1 of the first semiconductor element 2 and the second insulation conductor wiring 10 of the conductive substrate 9 and the electrode 6 of the second semiconductor element 7
and the conductor wiring 5 of the first insulating substrate 4 are electrically connected through contact with each other. If the connection resin 11 is cured in this state, the electrical connection between each electrode and the conductor wiring will be maintained even after the pressure applied by the pressure tool 12 is released, as shown in FIG. 1d. . When the connecting resin 11 is a thermosetting type, the connecting resin 11 is cured by heating with a heating section attached to the pressure tool 12, and when the connecting resin 11 is an ultraviolet curing type, ultraviolet rays are applied from the gap on the side. This is done by irradiation.
この際、いずれにおいても接続樹脂１１の硬化温度は半
導体素子を絶縁性基板にダイボンドする温度よりずっと
低い温度であるので、半導体素子と絶縁性基板との接合
は損なわれない。At this time, since the curing temperature of the connecting resin 11 is much lower than the temperature at which the semiconductor element is die-bonded to the insulating substrate, the bonding between the semiconductor element and the insulating substrate is not impaired.
ところで、マルチチップモジュールに半導体素子を搭載
する場合、轟然、各半導体素子間でその厚みに差異が存
在する場合が予期されるが、本発明ではそういった場合
でも半導体素子と絶縁性基板との間に台座を設けたり、
逆に凹部を設ける等の手法を用いることにより容易に対
応することができる。By the way, when semiconductor elements are mounted on a multi-chip module, it is expected that there will be differences in the thickness between each semiconductor element, but in the present invention, even in such a case, there will be a difference in thickness between the semiconductor element and the insulating substrate. Set up a pedestal,
On the contrary, this can be easily dealt with by using a technique such as providing a recessed portion.
発明の効果
以上のように、本発明によれば次のような効果を得るこ
とができる。Effects of the Invention As described above, according to the present invention, the following effects can be obtained.
（１）半導体素子の絶縁性基板への接合が半導体素子の
裏面を一向に使って行われるため、熱放散が容易であり
、しかも高い機械的強度が得られる。(1) Since the semiconductor element is bonded to the insulating substrate using the entire back surface of the semiconductor element, heat dissipation is easy and high mechanical strength can be obtained.
（２）半導体素子及び導体配線を内側に、絶縁性基板を
外側に配した構造であるため、半導体素子及び導体配線
が保護され、高い信頼性が得られる。(2) Since the structure is such that the semiconductor element and conductor wiring are placed inside and the insulating substrate is placed outside, the semiconductor element and conductor wiring are protected and high reliability can be obtained.
（３）第１の実施例においては半導体素子及び導体配線
が接続樹脂により密閉されるので、モールドやコーティ
ングの変わりとすることができる。(3) In the first embodiment, the semiconductor element and the conductor wiring are sealed with the connecting resin, so it can be used instead of molding or coating.
（４）第１の絶縁性基板への半導体素子の固着と第２の
絶縁性基板への半導体素子の固着が同時に並行して進行
して進行でき、かつ絶縁性基板に固着した全ての半導体
の全電極と全導体配線との電気的接合が一括して行える
ので、従来法に比べ比躍的に効率的であり、実装コスト
を低減できる。(4) The fixing of the semiconductor element to the first insulating substrate and the fixing of the semiconductor element to the second insulating substrate can proceed simultaneously and in parallel, and all the semiconductors fixed to the insulating substrate Since all electrodes and all conductor wiring can be electrically connected at once, this method is significantly more efficient than conventional methods and can reduce mounting costs.
（６） 電極と導体配線の接続を半田づけや合金を用
いて行わないので、余剰半田や合金等による電気的短絡
が生じない。(6) Since the electrodes and conductor wiring are not connected using soldering or alloy, electrical short circuits due to excess solder, alloy, etc. do not occur.
以上の様に本発明の実用的効果は非常に多大なものがあ
る。As described above, the practical effects of the present invention are extremely large.
第１図は本発明の一実施例の半導体装置の組み立て工程
を示す断面図、第２図は従来法であるフィリップチップ
方式を示す断面図である。
１．６・・・・・・電極、５，１０・・・・・・導体配
線、２・・・・・・第１の半導体素子、７・・・・・・
第２の半導体素子、４・・・・・・第１の絶縁性基板、
９・・・・・・第２の絶縁性基板、１１・・・・・・接
続樹脂、１２・・・・・・加圧ツーノペ１３・・・・・
・フレキシブル基板。FIG. 1 is a sectional view showing the assembly process of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional Philips chip method. 1.6...Electrode, 5,10...Conductor wiring, 2...First semiconductor element, 7...
second semiconductor element, 4...first insulating substrate,
9...Second insulating substrate, 11...Connecting resin, 12...Pressure tool 13...
・Flexible board.
Claims (3)
、第１の半導体素子の電極が向かい合う第２の絶縁性基
板の導体配線と接触により電気的に接続され、前記第２
の絶縁性基板に固着された前記第２の半導体素子の電極
が前記第１の絶縁性基板の導体配線と接触により電気的
に接続され、前記第１及び第２の半導体素子の電極と前
記第２及び第１の絶縁性基板の導体配線との接触による
電気的接続が保持できる様に圧力が加えられている半導
体装置。(1) A first semiconductor element is fixed to a first insulating substrate, an electrode of the first semiconductor element is electrically connected by contact with a conductor wiring of an opposing second insulating substrate, and the second
The electrodes of the second semiconductor element fixed to the insulating substrate are electrically connected by contact with the conductive wiring of the first insulating substrate, and the electrodes of the first and second semiconductor elements are connected to the conductor wiring of the first insulating substrate. 2 and a semiconductor device to which pressure is applied so as to maintain electrical connection through contact with the conductor wiring of the first insulating substrate.
第２の半導体素子を固着した第２の絶縁性基板とが両者
間に塗布した絶縁性の接続樹脂の硬化により固定され、
第１及び第２の半導体素子の電極と第２及び第１の絶縁
性基板の導体配線との接触による電気的接続が保持され
ている特許請求の範囲第１項記載の半導体装置。(2) the first insulating substrate to which the first semiconductor element is fixed and the second insulating substrate to which the second semiconductor element is fixed are fixed by curing an insulating connecting resin applied between the two;
2. The semiconductor device according to claim 1, wherein electrical connection is maintained through contact between the electrodes of the first and second semiconductor elements and the conductor wiring of the second and first insulating substrates.
の絶縁性基板の導体配線とはんだ付けにより接続されて
いる特許請求の範囲第１項記載の半導体装置。(3) The electrodes of the first and second semiconductor elements are the second and first electrodes.
The semiconductor device according to claim 1, wherein the semiconductor device is connected to the conductor wiring of the insulating substrate by soldering.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15822787A JPS642343A (en) | 1987-06-25 | 1987-06-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15822787A JPS642343A (en) | 1987-06-25 | 1987-06-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH012343A true JPH012343A (en) | 1989-01-06 |
| JPS642343A JPS642343A (en) | 1989-01-06 |
Family
ID=15667056
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15822787A Pending JPS642343A (en) | 1987-06-25 | 1987-06-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS642343A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6502409B1 (en) * | 2000-05-03 | 2003-01-07 | Computer Process Controls, Inc. | Wireless method and apparatus for monitoring and controlling food temperature |
-
1987
- 1987-06-25 JP JP15822787A patent/JPS642343A/en active Pending
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