JPH0122728B2 - - Google Patents

Info

Publication number
JPH0122728B2
JPH0122728B2 JP54133896A JP13389679A JPH0122728B2 JP H0122728 B2 JPH0122728 B2 JP H0122728B2 JP 54133896 A JP54133896 A JP 54133896A JP 13389679 A JP13389679 A JP 13389679A JP H0122728 B2 JPH0122728 B2 JP H0122728B2
Authority
JP
Japan
Prior art keywords
fine pattern
photoresist
workpiece
plasma etching
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54133896A
Other languages
English (en)
Other versions
JPS5656636A (en
Inventor
Yoji Masuko
Hirozo Takano
Sotohisa Asai
Kazuo Mizuguchi
Haruhiko Abe
Sumio Nomoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13389679A priority Critical patent/JPS5656636A/ja
Priority to US06/195,380 priority patent/US4377734A/en
Priority to DE3038185A priority patent/DE3038185C2/de
Publication of JPS5656636A publication Critical patent/JPS5656636A/ja
Publication of JPH0122728B2 publication Critical patent/JPH0122728B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Description

【発明の詳細な説明】 この発明は例えば半導体素子の製造工程などに
適用される微細パターンの加工方法に関するもの
である。
従来のこの種の微細パターンの加工方法を第１
図ないし第４図に示してある。この従来例は、第
１図に示したように、シリコン酸化膜１上に形成
されている多結晶シリコン膜２を所望の微細パタ
ーンに加工する場合であつて、まずこの多結晶シ
リコン膜２上にポジ型のフオトレジスト３を塗布
させたのち、所定のフオトマスクを介して前記フ
オトレジスト３の微細パターンに対応する部分
を、光４により露光させる。ついでこれを現像処
理することにより、第２図に示したように、光が
照射された部分にのみ硬化されたフオトレジスト
３が残る。そしてこのフオトレジスト３をマスク
として前記多結晶シリコン膜２を第３図のように
エツチング除去し、最後に残されたフオトレジス
ト３を同様にエツチング除去することによつて、
多結晶シリコン膜２による所望微細パターンを第
４図のように得るのである。
しかし乍ら従来のこのような微細パターンの加
工方法は、パターンのエツチングマスクにフオト
レジストを使用するために、一般的にその工程が
多くかつ複雑になる傾向を有するばかりか、フオ
トレジストの露光、現像は前記第２図にも見られ
るとおりに、レジストパターンがシヤープに形成
されないために、得られるパターン寸法に誤差を
生じ、微細度合に限度があり、さらにはレジスト
使用による化学処理に伴なう汚染の問題点もある
などの欠点があつた。
この発明は従来のこのような実情に鑑み、被加
工物の表面にプラズマエツチングに対して不動体
を形成する金属イオンを、所望の微細パターンに
対応して注入させ、このようにして得た金属イオ
ン注入層をマスクとして、被加工物をプラズマエ
ツチングすることで微細パターンを加工するよう
にしたものである。
以下、この発明に係わる微細パターン加工方法
の一実施例につき、第５図および第６図を参照し
て詳細に説明する。
この実施例においても、第５図に示したよう
に、シリコン酸化膜１上には被加工物である多結
晶シリコン膜２が形成されており、この多結晶シ
リコン膜２に対して、この実施例ではプラズマエ
ツチングに耐え得て不動体を形成する金属イオ
ン、例えばＷイオン５を、所望の微細パターン形
状となるようにイオン注入する。ついでこれに、
O2，ＣとＦの化合物を含むガスによるプラズマ
エツチングを施すと、前記Ｗの注入された表面に
Ｗの酸化膜６が形成されて、これがプラズマに対
するマスクの役割りをなし、これによつて第６図
にみられるように、多結晶シリコン膜２の微細パ
ターンを加工形成し得るのである。実際にも、表
面に1016／cm3程度のＷを含むSiに、O2を含むプラ
ズマ処理を行なうと、同表面にWO3層が形成さ
れて、これがプラズマに対してほとんど不動体に
なることが知られている。
なお上記実施例は、多結晶シリコン膜の微細パ
ターンを形成する場合について述べたが、他の物
質の微細パターン加工にも適用できることは勿論
であり、また実施例はＷのイオン注入を行なう場
合であるが、Nb，Soなどの金属のように表層部
にプラズマエツチングに対して不動体を形成する
ものであれば、同様の効果を期待できるものであ
る。
以上詳述したようにこの発明によるときは、被
加工物の表面に、プラズマエツチングに対して不
動体を形成する金属イオンを、所望の微細パター
ンに対応して注入させ、ついでこの金属イオン注
入層をマスクとして、被加工物をプラズマエツチ
ングするようにしたから、従来に比較してより少
ない加工工程により、精度の高い微細パターンを
容易かつ簡単に形成でき、しかもフオトレジスト
を用いるものでないため、余分な化学処理を行な
わなくてすみ、清浄な状態での加工ができるなど
の特長を有するものである。
【図面の簡単な説明】
第１図ないし第４図は従来例による微細パター
ンの加工方法を工程順に示す説明図、第５図およ
び第６図はこの発明に係わる微細パターン加工方
法の一実施例を工程順に示す説明図である。 １……シリコン酸化膜、２……多結晶シリコン
膜、５……Ｗイオン、６……Ｗの酸化膜（不動体
膜）。

Claims (1)

    【特許請求の範囲】
  1. １ 被加工物の表面に、プラズマエツチングに対
    して不動体を形成する金属イオンを、所望の微細
    パターンに対応して注入したのち、これをプラズ
    マエツチングして、微細パターンを形成すること
    を特徴とする微細パターンの加工方法。
JP13389679A 1979-10-13 1979-10-13 Processing method of fine pattern Granted JPS5656636A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP13389679A JPS5656636A (en) 1979-10-13 1979-10-13 Processing method of fine pattern
US06/195,380 US4377734A (en) 1979-10-13 1980-10-09 Method for forming patterns by plasma etching
DE3038185A DE3038185C2 (de) 1979-10-13 1980-10-09 Verfahren zum Ätzen eines Musters aus einer Schicht

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13389679A JPS5656636A (en) 1979-10-13 1979-10-13 Processing method of fine pattern

Publications (2)

Publication Number Publication Date
JPS5656636A JPS5656636A (en) 1981-05-18
JPH0122728B2 true JPH0122728B2 (ja) 1989-04-27

Family

ID=15115633

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13389679A Granted JPS5656636A (en) 1979-10-13 1979-10-13 Processing method of fine pattern

Country Status (3)

Country Link
US (1) US4377734A (ja)
JP (1) JPS5656636A (ja)
DE (1) DE3038185C2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3002419U (ja) * 1994-03-28 1994-09-27 株式会社田原大 帯 地

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4438556A (en) * 1981-01-12 1984-03-27 Tokyo Shibaura Denki Kabushiki Kaisha Method of forming doped polycrystalline silicon pattern by selective implantation and plasma etching of undoped regions
JPS59184528A (ja) * 1983-04-04 1984-10-19 Mitsubishi Electric Corp 薄膜のパタ−ン形成方法
JPS6022321A (ja) * 1983-07-18 1985-02-04 Mitsubishi Electric Corp Ｘ線露光用マスクのマスクパタ−ン形成方法
US4554728A (en) * 1984-06-27 1985-11-26 International Business Machines Corporation Simplified planarization process for polysilicon filled trenches
US4601778A (en) * 1985-02-25 1986-07-22 Motorola, Inc. Maskless etching of polysilicon
DE3682395D1 (de) * 1986-03-27 1991-12-12 Ibm Verfahren zur herstellung von seitenstrukturen.
US5186788A (en) * 1987-07-23 1993-02-16 Matsushita Electric Industrial Co., Ltd. Fine pattern forming method
US4880493A (en) * 1988-06-16 1989-11-14 The United States Of America As Represented By The United States Department Of Energy Electronic-carrier-controlled photochemical etching process in semiconductor device fabrication
US4968552A (en) * 1989-10-13 1990-11-06 International Business Machines Corp. Versatile reactive ion etch barriers from polyamic acid salts
US5236547A (en) * 1990-09-25 1993-08-17 Kabushiki Kaisha Toshiba Method of forming a pattern in semiconductor device manufacturing process
DE19901210A1 (de) * 1999-01-14 2000-07-27 Siemens Ag Halbleiterbauelement und Verfahren zu dessen Herstellung
EP1228528B1 (en) 1999-09-10 2014-08-13 Oerlikon USA Inc. Magnetic pole fabrication process and device
US6547975B1 (en) 1999-10-29 2003-04-15 Unaxis Usa Inc. Magnetic pole fabrication process and device
JP2002025986A (ja) * 2000-07-06 2002-01-25 Matsushita Electric Ind Co Ltd ドライエッチング方法
US20050100673A1 (en) * 2002-05-22 2005-05-12 Ulrich Schoof Method for the surface treatment of a doctor element
US6863930B2 (en) 2002-09-06 2005-03-08 Delphi Technologies, Inc. Refractory metal mask and methods for coating an article and forming a sensor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5461477A (en) * 1977-10-26 1979-05-17 Cho Lsi Gijutsu Kenkyu Kumiai Method of machining by electron beam or ion beam irradiation

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US3615935A (en) * 1967-05-22 1971-10-26 Westinghouse Electric Corp Fabrication of semiconductor devices utilizing bombardment-enhanced etching of insulating layers
US3915757A (en) * 1972-08-09 1975-10-28 Niels N Engel Ion plating method and product therefrom
US3808068A (en) * 1972-12-11 1974-04-30 Bell Telephone Labor Inc Differential etching of garnet materials
JPS52128066A (en) * 1976-04-20 1977-10-27 Matsushita Electronics Corp Manufacture of semiconductor device
US4057895A (en) * 1976-09-20 1977-11-15 General Electric Company Method of forming sloped members of N-type polycrystalline silicon
US4074139A (en) * 1976-12-27 1978-02-14 Rca Corporation Apparatus and method for maskless ion implantation
US4092209A (en) * 1976-12-30 1978-05-30 Rca Corp. Silicon implanted and bombarded with phosphorus ions
US4093503A (en) * 1977-03-07 1978-06-06 International Business Machines Corporation Method for fabricating ultra-narrow metallic lines
DE2717400C2 (de) * 1977-04-20 1979-06-21 Gesellschaft Fuer Schwerionenforschung Mbh, 6100 Darmstadt Ätzverfahren zur Herstellung von Strukturen unterschiedlicher Höhe
JPS5531154A (en) * 1978-08-28 1980-03-05 Hitachi Ltd Plasma etching apparatus

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5461477A (en) * 1977-10-26 1979-05-17 Cho Lsi Gijutsu Kenkyu Kumiai Method of machining by electron beam or ion beam irradiation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3002419U (ja) * 1994-03-28 1994-09-27 株式会社田原大 帯 地

Also Published As

Publication number Publication date
JPS5656636A (en) 1981-05-18
US4377734A (en) 1983-03-22
DE3038185C2 (de) 1985-10-24
DE3038185A1 (de) 1981-04-23

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