JPH01217935A - Manufacture of semiconductor device and apparatus thereof - Google Patents
Manufacture of semiconductor device and apparatus thereofInfo
- Publication number
- JPH01217935A JPH01217935A JP63042073A JP4207388A JPH01217935A JP H01217935 A JPH01217935 A JP H01217935A JP 63042073 A JP63042073 A JP 63042073A JP 4207388 A JP4207388 A JP 4207388A JP H01217935 A JPH01217935 A JP H01217935A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- wafer
- balls
- bonding
- hydrogen flame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 229910000679 solder Inorganic materials 0.000 claims abstract description 64
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 13
- 239000001257 hydrogen Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 24
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 230000004907 flux Effects 0.000 abstract description 2
- 238000009736 wetting Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 19
- 239000010408 film Substances 0.000 description 13
- 238000007740 vapor deposition Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000007664 blowing Methods 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法および装置に関し、半
田バンプの製造技術に適用して有効な技術に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method and apparatus for manufacturing a semiconductor device, and relates to a technique that is effective when applied to a technique for manufacturing solder bumps.
半導体装置の高密度実装に好適な方式とされている、い
わゆるフリップチップは、アルミニウム（Ａｌ）などか
らなる電極パッド上に形成された半田バンプ（Ｂｕｍｐ
、突起電極）を介して基板などに半導体ペレットをフェ
イスダウンポンディングするものである。The so-called flip chip, which is considered to be a suitable method for high-density packaging of semiconductor devices, uses solder bumps formed on electrode pads made of aluminum (Al) or the like.
In this method, semiconductor pellets are face-down bonded onto a substrate etc. via protruding electrodes).
上記半田バンプを電極パッド上に形成する技術について
は、ＩＢＭ社発行、「１８Ｍジャーナル・オブ・リサー
チ・アンド・ディベロップメント。The technology for forming the solder bumps on the electrode pads is described in "18M Journal of Research and Development," published by IBM.
１３巻、 Ｎａ ３ （ＩＢＭ Ｊｏｕｒｎａｌ ｏｆ
Ｒｅ５ｅａｒｃｈ ａｎｄＤｅｖｅＩｏｐｍｅｎｔ、
Ｖｏｌ、１３． ＮＯ，３） Ｊ Ｐ ２３９〜Ｐ
２５０に記載がある。Volume 13, Na 3 (IBM Journal of
Re5search and DevelopIopment,
Vol, 13. NO, 3) JP 239~P
It is described in 250.
その概要は、半導体ウェハ（以下、ウェハという）のＡ
ｌ電極パッドの表面にクロム（Ｃｒ）／銅（Ｃｕ）／金
（Ａｕ）などの金属層からなる半田下地膜（Ｂ Ｌ Ｍ
； Ｂｕｍｐ Ｌｉｍ１ｔｔ、ｉｎｇ Ｍｅｔａｌｌ
ｕｒｇｙ）を蒸着形成した後、この半田下地膜の表面に
スズ（Ｓｎ）／鉛（Ｐｂ）合金などからなる半田を選択
的に蒸着し、次いで、リフロー炉内でウェットバックを
行って半球状の半田バンプを形成する、というものであ
る。The outline is A of semiconductor wafer (hereinafter referred to as wafer).
A solder base film (B L M
; Bump Limlitt, ing Metal
After forming a solder base film by vapor deposition, solder made of a tin (Sn)/lead (Pb) alloy or the like is selectively vapor-deposited on the surface of this solder base film, and then wet-back is performed in a reflow oven to form a hemispherical shape. This is to form solder bumps.
しかしながら、へβ電極バンド上に半田を選択的に蒸着
する従来の半田バンブ形成法は、半田蒸着膜の堆積に多
くの時間を要するためにスルーブツトが低下してしまう
、という欠点がある。However, the conventional solder bump forming method in which solder is selectively deposited on the beta electrode band has the disadvantage that throughput is reduced because it takes a long time to deposit the solder deposited film.
特に、近年は、へβ電極パッドのピッチの微細化に伴っ
て半田蒸着膜の厚膜化が要求されているため、上記した
半田蒸着膜堆積工程の長時間化に起因するスルーブツト
の低下が一層深刻な問題となっている。In particular, in recent years, as the pitch of β-electrode pads has become finer, thicker solder evaporation films have been required. This has become a serious problem.
また、上記蒸着法の欠点として、メタル又はフォトレジ
ストからなる選択蒸着用のマスクが必要なこと、蒸着装
置が極めて高価であること等のため、これによってフリ
ップチップの製造コストが上昇してしまうことが指摘さ
れている。In addition, disadvantages of the above vapor deposition method include the need for a mask for selective vapor deposition made of metal or photoresist, and the extremely expensive vapor deposition equipment, which increases the manufacturing cost of flip chips. has been pointed out.
従来法の上記した問題点を解消する手段として、例えば
、「昭和６２年電子情報通信学会創立７０周年記念総合
全国大会論文集Ｊ （１９８７年３月、論文番号４６
０）には、ウェハを溶融半田に浸漬して超音波を印加す
ることにより、ＡＩｌ電極バッド上に直接、バンブ用の
半田を被着さ七る技術が記載されている。As a means of solving the above-mentioned problems of the conventional method, for example, "Proceedings of the General National Conference of the Institute of Electronics, Information and Communication Engineers, 1986
No. 0) describes a technique in which solder for bumps is deposited directly onto the Al electrode pad by dipping the wafer in molten solder and applying ultrasonic waves.
しかしながら、この方法は、半田バンブの高さを均一に
制御することが困難であり、しかも、被着する半田量に
限界があるため、得られる半田バンブの高さにも限界が
ある。However, with this method, it is difficult to uniformly control the height of the solder bumps, and since there is a limit to the amount of solder that can be deposited, there is also a limit to the height of the solder bumps that can be obtained.
また、従来知られた他の半田バンブ形成法として、スク
リーン印刷法を用いてＡβ電極パッド上半田ペーストを
被着させる方法やメツキ法によって半田膜を被着させる
方法などがあるが、これらの方法は、半田バンブとへβ
電極パッドとの位百合わせに高い精度が要求される高密
度実装用フリップチップに適用するには、限界がある。In addition, other conventionally known solder bump forming methods include a method of depositing solder paste on the Aβ electrode pad using a screen printing method and a method of depositing a solder film by a plating method. is solder bump and β
There are limits to its application to flip chips for high-density mounting, which require high accuracy in alignment with electrode pads.
本発明は、上記した問題点に着目してなされたものであ
り、その目的は、高密度実装用フリップチップを安価に
提供することができる技術を提供することにある。The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a technology that can provide flip chips for high-density mounting at low cost.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、水素炎トーチを備えた超音波ワイヤボンダを
用いてウェハの電極パッド上に所定量の半田ボールをボ
ンディングした後、この半田ボールをリフロー炉内でウ
ェットバックすることによって、電極パッド上に半田バ
ンブを形成する方法である。That is, after bonding a predetermined amount of solder balls onto the electrode pads of the wafer using an ultrasonic wire bonder equipped with a hydrogen flame torch, the solder balls are wet-backed in a reflow oven to form solder bumps on the electrode pads. This is a method of forming.
また、上記半田バンブを形成する際、水素炎トーチを備
えたワイヤボンダの一部にリフロー炉を設けた装置を使
用するものである。Further, when forming the solder bumps, an apparatus is used in which a reflow oven is provided as a part of a wire bonder equipped with a hydrogen flame torch.
上記した手段によれば、半田蒸着装置よりも安価な装置
を用いてウェハの電極パッド上に所望する量の半田を速
やかに、かつ、精度良くボンディングすることが可能と
なる。According to the above-mentioned means, it becomes possible to quickly and accurately bond a desired amount of solder onto the electrode pad of a wafer using a device that is cheaper than a solder vapor deposition device.
また、ワイヤボンダの一部にリフロー炉を設けることに
より、半田ボールのボンディングとウェットバックとを
同一の装置内で連続的に行うことが可能となる。Further, by providing a reflow oven in a part of the wire bonder, it becomes possible to continuously perform solder ball bonding and wet back in the same device.
第１図（ａ）〜（Ｃ）は本発明の一実施例である半導体
装置の製造方法を工程順に示すウェハの要部断面図、第
２図は本実施例で使用するワイヤボンダの略正面図であ
る。FIGS. 1(a) to (C) are cross-sectional views of main parts of a wafer showing a method for manufacturing a semiconductor device according to an embodiment of the present invention in order of steps, and FIG. 2 is a schematic front view of a wire bonder used in this embodiment. It is.
まず、ウェハプロセスの常法に従ってウェハ１の回路形
成領域に所定の集積回路（図示せず）を形成した後、石
英スパッタ法などによってウェハ１の表面にガラス保護
膜２を被着し、次いで、フォトレジスト／エツチングに
より所定個所を孔開けして酸化膜３の表面にパターン形
成されたＡｌ配線の一部を露出させてＡｌ電極パッド４
を形成する。First, a predetermined integrated circuit (not shown) is formed in a circuit forming area of a wafer 1 according to a conventional wafer process method, and then a glass protective film 2 is deposited on the surface of the wafer 1 by quartz sputtering or the like. A hole is formed at a predetermined location using photoresist/etching to expose a part of the Al wiring patterned on the surface of the oxide film 3, and an Al electrode pad 4 is formed.
form.
次に、クロム（Ｃｒ）、銅（Ｃｕ）および金（Ａｕ）の
薄膜を順次蒸着してＡｌ電極パッド４の表面に半田下地
膜５を形成する（第１図（ａ））。Next, thin films of chromium (Cr), copper (Cu), and gold (Au) are sequentially deposited to form a solder base film 5 on the surface of the Al electrode pad 4 (FIG. 1(a)).
ここで、上記半田下地膜５の最上層として適した金属は
、上記金（Ａｕ）の他、鉛（Ｐｂ）、スズ（Ｓｎ）、ニ
ッケル（Ｎｉ）、銀（Ａｇ）などである。Here, metals suitable for the uppermost layer of the solder base film 5 include lead (Pb), tin (Sn), nickel (Ni), silver (Ag), etc. in addition to the gold (Au) described above.
次に、ブロービング・テストによって各Ａｆｌ電極パッ
ド４の電気特性を検査した後、不良のないウェハ１を第
２図に示すワイヤボンダ６のローダ７に一枚ずつ収容す
る。Next, after inspecting the electrical characteristics of each Afl electrode pad 4 by a blowing test, the wafers 1 without defects are loaded one by one into the loader 7 of the wire bonder 6 shown in FIG.
このワイヤボンダ６のＸＹテーブル８の上にはボンディ
ングヘッド９が載置され、上下動ブロック１０の内部に
ボンディングアーム１１およびクランプ１２が揺動可能
に取り付けられている。A bonding head 9 is placed on the XY table 8 of the wire bonder 6, and a bonding arm 11 and a clamp 12 are swingably attached inside a vertically movable block 10.
基端部に超音波発振子１３が取り付けられたボンディン
グアーム１１の先端にはキャピラリ１４が固定され、ス
ズ（Ｓｎ）と鉛（ｐｂ）との合金からなる半田ワイヤ１
５がキャピラリ１４−とスプルー１６との間に張設され
ている。A capillary 14 is fixed to the tip of the bonding arm 11, which has an ultrasonic oscillator 13 attached to the base end, and a solder wire 1 made of an alloy of tin (Sn) and lead (PB).
5 is stretched between the capillary 14- and the sprue 16.
キャピラリ１４の近傍には水素炎トーチ１７が配設され
、半田ワイヤ１５の先端を水素炎で加熱溶融することに
よって、半田ボール１８を形成するようになっている。A hydrogen flame torch 17 is disposed near the capillary 14, and a solder ball 18 is formed by heating and melting the tip of the solder wire 15 with the hydrogen flame.
クランプ１２の上方にはＴＶカメラ１９が設置され、制
御部２０からの信号によって作動されるボンディングア
ーム１１の作動状態が外部のモニタＴＶ２１で監視でき
るようになっている。A TV camera 19 is installed above the clamp 12 so that the operating state of the bonding arm 11, which is activated by a signal from the control unit 20, can be monitored on an external monitor TV 21.
そこで、ローダ７から搬出したウェハ１をホルダ２２の
上に位置決めすると、制御部２０からの信号によってボ
ンディングアーム１１の作動が開始され、キャピラリ１
４の下端で形成された半田ボール１８がＡＡ電極パッド
４の上にボンディングされる（第１図（ｂ））。Therefore, when the wafer 1 carried out from the loader 7 is positioned on the holder 22, the operation of the bonding arm 11 is started by a signal from the control unit 20, and the capillary 1
A solder ball 18 formed at the lower end of the AA electrode pad 4 is bonded onto the AA electrode pad 4 (FIG. 1(b)).
次に、ウェハ１の表面にフラックスを被着した後、これ
をボンディングヘッド９に隣接して設置されたりフロー
炉２３に搬入し、非酸化性雰囲気または還元性雰囲気で
ウェットバックを行うと、半田ボール１８が溶融してＡ
Ｉ！電極パッド４の上に半球状の半田バンブ２４が形成
される（第１図（Ｃ））。Next, after applying flux to the surface of the wafer 1, it is installed adjacent to the bonding head 9 or transported into the flow furnace 23, and wet-backed in a non-oxidizing atmosphere or a reducing atmosphere. Ball 18 melts and A
I! A hemispherical solder bump 24 is formed on the electrode pad 4 (FIG. 1(C)).
半田バンブ２４が形成されたウェハｌは、アンローダ２
５に一枚ずつ収容され、さらに、次工程に搬送される。The wafer l on which the solder bumps 24 are formed is transferred to the unloader 2
5, one by one, and then transported to the next process.
このように、本実施例によれば、下記の効果を得ること
ができる。As described above, according to this embodiment, the following effects can be obtained.
（工〕、水素炎トーチ１７を備えた超音波ワイヤボンダ
６を用いてＡｌ電極バッド４の上に半田ボール１８をボ
ンディングした後、この半田ボール１８をリフロー炉２
３でウェットバックして半田バンブ２４を形成するので
、所望する体積の半田バンブ２４を短時間で形成するこ
とができ、スループットが大幅に向上する。After bonding a solder ball 18 onto the Al electrode pad 4 using an ultrasonic wire bonder 6 equipped with a hydrogen flame torch 17, the solder ball 18 was transferred to a reflow oven.
Since the solder bumps 24 are formed by wet-backing in Step 3, the solder bumps 24 having a desired volume can be formed in a short time, and the throughput is greatly improved.
〔２）、高価な半田蒸着装置を必要としないので、半田
バンブ２４の製造コストを低減することができる。[2) Since an expensive solder vapor deposition device is not required, the manufacturing cost of the solder bump 24 can be reduced.
（３）、水素炎トーチ１７を備えたワイヤボンダ６を用
いてＡｌ電極バッド４の上に半田ボール１８をボンディ
ングするので、Ａ１電極パッド４のピッチが微細なウェ
ハにも適用することができる。(3) Since the solder balls 18 are bonded onto the Al electrode pads 4 using the wire bonder 6 equipped with the hydrogen flame torch 17, the method can be applied to wafers with fine pitches of the A1 electrode pads 4.
（４）、半田ボール１８を形成するに際し、放電トーチ
を備えたワイヤボンダを用いた場合には、蒸発した鉛（
Ｐｂ）やスズ（Ｓｎ）がトーチの電極に付着、堆積して
電極間にスパークが発生しなくなる虞れがあるが、水素
炎トーチ１７を用いることによって上記のような不具合
が解消され、半田ボール１８を連続的に形成することが
できる。(4) When forming the solder balls 18 using a wire bonder equipped with a discharge torch, evaporated lead (
There is a risk that sparks may not be generated between the electrodes due to Pb) and tin (Sn) adhering to or depositing on the torch electrodes, but by using the hydrogen flame torch 17, the above problems are resolved and the solder balls are removed. 18 can be formed continuously.
（５）、上記（１）〜（４）により、高密度実装用フリ
ップチップを安価に提供することができる。(5) According to (1) to (4) above, a flip chip for high-density mounting can be provided at low cost.
（６）、ブロービング・テストによってウェハ１の電気
特性を検査した後、Ａｌ電極バッド４の上に半田ボール
１８をボンディングするので、不良のないウェハ１にの
み半田バンブ２４を形成することができ、歩留りが向上
する。(6) Since the solder balls 18 are bonded onto the Al electrode pads 4 after inspecting the electrical characteristics of the wafer 1 by a blowing test, the solder bumps 24 can be formed only on the wafers 1 without defects. , yield is improved.
（７）、ワイヤボンダ６の一部にリフロー炉２３を設置
した装置を使用するので、半田ボール１８のボンディン
グとウェットバックとを同一の装置内で連続的に行うこ
とができ、半田バンブ２４を形成する工程のスルーブツ
トが一層向上する。(7) Since a device in which a reflow oven 23 is installed in a part of the wire bonder 6 is used, bonding and wet backing of the solder balls 18 can be performed continuously in the same device, and the solder bumps 24 are formed. The throughput of the process is further improved.
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.
本願にふいて開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記の通りである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
すなわち、水素炎トーチを備えたワイヤボンダを用いて
ウェハの電極パッド上に所定量の半田ボー −ルをボン
ディングした後、上記半田ボールをリフロー炉内でウェ
ットバックすることによって、高密度実装用フリップチ
ップを安価に製造することができる。That is, after bonding a predetermined amount of solder balls onto the electrode pads of a wafer using a wire bonder equipped with a hydrogen flame torch, the solder balls are wet-backed in a reflow oven to form flip chips for high-density mounting. can be manufactured at low cost.
また、ワイヤボンダの一部にリフロー炉を設置した装置
を使用することにより、半田バンブ形成工程のスルーブ
ツトを一層向上させることができる。Furthermore, by using an apparatus in which a reflow oven is installed in a part of the wire bonder, the throughput of the solder bump forming process can be further improved.
第１図（ａ）〜（Ｃ）は本発明の一実施例である半導体
装置の製造方法を工程順に示す半導体ウェハの要部断面
図、
第２図は本実施例で使用するワイヤボンダの略正面図で
ある。
１・・・半導体ウェハ、２・・ガラス保護膜、３・・・
酸化膜、４・・・Ａ！電極パッド、５・・・半田下地膜
、６・・・ワイヤボンダ、７・・・ローダ、８・・・Ｘ
Ｙテーブル、９・・・ボンディングヘッド、１０・・・
上下動ブロック、１１・・・ボンディングアーム、１２
・・・クランプ、１３・・・超音波振動子、１４・・・
キャピラリ、１５・・・半田ワイヤ、１６・・・スプル
ー、１７・・・水素炎トーチ、１８・・・半田ボール、
１９・・・ＴＶ左カメラ２０・・・制御部、２１・・・
モニタＴＶ、２２・・・ホルタ、２３・・・リフロー炉
、２４・・・半田バンブ、２５・・・アンローダ。
第２図FIGS. 1(a) to (C) are cross-sectional views of main parts of a semiconductor wafer showing a method for manufacturing a semiconductor device according to an embodiment of the present invention in order of steps; FIG. 2 is a schematic front view of a wire bonder used in this embodiment. It is a diagram. 1... Semiconductor wafer, 2... Glass protective film, 3...
Oxide film, 4...A! Electrode pad, 5...Solder base film, 6...Wire bonder, 7...Loader, 8...X
Y table, 9... bonding head, 10...
Vertical movement block, 11... Bonding arm, 12
...Clamp, 13...Ultrasonic vibrator, 14...
Capillary, 15...Solder wire, 16...Sprue, 17...Hydrogen flame torch, 18...Solder ball,
19...TV left camera 20...control unit, 21...
Monitor TV, 22... Holter, 23... Reflow oven, 24... Solder bump, 25... Unloader. Figure 2
Claims (1)
るに際し、水素炎トーチを備えた超音波ワイヤボンダを
用いて前記電極パッド上に所定量の半田ボールをボンデ
ィングした後、前記半田ワイヤをリフロー炉内でウェッ
トバックすることを特徴とする半導体装置の製造方法。 ２、水素炎トーチを備えたワイヤボンダの一部にリフロ
ー炉を設けたことを特徴とする半導体装置の製造装置。[Claims] 1. When forming solder bumps on electrode pads of a semiconductor wafer, after bonding a predetermined amount of solder balls onto the electrode pads using an ultrasonic wire bonder equipped with a hydrogen flame torch, A method for manufacturing a semiconductor device, comprising wet-backing solder wire in a reflow oven. 2. A semiconductor device manufacturing apparatus characterized in that a reflow oven is provided in a part of a wire bonder equipped with a hydrogen flame torch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63042073A JPH01217935A (en) | 1988-02-26 | 1988-02-26 | Manufacture of semiconductor device and apparatus thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63042073A JPH01217935A (en) | 1988-02-26 | 1988-02-26 | Manufacture of semiconductor device and apparatus thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01217935A true JPH01217935A (en) | 1989-08-31 |
Family
ID=12625890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63042073A Pending JPH01217935A (en) | 1988-02-26 | 1988-02-26 | Manufacture of semiconductor device and apparatus thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01217935A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5478007A (en) * | 1993-04-14 | 1995-12-26 | Amkor Electronics, Inc. | Method for interconnection of integrated circuit chip and substrate |
| US5514604A (en) * | 1993-12-08 | 1996-05-07 | General Electric Company | Vertical channel silicon carbide metal-oxide-semiconductor field effect transistor with self-aligned gate for microwave and power applications, and method of making |
| EP0697721A3 (en) * | 1994-08-10 | 1996-07-10 | Ibm | Selective addition of a solder ball to an array of solder balls |
| JPH0974098A (en) * | 1995-09-04 | 1997-03-18 | Anam Ind Co Inc | Bonding method for semiconductor chip |
| US5795818A (en) * | 1996-12-06 | 1998-08-18 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection and method |
| JP2005026715A (en) * | 1996-08-27 | 2005-01-27 | Nippon Steel Corp | Semiconductor device with low melting point metal bump and method for flip-chip bonding |
| US7288472B2 (en) * | 2004-12-21 | 2007-10-30 | Intel Corporation | Method and system for performing die attach using a flame |
| JP2008108798A (en) * | 2006-10-24 | 2008-05-08 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method therefor |
-
1988
- 1988-02-26 JP JP63042073A patent/JPH01217935A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5478007A (en) * | 1993-04-14 | 1995-12-26 | Amkor Electronics, Inc. | Method for interconnection of integrated circuit chip and substrate |
| US5514604A (en) * | 1993-12-08 | 1996-05-07 | General Electric Company | Vertical channel silicon carbide metal-oxide-semiconductor field effect transistor with self-aligned gate for microwave and power applications, and method of making |
| EP0697721A3 (en) * | 1994-08-10 | 1996-07-10 | Ibm | Selective addition of a solder ball to an array of solder balls |
| JPH0974098A (en) * | 1995-09-04 | 1997-03-18 | Anam Ind Co Inc | Bonding method for semiconductor chip |
| JP2005026715A (en) * | 1996-08-27 | 2005-01-27 | Nippon Steel Corp | Semiconductor device with low melting point metal bump and method for flip-chip bonding |
| US5795818A (en) * | 1996-12-06 | 1998-08-18 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection and method |
| US6163463A (en) * | 1996-12-06 | 2000-12-19 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection |
| US7288472B2 (en) * | 2004-12-21 | 2007-10-30 | Intel Corporation | Method and system for performing die attach using a flame |
| JP2008108798A (en) * | 2006-10-24 | 2008-05-08 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method therefor |
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