JPH01207932A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01207932A JPH01207932A JP3346588A JP3346588A JPH01207932A JP H01207932 A JPH01207932 A JP H01207932A JP 3346588 A JP3346588 A JP 3346588A JP 3346588 A JP3346588 A JP 3346588A JP H01207932 A JPH01207932 A JP H01207932A
- Authority
- JP
- Japan
- Prior art keywords
- film
- films
- laminated
- thickness
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 230000001681 protective effect Effects 0.000 claims abstract description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000011521 glass Substances 0.000 claims abstract description 6
- 238000010030 laminating Methods 0.000 claims abstract description 6
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 abstract description 9
- 239000012535 impurity Substances 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 6
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 5
- 239000011574 phosphorus Substances 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 238000006243 chemical reaction Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000000052 comparative effect Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 238000002161 passivation Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910005091 Si3N Inorganic materials 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000011253 protective coating Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野〕゛
本発明は、半導体基板に接してパッシベーション膜を有
し、さらに基板上に設けられる配線を覆って同様なパッ
シベーション機能をもつ最終保護膜を有する半導体装置
に関する。Detailed Description of the Invention (Industrial Application Field) The present invention has a passivation film in contact with a semiconductor substrate, and a final protective film having a similar passivation function covering wiring provided on the substrate. The present invention relates to a semiconductor device having the present invention.
半導体装置の特性の安定化のために、不安定性の要因の
侵入を阻止し、また半導体基板に内在しているもしくは
内部で発生した不安定性の要因を除去し、不活性化する
ためにパッシベーションが行われる。雰囲気に接する最
終保護膜は特に外気の影響の阻止のほかルこ亀裂の発生
のない耐タラツク性が要求される。In order to stabilize the characteristics of semiconductor devices, passivation is used to prevent the entry of instability factors, and to remove and inactivate instability factors that are inherent in or have occurred within the semiconductor substrate. It will be done. The final protective film that comes into contact with the atmosphere is particularly required to block the influence of outside air and also to be resistant to scratches without causing cracks.
従来、半導体装置の最終保護膜としてりんガラス（ＰＳ
Ｇ）、酸化珪素（Ｓｉｆｔ） 、窒化珪素（ＳｉＪ４）
＋酸窒化珪素（ＳｉＯＮ）などが使われてきている。こ
のうち、ＰＳＧ膜は、りんによる不純物のゲッタリング
効果と耐クランクの点で優れてはいるが、りんを含んで
いるため耐水性の低下による配線金属のＭの腐食等を引
き起こす可能性があるため、きびしい条件下では使用で
きない。Conventionally, phosphor glass (PS) has been used as the final protective film for semiconductor devices.
G), silicon oxide (Sift), silicon nitride (SiJ4)
+Silicon oxynitride (SiON), etc. are being used. Among these, the PSG film is excellent in terms of impurity gettering effect due to phosphorus and crank resistance, but since it contains phosphorus, it may cause corrosion of the M of the wiring metal due to a decrease in water resistance. Therefore, it cannot be used under harsh conditions.
５ｉＪ４は、不純物や水分の阻止効果がきわめて大きい
かわり、膜の応力が大きいため耐クランク性に問題があ
る。また、Ｓｉ３Ｎ４を最終保護膜として用いる場合の
製法は原料ガスにＳｉ■ｔ、’ＮＨｓ等を用いてのプラ
ズマＣＶＤ法によるため、膜中に多量のＮ−Ｈ；’５ｉ
＝Ｈ基が混入、している。この膜中の多量の水素により
％１０．５ＦＥＴのしきい値電圧を変動させる等の問題
・を、発パ生させている。また、Ｓｉ３Ｎ、膜の応力を
緩和させるために、５ｉ０２とＳｉ３Ｎ４を混合した膜
として５ｉＯＮ膜が用いられているが、５ｉＯＮ膜は膜
質の再現性等の問題がある。Although 5iJ4 has a very high effect of blocking impurities and moisture, it has a problem in crank resistance because the stress of the film is large. In addition, since the manufacturing method when using Si3N4 as the final protective film is a plasma CVD method using Si*t, 'NHs, etc. as the raw material gas, a large amount of N-H; '5i
=H group is mixed. A large amount of hydrogen in this film causes problems such as fluctuations in the threshold voltage of the %10.5 FET. Further, in order to relieve the stress of the Si3N film, a 5iON film is used as a mixed film of 5i02 and Si3N4, but the 5iON film has problems such as reproducibility of film quality.
その他、適度な耐水性、耐クラツク性を持つ膜としてＳ
ｔＯ，膜も用いられる場合がある。しかし最近の傾向と
しては、以上述べた各種膜を単体では使わず、第２図に
示すようにＭ配線２を設けたシリコン基板１上にＰＳＧ
Ｓ複膜ＳｉＯ□膜３ではさんだ構造にし、直接ＭがＰＳ
Ｇ膜と接触することを防ぐ方法、または５ｉＯ１膜とＳ
ｉ ｓＮａ膜あるいはＰＳＧ膜とＳｉＪ＊膜の２層構造
とし、５ｌｓＮａ膜の高い不純物や水分の阻止効果と、
５ｉ０２やＰＳＧを積層することによる低応力化とを組
み合わせた方法等がある。In addition, S is used as a film with appropriate water resistance and crack resistance.
tO, membranes may also be used. However, as a recent trend, the various films mentioned above are not used alone, but PSG
The structure is sandwiched between S double film SiO□ film 3, and M is directly connected to PS.
How to prevent contact with G film or 5iO1 film and S
It has a two-layer structure of i sNa film or PSG film and SiJ* film, and has the high impurity and moisture blocking effect of 5lsNa film,
There is a method that combines stress reduction by laminating 5i02 or PSG.
しかしながら、最近の半導体素子の微細化に伴い、保護
膜の水素の影響を受けやすくなりＭＯＳＦＥＴのしきい
値電圧の変動が起こりやすくなったり、Ｍ配線の細線化
により保護膜の応力によるＭ配線の変形や断線が非常に
起きやすくなっている。However, with the recent miniaturization of semiconductor devices, they are more susceptible to the effects of hydrogen in the protective film, causing fluctuations in the threshold voltage of MOSFETs. Deformation and disconnection are extremely likely to occur.
このため、不純物や水分の高い阻止効果、膜の低応力化
等が非常に強く望まれている。For this reason, there is a strong desire to have a high impurity and moisture blocking effect and to reduce the stress of the film.
本発明の課題は、外部からの不純物や水分の阻止性が向
上しかつ膜内応力の低下した最終保護膜を有する半導体
装置を提供するものとする。An object of the present invention is to provide a semiconductor device having a final protective film that has improved blocking properties against external impurities and moisture and reduced internal stress.
上記の課題を解決するために、本発明の半導体装置は、
窒化珪素膜、酸化珪素膜およびりんガラス膜のうちの少
なくとも２種からなる積層膜の複数をさらに積層してな
る最終保護膜を有するものとする。In order to solve the above problems, the semiconductor device of the present invention includes:
The final protective film is formed by further laminating a plurality of laminated films made of at least two of a silicon nitride film, a silicon oxide film, and a phosphorous glass film.
従来用いられていた２種の膜の積層では不十分であった
不純物や水分の阻止効果あるいは応力の低減が積層膜を
さらに複数積層することにより向上し、所要の膜性能を
得るに至る。The effect of blocking impurities and moisture or the reduction of stress, which was insufficient with the lamination of two types of films conventionally used, is improved by laminating a plurality of laminated films, and the desired film performance can be obtained.
以下、第２図を含めて共通の部分には同一の符号を付し
た図を引用して本発明の実施例のいくつかについて述べ
る。Hereinafter, some embodiments of the present invention will be described with reference to drawings including FIG. 2 in which common parts are given the same reference numerals.
第１図に示した実施例は、配線２を設けたシリコン基板
１の上ニ２ｏｏｏ人の厚さ（７） ５ｉＯｉ ＋！：
１０００人の厚さのＳｉ３Ｎ、からなる２層絶縁膜を３
層分積層し、全体で約ＩＩｎＡ弱の厚さにしたものであ
る。この酸化膜３と窒化膜５は、プラズマＣＶＤ法で窒
化膜を、プラズマＣＶＤ法または減圧ＣＶＤ法で酸化膜
を同一反応槽で連続成膜したものである。この実施例の
最終保護膜を第３図に示したように、６０００人の厚さ
ノ５ｉＯｚ膜３と３０００人の厚さの５ｉｓＮａ膜を積
層し、全体の犀さは第１図に示した場合と等しくした最
終保護膜と比較すると、シリコン板１のそりから測った
圧縮応力は第１図の実施例では１． ＯＸ １０Ｉ０ｄ
ｙｎ／ ａｊ、第３図の比較例では１．５×’１Ｑｌｏ
ｄｙｎ／−であった。また２気圧、１２５℃の水蒸気
中での圧力がま試験の結果では、第１図の実施例で１３
００時間で、第３図の比較例では１０００時間〜である
から耐水性の向上したことが実証された。In the embodiment shown in FIG. 1, the thickness of the silicon substrate 1 on which the wiring 2 is provided is 2ooo people (7) 5iOi +! :
A two-layer insulating film made of Si3N with a thickness of 1000 nm is
The layers are laminated to have a total thickness of a little less than IInA. The oxide film 3 and the nitride film 5 are obtained by successively forming a nitride film using a plasma CVD method and an oxide film using a plasma CVD method or a low pressure CVD method in the same reaction tank. As shown in Fig. 3, the final protective film of this example was a 6,000-layer thick 5iOz film 3 and a 3,000-layer-thick 5isNa film, and the overall thickness was as shown in Fig. 1. When compared with the final protective film made equal to the case, the compressive stress measured from the warpage of the silicon plate 1 is 1. OX10I0d
yn/aj, 1.5×'1Qlo in the comparative example in Figure 3
It was dyn/-. In addition, the results of a pressure cooker test in water vapor at 2 atm and 125°C showed that the example shown in Figure 1 was 13
00 hours, and in the comparative example shown in FIG. 3, it was 1000 hours, demonstrating that the water resistance was improved.
第４図は別の実施例を示し、最終保護膜は２０００人の
厚さのＰＳＧＳ複膜上に３層の１０００人の厚さの５ｉ
Ｊａ膜５を２０００人の厚さの５ｉＯ１膜３を介して積
層したもので、全体の厚さは約１μ弱である。ＰＳＧＳ
複膜りん濃度は２〜４％で、プラズマＣＶＤ法または減
圧ＣＶＤ法で形成でき、第１図の実施例の場合と同様に
この最終保護膜も同一反応槽で連続成膜したものである
。第５図はこの実施例に対する比較例で、基板１の上に
６０００人の厚さのＰＳＧＳ複膜３０００人の５ｉｓＮ
ａ膜５を積層したものである。FIG. 4 shows another example in which the final protective coating is 3 layers of 1000 mm thick 5i on a 2000 mm thick PSGS composite membrane.
A Ja film 5 is laminated with a 5iO1 film 3 having a thickness of 2,000 layers interposed therebetween, and the total thickness is approximately a little less than 1 μm. P.S.G.S.
The double film has a phosphorus concentration of 2 to 4% and can be formed by plasma CVD or low pressure CVD, and the final protective film was also formed continuously in the same reaction tank as in the embodiment shown in FIG. FIG. 5 is a comparative example for this example, in which a PSGS composite film with a thickness of 3000 μm and 5isN of 3000 μm is deposited on the substrate 1.
A-film 5 is laminated.
圧縮応力は第４図の実施例で９．５ Ｘ １０”ｄｙｎ
／ ｃｊ、第５図の比較例では７ Ｘ １０’ｄｙｎ
／−でＰＳＧ膜の厚い比較例の方が応力吸収効果が大き
いが、第４図の実施例でも第１図の実施例におけるより
低下している。また圧力がま試験では、第４図の実施例
で１１００時間、第５図の比較例で７００時間のデータ
が得られた。従って水分の阻止効果は第１図の実施例の
方が第４図の実施例より高い。The compressive stress is 9.5 x 10” dyn in the example shown in Figure 4.
/ cj, 7 x 10'dyn in the comparative example in Figure 5
The stress absorption effect is greater in the comparative example in which the PSG film is thicker than that in the example shown in FIG. 4, but it is lower than that in the example shown in FIG. In the pressure cooker test, data of 1100 hours was obtained for the example shown in FIG. 4 and 700 hours for the comparative example shown in FIG. Therefore, the moisture blocking effect is higher in the embodiment shown in FIG. 1 than in the embodiment shown in FIG.
本発明によれば、最終保護膜を窒化珪素膜、酸化珪素膜
およびりんガラス膜のうちの少なくとも２種の絶縁膜か
らなる積層膜をさらに複数積層して形成することにより
、不純物や水分の阻止性能の向上、膜内応力の低減が実
現でき、信鰭性の向上した半導体装置を得ることができ
た。According to the present invention, the final protective film is formed by laminating a plurality of laminated films each consisting of at least two types of insulating films selected from silicon nitride, silicon oxide, and phosphorous glass, thereby blocking impurities and moisture. It was possible to improve performance and reduce stress in the film, and to obtain a semiconductor device with improved reliability.
第１図は本発明の一実施例の半導体装置の断面図、第２
図は従来の最終保護膜の一例を備えた半導体装置の断面
図、第３図は第１図との比較例の断面図、第４図は本発
明の別の実施例の断面図、第５図は第４図との比較例の
断面図である。
１：シリコン基板、２：配線、３：酸化珪素膜、（Ｙ）
（Ｙ） ｕつ
１ｒ’ｌｌ”Ｉ”ｌ □FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIG.
3 is a sectional view of a semiconductor device equipped with an example of a conventional final protective film, FIG. 3 is a sectional view of a comparative example with FIG. 1, FIG. 4 is a sectional view of another embodiment of the present invention, and FIG. The figure is a sectional view of a comparative example with FIG. 4. 1: Silicon substrate, 2: Wiring, 3: Silicon oxide film, (Y)
(Y) utsu1r'll"I"l □
Claims (1)
ちの少なくとも２種の絶縁膜からなる積層膜の複数をさ
らに積層してなる最終保護膜を有することを特徴とする
半導体装置。(1) A semiconductor device characterized by having a final protective film formed by further laminating a plurality of laminated films each made of at least two kinds of insulating films selected from a silicon nitride film, a silicon oxide film, and a phosphorous glass film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3346588A JPH01207932A (en) | 1988-02-16 | 1988-02-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3346588A JPH01207932A (en) | 1988-02-16 | 1988-02-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01207932A true JPH01207932A (en) | 1989-08-21 |
Family
ID=12387295
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3346588A Pending JPH01207932A (en) | 1988-02-16 | 1988-02-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01207932A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0689893A (en) * | 1991-11-11 | 1994-03-29 | Nec Corp | Semiconductor device |
| US5536672A (en) * | 1987-10-08 | 1996-07-16 | National Semiconductor Corporation | Fabrication of ferroelectric capacitor and memory cell |
| WO1997002594A1 (en) * | 1995-07-03 | 1997-01-23 | Intel Corporation | Low damage source and drain doping technique |
| US5780364A (en) * | 1994-12-12 | 1998-07-14 | Micron Technology, Inc. | Method to cure mobile ion contamination in semiconductor processing |
| CN1053994C (en) * | 1993-04-14 | 2000-06-28 | 松下电器产业株式会社 | Semiconductor device and method of fabricating the same |
| US6664612B2 (en) | 1998-07-09 | 2003-12-16 | Infineon Technologies Ag | Semiconductor component having double passivating layers formed of two passivating layers of different dielectric materials |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4866777A (en) * | 1971-12-15 | 1973-09-12 | ||
| JPS5555538A (en) * | 1978-10-20 | 1980-04-23 | Hitachi Ltd | Semiconductor device |
| JPS60233829A (en) * | 1984-01-19 | 1985-11-20 | Nec Corp | Formation of insulation layer |
| JPS6150375A (en) * | 1984-08-20 | 1986-03-12 | Sanyo Electric Co Ltd | Semiconductor device |
-
1988
- 1988-02-16 JP JP3346588A patent/JPH01207932A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4866777A (en) * | 1971-12-15 | 1973-09-12 | ||
| JPS5555538A (en) * | 1978-10-20 | 1980-04-23 | Hitachi Ltd | Semiconductor device |
| JPS60233829A (en) * | 1984-01-19 | 1985-11-20 | Nec Corp | Formation of insulation layer |
| JPS6150375A (en) * | 1984-08-20 | 1986-03-12 | Sanyo Electric Co Ltd | Semiconductor device |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5536672A (en) * | 1987-10-08 | 1996-07-16 | National Semiconductor Corporation | Fabrication of ferroelectric capacitor and memory cell |
| JPH0689893A (en) * | 1991-11-11 | 1994-03-29 | Nec Corp | Semiconductor device |
| CN1053994C (en) * | 1993-04-14 | 2000-06-28 | 松下电器产业株式会社 | Semiconductor device and method of fabricating the same |
| US5780364A (en) * | 1994-12-12 | 1998-07-14 | Micron Technology, Inc. | Method to cure mobile ion contamination in semiconductor processing |
| US5943602A (en) * | 1994-12-12 | 1999-08-24 | Micron Technology, Inc. | Method to cure mobile ion contamination in semiconductor processing |
| US6114222A (en) * | 1994-12-12 | 2000-09-05 | Micron Technology, Inc. | Method to cure mobile ion contamination in semiconductor processing |
| WO1997002594A1 (en) * | 1995-07-03 | 1997-01-23 | Intel Corporation | Low damage source and drain doping technique |
| US5976939A (en) * | 1995-07-03 | 1999-11-02 | Intel Corporation | Low damage doping technique for self-aligned source and drain regions |
| US6664612B2 (en) | 1998-07-09 | 2003-12-16 | Infineon Technologies Ag | Semiconductor component having double passivating layers formed of two passivating layers of different dielectric materials |
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