JPH01194335A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01194335A JPH01194335A JP1721388A JP1721388A JPH01194335A JP H01194335 A JPH01194335 A JP H01194335A JP 1721388 A JP1721388 A JP 1721388A JP 1721388 A JP1721388 A JP 1721388A JP H01194335 A JPH01194335 A JP H01194335A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- polycrystalline
- wiring
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 33
- 238000009792 diffusion process Methods 0.000 claims abstract description 20
- 239000012535 impurity Substances 0.000 claims abstract description 18
- 230000004888 barrier function Effects 0.000 claims abstract description 6
- 239000002210 silicon-based material Substances 0.000 claims description 26
- MTPVUVINMAGMJL-UHFFFAOYSA-N trimethyl(1,1,2,2,2-pentafluoroethyl)silane Chemical compound C[Si](C)(C)C(F)(F)C(F)(F)F MTPVUVINMAGMJL-UHFFFAOYSA-N 0.000 abstract description 14
- 239000000758 substrate Substances 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 11
- 239000000463 material Substances 0.000 abstract description 7
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 abstract description 2
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 abstract 2
- 229910019213 POCl3 Inorganic materials 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229920001076 Cutan Polymers 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000007447 staining method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Non-Volatile Memory (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は半導体装置に係り、特に多結晶シリコン材料を
半導体素子の配線に用いた半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device, and particularly to a semiconductor device using polycrystalline silicon material for wiring of semiconductor elements.
（従来の技南ン
ＭＯＳ （絶縁ｆｆ−）ｆｆｉ、）素子やバイポーラ素
子などの半導体素子の配線として多結晶シリコン材料が
用いられることが多く、これによって各種のセル７アラ
イン構造が可能となり、素子の烏集積化、゛高密度化の
実現に大きく寄与している。たとえば第４図に示すよう
な従来のＭＯＳ）ランジスタにおいて、ダート電極配＃
！４３として多結晶シリコン材料が用いられている。こ
こで、４０はシリコン基板、４ノはフィールド酸化膜、
４２はシリコン酸化膜（ダート絶縁膜）、４４はソース
拡散層領域、４５はドレイン拡散層領域、４６は絶縁膜
、４７はアルミニウム・シリコン配線である。Polycrystalline silicon materials are often used as wiring for semiconductor devices such as (conventional MOS (insulated ff-)ffi) devices and bipolar devices, which enables various cell 7-aligned structures and It has greatly contributed to the realization of high integration and high density. For example, in a conventional MOS transistor as shown in FIG.
! A polycrystalline silicon material is used as the material 43. Here, 40 is a silicon substrate, 4 is a field oxide film,
42 is a silicon oxide film (dirt insulating film), 44 is a source diffusion layer region, 45 is a drain diffusion layer region, 46 is an insulating film, and 47 is an aluminum/silicon wiring.
ところで、素子の微細化によシグートＭ！３縁膜４２が
薄膜化されるので、ダート電極配線用の多結晶シリコン
膜の堆積後のグロセスで熱工程を経過すると、多結晶シ
リコン材料にドーグされている不純物（たとえばｐ 、
Ａｓ 、 Ｂなど）が前記ｙ−トｉ縁膜４２に拡散し
てシリコン酸化ｍ負を劣化させてしまい、トランジスタ
特性や信頼性の低下とか不良の発生をまねいてしまうと
いう問題がある。By the way, due to the miniaturization of elements, Sigut M! 3. Since the edge film 42 is thinned, impurities doped in the polycrystalline silicon material (for example, p,
There is a problem in that the silicon oxide (As, B, etc.) diffuses into the y-to-i edge film 42 and deteriorates the silicon oxide, leading to deterioration in transistor characteristics and reliability and the occurrence of defects.
（発明が解決しようとする課題）
本発明は、上記したように電極配線用の多結晶シリコン
材料中の不純物が外部に拡散して千尋体系子の信頼性の
低下をまねくという間亀点を解決すべくなされたもので
、上記多結晶シリコン材料から下層あるいｒｒｉ周囲へ
の不純物の拡散を防止し得る半導体装置を提供すること
を目的とする。(Problems to be Solved by the Invention) As described above, the present invention solves the problem that impurities in the polycrystalline silicon material for electrode wiring diffuse to the outside and cause a decrease in the reliability of the Chihiro system. It is an object of the present invention to provide a semiconductor device that can prevent impurities from diffusing from the polycrystalline silicon material to the lower layer or around the rri.
［発明の構成コ
（課題を解決するための手段）
本発明の半尋体装ｒｉｔは、半導体素子の配線用の多結
晶シリコン材料と下層の絶縁膜あるいは周囲の絶縁膜と
の間に、上記多結晶シリコン材料に含まれる不純物の拡
散を防止する障壁用尋を腺を設けてなることｆｔ特徴と
する。[Structure of the Invention (Means for Solving the Problems)] The half-layer RIT of the present invention has the above-mentioned structure between the polycrystalline silicon material for wiring of a semiconductor element and the underlying insulating film or the surrounding insulating film. It is characterized by providing a barrier gland for preventing the diffusion of impurities contained in the polycrystalline silicon material.
（作用）
上記多結晶シリコン材料の下部あるいは周囲が不純物拡
散の陣壁となる膜で覆われているので、半導体素子製造
プロセスの熱工程を経ても上記多結晶シリコン材料中に
含まれている不純物が下層あるいは周囲に拡散すること
がなく、半導体素子の・特性や信頼性の低下を防ぐこと
が可能になる・（実施例）
以下、図面を多照して本発明の一実施例を詳細に説明す
る◎
第１図（、）乃至（ｄ）はＭＯ８型ＬＳＩにおけるＭＱ
Ｓ ）ランジスタの製造工程を示している。即ち、先ず
第１図（ａ）に示すように、半導体基板（たとえばＰ型
シリコン基板）Ｊ上に熱酸化法を用いて遇択的にフィー
ルド酸化膜２を形成する。次に、ダート絶縁膜となるシ
リコン酸化ｔｓ３ｔ−熱酸化法によシ基板上全面に形成
する。次に、耐不利物拡散性の尋寛換となる例えばチタ
ンカーバイド族４を、たとえば反応性ス・ぐツタ法によ
り基板上全面に５００又の厚さとなるように堆積形成す
る。欠に、ケ・−計電極配線用多結晶シリコン材料を基
板上全面に堆積する。次に、ｐｏｃｔ、拡散法により上
記多結晶シリコン材料中にＮ型不純物をドーグする。次
いで、周知のＰＥＰ法（フォトエツチング法）、ＰＩＥ
法（反応性イオンエツチング法）を用いて多結晶シリコ
ン材料およびチタンカーバイド族４のパターニングを行
い、第１囚（ｂ）に示すようにゲート電極パターン５お
よびチタンカーバイド族４′を自己螢合的に形成する。(Function) Since the lower part or the periphery of the polycrystalline silicon material is covered with a film that serves as a barrier for impurity diffusion, impurities contained in the polycrystalline silicon material can be removed even after the thermal process of the semiconductor device manufacturing process. will not diffuse into the lower layer or the surrounding area, making it possible to prevent deterioration of the characteristics and reliability of the semiconductor element. (Example) An example of the present invention will be described in detail below with reference to the drawings. Explain◎ Figures 1 (,) to (d) show the MQ in MO8 type LSI.
S) Shows the manufacturing process of transistors. That is, first, as shown in FIG. 1(a), a field oxide film 2 is selectively formed on a semiconductor substrate (for example, a P-type silicon substrate) J using a thermal oxidation method. Next, a dirt insulating film is formed on the entire surface of the substrate by silicon oxidation ts3t-thermal oxidation method. Next, for example, titanium carbide group 4, which is highly resistant to diffusion of disadvantageous substances, is deposited on the entire surface of the substrate to a thickness of 500 mm by using, for example, a reactive staining method. In the meantime, a polycrystalline silicon material for electrode wiring is deposited over the entire surface of the substrate. Next, an N-type impurity is doped into the polycrystalline silicon material using a poct diffusion method. Next, the well-known PEP method (photoetching method), PIE method
The polycrystalline silicon material and the titanium carbide group 4 are patterned using a reactive ion etching method (reactive ion etching method), and the gate electrode pattern 5 and the titanium carbide group 4' are patterned in a self-synthesizing manner as shown in the first image (b). to form.
なお、このときゲート′＃を極／臂ターン５に連なる多
結晶シリコン材料からなる配線ツクターン（図示せず）
およびその下層のチタンカーバイド膜／４’ターン（図
示せず）も同時に形成する。次に、上記ゲート電極ｉ４
ターン５をマスクとするイオン注入、その後のアニール
処理によシ第１図（Ｃ）に示すようにソース拡散層領域
６、ドレイン拡散層領域７を形成する。次に、第１図（
ｄ）に示すように、基板上全面にＰＳＧ層（リン・シリ
ケート・ガラスノー）８を形成し、さらに周知の方法に
より上記ＰＳＧ層８にコンタクトホールを開孔し、基板
上全面に金属配線膜（たとえばアルミニウム・シリコン
配線）を形成し、その・９ターニングを行って゛金属配
線９を形成する。In addition, at this time, the gate '# is connected to the pole/arm turn 5 by a wiring turn (not shown) made of polycrystalline silicon material.
And the underlying titanium carbide film/4' turn (not shown) is also formed at the same time. Next, the gate electrode i4
By ion implantation using the turn 5 as a mask and subsequent annealing treatment, a source diffusion layer region 6 and a drain diffusion layer region 7 are formed as shown in FIG. 1(C). Next, Figure 1 (
As shown in d), a PSG layer (phosphorus silicate glass) 8 is formed on the entire surface of the substrate, contact holes are formed in the PSG layer 8 by a well-known method, and a metal wiring film ( For example, a metal wiring 9 is formed by forming an aluminum silicon wiring 9 and turning it 9 times.
上記のように形成さｒｔだ第１図（ｄ）のＭＱＳ ）ラ
ンジスタによれば、多結晶シリコン材料５の下部全面に
耐不純物拡散性展となるチタンカーバイド膜４′が設け
ら札ているので、多結晶シリコン材料堆積後の熱工程に
よって多結晶シリコン材料から不純物（本例ではリン）
がケ゛−ト絶脈換３に拡散することがρノ止され、ＭＱ
Ｓ トランジスタの特性の劣化や信頼性の低下から完全
に保膿される。According to the MQS transistor (FIG. 1(d)) formed as described above, a titanium carbide film 4' which is resistant to impurity diffusion is provided on the entire lower part of the polycrystalline silicon material 5. , impurities (phosphorous in this example) are removed from the polycrystalline silicon material by a thermal process after the polycrystalline silicon material is deposited.
ρ is prevented from spreading to the network 3, and MQ
S: Completely impregnated due to deterioration of transistor characteristics and decrease in reliability.
なお、上記実施例では、耐拡散性導電膜としてチタンカ
ーバイド膜を用いたが、これに限らず、チタンナイトラ
イドを用いてもよい。また、上記実施例では、電極配線
用の多結晶シリコン材料の下部にのみ耐拡散性導電膜を
設けたが、上記多結晶シリコン材料の周囲を完全に覆う
ように耐拡散性導電膜を設けることによって、多結晶シ
リコン材料から周囲の絶縁膜への不純物拡散を防止する
ようにしてもよく、その−例を第２図に示す。即ち、第
２図に示すＭＱＳ）ランジスタは、第１図（ｄ）を参照
して前述したＭＱＳ ）ランジスタに比べてダート電極
パターン５の周囲をチタンカーバイド膜２０で楓ってい
る点が異なり、その他は同じであり、第１図（ｄ）中と
同一部分には同一符号を付してその説明を省略する。ま
た、上記各実施例は、−層の多結晶シリコンゲート電極
を有するＭＯ８型ＬＳＩを示したが、これに限ることな
く、二層以上の多結晶シリコンケ゛−ト電極を有するＭ
Ｏ８型ＬＳＩにも本発明を適用でき、その−例を第３図
に示す。In the above embodiment, a titanium carbide film was used as the diffusion-resistant conductive film, but the film is not limited to this, and titanium nitride may also be used. Further, in the above embodiment, the diffusion-resistant conductive film was provided only under the polycrystalline silicon material for electrode wiring, but the diffusion-resistant conductive film may be provided to completely cover the periphery of the polycrystalline silicon material. This may be used to prevent impurity diffusion from the polycrystalline silicon material to the surrounding insulating film, an example of which is shown in FIG. That is, the MQS transistor shown in FIG. 2 differs from the MQS transistor described above with reference to FIG. 1D in that the dirt electrode pattern 5 is surrounded by a titanium carbide film 20. The rest is the same, and the same parts as in FIG. 1(d) are given the same reference numerals and their explanations will be omitted. Further, although each of the above embodiments has shown an MO8 type LSI having a -layer polycrystalline silicon gate electrode, the present invention is not limited to this, and an M08 type LSI having a polycrystalline silicon gate electrode of two or more layers can be used.
The present invention can also be applied to an O8 type LSI, an example of which is shown in FIG.
即ち、第３図は浮遊ケ◆−ト型トランジスタを示してお
り、第１図（ａ）を参照して前述したＭＯＳ ）ランジ
スタに比べて、多結晶シリコン材料からなる浮遊ゲート
電極パターン３ノと制御ダート電極・クターン（および
図示しない制御ｒ−）配線）３２とが二層となるように
形成されており、浮遊ｆｆ−）電極ノ母ターン３ノの下
部にチタンカーバイド膜３３が形成されており、上記２
つのダート電極ｉ４？ターン３１．３２の層間にダート
絶縁膜（シリコン酸化膜）３４が形成されており、制御
ダート電極パターン３２の下部（上記ダート酸化膜３４
の上部）にチタンカーバイド膜３５が形成されている点
が異なり、その他は同じであるので第１図（ｄ）中と同
一部分には同一符号を付してその説明を省略する。That is, FIG. 3 shows a floating gate transistor, which has a floating gate electrode pattern 3 made of polycrystalline silicon material, compared to the MOS transistor described above with reference to FIG. 1(a). A control dirt electrode/cutan (and control r-) wiring (not shown) 32 is formed in two layers, and a titanium carbide film 33 is formed under the mother turn 3 of the floating ff-) electrode. Yes, above 2
Two dart electrodes i4? A dirt insulating film (silicon oxide film) 34 is formed between the layers of the turns 31 and 32, and the lower part of the control dirt electrode pattern 32 (the dirt oxide film 34) is formed between the layers of the turns 31 and 32.
1(d) except that a titanium carbide film 35 is formed on the upper part of FIG.
また、上記各実施例では、不純物拡散の障壁となる導を
膜としてチタンカーバイド膜、チタンナイトライド膜を
例示したが、これらに限らず、粒界拡散を防止しである
高融点金属の窒化物や炭化物を使用することができる。In each of the above embodiments, a titanium carbide film and a titanium nitride film are used as conductive films that act as a barrier to impurity diffusion, but the invention is not limited to these. or carbide can be used.
また、上記各実施例では、ＭＯ８ＷＬＳＩを示したが、
他のバイポーラ素子や容量素子などの半導体素子に対し
て一般的に本発明を適用することができる。In addition, in each of the above embodiments, MO8WLSI was shown, but
The present invention can generally be applied to other semiconductor devices such as bipolar devices and capacitive devices.
［発明の幼果コ
上述したように本発明の半導体装置によれば、半導体索
子の電極等の配線とか半導体素子間配線に高来槓化が可
能な多結晶シリコン材料を用いると共に、その下部ある
いは周囲に不純物拡散の障壁となる耐拡散性溝ｔｇ＋を
設けることにより、多結晶シリコン材料に含まれる不純
物が外部に拡散して半導体索子の特性、信頼性の劣化を
まねくことを防止できるので、ＶＬＳＩＯＬＳＩ化、高
信頼性化が可能になる。[Young Fruit of the Invention] As described above, according to the semiconductor device of the present invention, a polycrystalline silicon material that can be made into a high-density material is used for the wiring such as the electrodes of the semiconductor cables and the wiring between semiconductor elements, and the lower part of the polycrystalline silicon material is used. Alternatively, by providing a diffusion-resistant groove tg+ around the periphery that acts as a barrier to impurity diffusion, it is possible to prevent impurities contained in the polycrystalline silicon material from diffusing to the outside and causing deterioration of the characteristics and reliability of the semiconductor cord. , VLSIOLSI, and high reliability becomes possible.
第１図（ａ）乃至（ｄ）は本発明の半導体装置の一実施
例の製造工程を示す断面図、第２図および第３図はそれ
ぞれ本発明の他の実施例に係る牛得体装置を示す断面図
、第４図は従来のＭＯ８型トランジスタを示す断面図で
ある。
３．３４・・・ダート絶縁膜、４．２０・・・チタンカ
ーバイド膜、５・・・ｒ−）電極、８・・・ＰＳＧ膜、
３１°°°浮遊ｆ−）電極、３２・°・制御ダート電極
、３３゜３５・・・チタンカルバイト膜。
出顔人代理人 弁理士銘 江 武 彦（ａ）
（ｂ）
第１図1(a) to (d) are cross-sectional views showing the manufacturing process of one embodiment of the semiconductor device of the present invention, and FIG. 2 and FIG. FIG. 4 is a cross-sectional view showing a conventional MO8 type transistor. 3.34...Dart insulating film, 4.20...Titanium carbide film, 5...r-) electrode, 8...PSG film,
31°°° floating f-) electrode, 32°・controlled dart electrode, 33°35... titanium carbide film. Appearing agent Patent attorney name: Takehiko E (a) (b) Figure 1
Claims (1)
リコン材料と下層の絶縁膜あるいは周囲の絶縁膜との間
に、上記多結晶シリコン材料に含まれる不純物の拡散を
防止する障壁用導電膜を設けてなることを特徴とする半
導体装置。A barrier conductive film for preventing diffusion of impurities contained in the polycrystalline silicon material is provided between a semiconductor element or a polycrystalline silicon material for wiring between semiconductor elements and an underlying insulating film or a surrounding insulating film. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63017213A JP2695812B2 (en) | 1988-01-29 | 1988-01-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63017213A JP2695812B2 (en) | 1988-01-29 | 1988-01-29 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01194335A true JPH01194335A (en) | 1989-08-04 |
| JP2695812B2 JP2695812B2 (en) | 1998-01-14 |
Family
ID=11937666
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63017213A Expired - Fee Related JP2695812B2 (en) | 1988-01-29 | 1988-01-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2695812B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100407238B1 (en) * | 2000-03-16 | 2003-11-28 | 샤프 가부시키가이샤 | Method for forming conducting diffusion barriers |
| JP2005347705A (en) * | 2004-06-07 | 2005-12-15 | Samsung Electronics Co Ltd | Semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5877257A (en) * | 1981-11-04 | 1983-05-10 | Hitachi Ltd | Superiorly high reliable electrode |
| JPS58210639A (en) * | 1982-05-31 | 1983-12-07 | Toshiba Corp | Semiconductor device |
| JPS61144872A (en) * | 1984-12-19 | 1986-07-02 | Toshiba Corp | Semiconductor device |
| JPS62111466A (en) * | 1985-11-09 | 1987-05-22 | Toshiba Corp | Semiconductor device |
| JPS63150963A (en) * | 1986-12-12 | 1988-06-23 | Fujitsu Ltd | Semiconductor device |
-
1988
- 1988-01-29 JP JP63017213A patent/JP2695812B2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5877257A (en) * | 1981-11-04 | 1983-05-10 | Hitachi Ltd | Superiorly high reliable electrode |
| JPS58210639A (en) * | 1982-05-31 | 1983-12-07 | Toshiba Corp | Semiconductor device |
| JPS61144872A (en) * | 1984-12-19 | 1986-07-02 | Toshiba Corp | Semiconductor device |
| JPS62111466A (en) * | 1985-11-09 | 1987-05-22 | Toshiba Corp | Semiconductor device |
| JPS63150963A (en) * | 1986-12-12 | 1988-06-23 | Fujitsu Ltd | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100407238B1 (en) * | 2000-03-16 | 2003-11-28 | 샤프 가부시키가이샤 | Method for forming conducting diffusion barriers |
| JP2005347705A (en) * | 2004-06-07 | 2005-12-15 | Samsung Electronics Co Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2695812B2 (en) | 1998-01-14 |
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