JPH01192216A - Delay circuit - Google Patents

Delay circuit

Info

Publication number
JPH01192216A
JPH01192216A JP63017934A JP1793488A JPH01192216A JP H01192216 A JPH01192216 A JP H01192216A JP 63017934 A JP63017934 A JP 63017934A JP 1793488 A JP1793488 A JP 1793488A JP H01192216 A JPH01192216 A JP H01192216A
Authority
JP
Japan
Prior art keywords
pulse
bit
frequency division
delay
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63017934A
Other languages
Japanese (ja)
Inventor
Kuniyasu Hayashi
林　国康
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63017934A priority Critical patent/JPH01192216A/en
Publication of JPH01192216A publication Critical patent/JPH01192216A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To decrease the circuit scale by employing mainly a 1/n-1 frequency division binary counter in case of n-bit delay of an isolated input pulse. CONSTITUTION:With an isolated pulse 106 whose pulse width is T given to the input, a signal line 107 being an output of an RS flip-flop 105 goes to an H level. Then a 1/16 frequency division counter 102 is released from the reset state and applies counts by a clock 101 whose period is T. An output is generated by a carry out generating circuit 103 after 16-bit, it is retarded by one bit at a retiming circuit 104 to obtain a delay pulse 108 with a pulse width T retarded by 17-bit in total. Then the RS flip-flop 105 is triggered by the delay pulse 108, the signal line 107 being the output goes to an L leel and the 1/16 frequency division counter 102 is fixed to the reset state. In case of retarding the isolated input pulse by n-bit, a 1/n-1 frequency division counter is employed mainly, then the circuit scale is reduced by log2(n-1)/n.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はディジタル回路における遅延回路に関し、特に
クロック周期で量子化された遅延量を持ち、さらに遅延
されるもののパルス幅がクロック周期と同一のものに関
する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a delay circuit in a digital circuit, and in particular has a delay amount quantized by a clock cycle, and which has a pulse width that is the same as the clock cycle. related to things.

〔従来の技術〕[Conventional technology]

従来、この種の遅延回路はｎビット遅延させる場合には
、周期Ｔのクロックで動作するＤ形フリップフロップを
直列にｎ個接続して、ｎビットのシフトレジスタを構成
することにより作られていた。Conventionally, when delaying by n bits, this type of delay circuit was made by connecting n D-type flip-flops in series that operated with a clock with period T to form an n-bit shift register. .

第２図は従来の１７ビツト遅延回路の一例の回路図であ
る。入力パルス１０６が１７個のＤ形フリップフロップ
２０１ａにより構成したシフトレジスタ２０１でクロッ
ク１０１によってシフトされ、１７ビツト遅延した遅延
パルス１０８が得られる。FIG. 2 is a circuit diagram of an example of a conventional 17-bit delay circuit. An input pulse 106 is shifted by a clock 101 in a shift register 201 composed of 17 D-type flip-flops 201a, and a delayed pulse 108 delayed by 17 bits is obtained.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の遅延回路は、遅延量（ｎビット）のビッ
ト数個のＤ形フリップフロップが必要であり、遅延量が
大きくなると回路規模がそれに比例して大きくなるとい
う欠点がある。The conventional delay circuit described above requires D-type flip-flops for several bits corresponding to the amount of delay (n bits), and has the disadvantage that as the amount of delay increases, the circuit scale increases in proportion to the amount of delay.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の遅延回路は、パル幅がＴの孤立パルスをｎビッ
ト遅延させるとき、周期Ｔのクロックをｎ−１分周しキ
ャリィ信号を出力するｎ−１分周カウンタ及びキャリィ
アウド発生回路と、前記キャリィ信号を前記クロックで
リタイミングした遅延パルスを出力するリタイミング回
路゛と、前記ｎ−１分周カウンタを前記孤立パルスによ
り動作させ前記遅延パルスによりリセットさせるＲＳフ
リップフロップとを有することを特徴とする。The delay circuit of the present invention comprises an n-1 frequency dividing counter and a carry signal generation circuit which divides a clock having a period T by n-1 and outputs a carry signal when delaying an isolated pulse having a pulse width of T by n bits; The present invention is characterized by comprising a retiming circuit that outputs a delayed pulse obtained by retiming the carry signal using the clock, and an RS flip-flop that operates the n-1 frequency division counter using the isolated pulse and resets it using the delayed pulse. do.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は、本発明の一実施例の１７ビツト遅延回路の回
路図である。FIG. 1 is a circuit diagram of a 17-bit delay circuit according to an embodiment of the present invention.

入力にパルス幅Ｔの孤立パルス１０６（この場合、常時
「Ｈ」レベルでパルス幅Ｔだけ「Ｌ」レベルになるもの
を考える）が入力されると、ＲＳフリップフロップ１０
５の出力である信号線１０７がｒＨｕレベルになり、１
６分周カウンタ１０２がリセット状態から解除されて、
周期がＴのクロック１０１によってカウント動作を行な
う。When an isolated pulse 106 with a pulse width T is input to the input (in this case, consider a pulse that is always at "H" level and becomes "L" level by the pulse width T), the RS flip-flop 10
The signal line 107 which is the output of 5 becomes rHu level, and 1
The divide-by-6 counter 102 is released from the reset state,
A counting operation is performed by a clock 101 having a period of T.

１６ビツト後に、キャリィアウド発生回路１０３により
出力が発生され、それをリタイミング回路１０４により
１ビツト遅延させ合計１７ビツート遅延させたパルス幅
Ｔの遅延パルス１０８が得られる。そしてさらにこの遅
延パルス１０８によってＲＳフリップフロップ１０５が
トリガされて、その出力である信号線１０７が「Ｌ」レ
ベルになり、１６分周カウンタ１０２はリセット状態に
固定され、次の入力パルスが入力されるまで待つことに
なる。After 16 bits, the carry-out generation circuit 103 generates an output, which is delayed by 1 bit by the retiming circuit 104 to obtain a delayed pulse 108 having a pulse width T delayed by a total of 17 bits. Furthermore, the RS flip-flop 105 is triggered by this delayed pulse 108, and its output, the signal line 107, goes to the "L" level, and the divide-by-16 counter 102 is fixed in the reset state, and the next input pulse is input. You will have to wait until the

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、孤立入力パルスをｎビッ
ト遅延させる場合、ｎ−１分周バイナリカウンタを中心
に構成することにより、従来のＤ形フリップフロップの
構成ではｎ個必要であるのに対してｅｏｇｚ　　（ｎ−
１）＋１値で構成でき、つまり従来比でｅｏｇｚ　（ｎ
−１）／ｎだけ回路規模を小さくできるという効果があ
る。As explained above, in the case of delaying an isolated input pulse by n bits, the present invention is configured mainly with a binary counter divided by n-1, whereas n pieces are required in the conventional D-type flip-flop configuration. On the other hand, eogz (n-
1) It can be configured with +1 value, which means eogz (n
There is an effect that the circuit scale can be reduced by -1)/n.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例の回路図、第２図は従来の遅
延回路の一例の回路図である。 １０１・・・クロック、１０２・・・１６分周カウンタ
、１０３・・・キャリィアウド発生回路、１０４・・・
リタイミング回路、１０５・・・ＲＳフリップフロップ
、１０６・・・孤立パルス、１０７・・・信号線、１０
８・・・遅延パルス、２０１・・・１７ビツトシフトレ
ジスタ。 代理人　弁理士　　内　原　　晋FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an example of a conventional delay circuit. 101... Clock, 102... 16 frequency division counter, 103... Carry-out generation circuit, 104...
Retiming circuit, 105... RS flip-flop, 106... Isolated pulse, 107... Signal line, 10
8...Delayed pulse, 201...17-bit shift register. Agent Patent Attorney Susumu Uchihara

Claims (1)

【特許請求の範囲】[Claims] パル幅がＴの孤立パルスをｎビット遅延させるとき、周
期Ｔのクロックをｎ−１分周しキャリィ信号を出力する
ｎ−１分周カウンタ及びキャリィアウト発生回路と、前
記キャリィ信号を前記クロックでリタイミングした遅延
パルスを出力するリタイミング回路と、前記ｎ−１分周
カウンタを前記孤立パルスにより動作させ前記遅延パル
スによりリセットさせるＲＳフリップフロップとを有す
ることを特徴とする遅延回路。When an isolated pulse with a pulse width of T is delayed by n bits, an n-1 frequency division counter and a carry-out generation circuit which divides a clock having a period T by n-1 and outputs a carry signal; A delay circuit comprising: a retiming circuit that outputs a retimed delay pulse; and an RS flip-flop that operates the n-1 frequency division counter by the isolated pulse and resets it by the delay pulse.
JP63017934A 1988-01-27 1988-01-27 Delay circuit Pending JPH01192216A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63017934A JPH01192216A (en) 1988-01-27 1988-01-27 Delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63017934A JPH01192216A (en) 1988-01-27 1988-01-27 Delay circuit

Publications (1)

Publication Number Publication Date
JPH01192216A true JPH01192216A (en) 1989-08-02

Family

ID=11957603

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63017934A Pending JPH01192216A (en) 1988-01-27 1988-01-27 Delay circuit

Country Status (1)

Country Link
JP (1) JPH01192216A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100361388C (en) * 2004-12-24 2008-01-09 科圆半导体（上海）有限公司 Programmable asynchronous triggering time delayer, and method of use

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5325346A (en) * 1976-08-20 1978-03-09 Matsushita Electric Ind Co Ltd Digital delay circuit
JPS6091717A (en) * 1983-10-26 1985-05-23 Hitachi Ltd Digital delay circuit
JPS6123412A (en) * 1984-07-11 1986-01-31 Advantest Corp Timing generator
JPS61140215A (en) * 1984-12-12 1986-06-27 Nec Corp Pulse generating circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5325346A (en) * 1976-08-20 1978-03-09 Matsushita Electric Ind Co Ltd Digital delay circuit
JPS6091717A (en) * 1983-10-26 1985-05-23 Hitachi Ltd Digital delay circuit
JPS6123412A (en) * 1984-07-11 1986-01-31 Advantest Corp Timing generator
JPS61140215A (en) * 1984-12-12 1986-06-27 Nec Corp Pulse generating circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100361388C (en) * 2004-12-24 2008-01-09 科圆半导体（上海）有限公司 Programmable asynchronous triggering time delayer, and method of use

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