JPH01173649A - Manufacture of thin-film transistor - Google Patents
Manufacture of thin-film transistorInfo
- Publication number
- JPH01173649A JPH01173649A JP33150887A JP33150887A JPH01173649A JP H01173649 A JPH01173649 A JP H01173649A JP 33150887 A JP33150887 A JP 33150887A JP 33150887 A JP33150887 A JP 33150887A JP H01173649 A JPH01173649 A JP H01173649A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- forming
- gate electrode
- contact hole
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000010409 thin film Substances 0.000 title claims description 9
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000011229 interlayer Substances 0.000 claims abstract description 8
- 230000003647 oxidation Effects 0.000 claims abstract description 4
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 4
- 239000010408 film Substances 0.000 claims description 37
- 239000010410 layer Substances 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 14
- 229910052681 coesite Inorganic materials 0.000 abstract description 7
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 7
- 239000000377 silicon dioxide Substances 0.000 abstract description 7
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 7
- 229910052682 stishovite Inorganic materials 0.000 abstract description 7
- 229910052905 tridymite Inorganic materials 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
援批立互
本発明はゲート酸化膜を残した状態でソース・ドレイン
領域を形成する工程を含む薄膜トランジスターの改良製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved method for manufacturing a thin film transistor including a step of forming source/drain regions with a gate oxide film remaining.
従来技術
ガラス板のような絶縁基板上に形成される薄膜トランジ
スターの製造方法として絶縁基板上にｐｏｌｙ Ｓｉ、
ａ−Ｓｉ（アモルファスＳｉ）等の８１半導体活性層、
ＳｉＯ，のゲート酸化膜及び８１半導体系ゲート電極を
形成後、活性層にソース・ドレイン領域を形成し、更に
５ｊＯ２の層間絶縁膜、コンタクトホール及びこのホー
ルにＡＱのような金属電極を形成する方法が知ら才℃て
いる。Prior Art As a method for manufacturing a thin film transistor formed on an insulating substrate such as a glass plate, polySi,
81 semiconductor active layer such as a-Si (amorphous Si),
After forming a SiO gate oxide film and an 81 semiconductor gate electrode, a source/drain region is formed in the active layer, and a 5jO2 interlayer insulating film, a contact hole, and a metal electrode such as AQ are formed in this hole. He is known for his talent.
しかしこの方法ではゲート酸化膜を残した状態でソース
・ドレイン領域を形成後、そのまま層間絶縁膜及びコン
タクトホールを形成するため、ゲート電極上とソース・
トレイン領域上とではゲート酸化膜厚分だけ酸化膜厚が
異なり、その結果、コンタクトホールの形成時、ゲート
電極上ではオーバーエツチングとなってコンタクトホー
ルの形状、大きさ等にかなりのバラツキが生じた。However, in this method, after forming the source/drain region with the gate oxide film remaining, the interlayer insulating film and contact hole are formed as is, so the source/drain region is formed on the gate electrode and the source/drain region is formed.
The oxide film thickness on the train region differs by the thickness of the gate oxide film, and as a result, when forming the contact hole, over-etching occurred on the gate electrode, resulting in considerable variation in the shape, size, etc. of the contact hole. .
月−一一的一
本発明の目的はコンタクトホールの形状、犬きさ等のバ
ラツキをなくして歩留りの向上を計った薄膜トランジス
ターの製造方法を提供することである。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing thin film transistors that improves yield by eliminating variations in the shape, size, etc. of contact holes.
碧−一」文
本発明方法は絶縁基板上にＳｉ半導体活性層、Ｓｉｏ、
のゲート化膜及びＳｉ半導体系ゲート電極を形成後、活
性層にソース・ドレイン領域を形成し、ついでＳｉＯ２
、の層間絶縁膜を形成する工程を含む薄膜トランジスタ
ーの製造方法において、ソース・ドレイン領域の形成工
程と眉間絶縁膜の形成工程との間にゲート電極の周囲に
熱酸化によりゲート酸化膜とほぼ同じ厚さのＳｉＯ□酸
化膜を形成する工程を付加したことを特徴とするもので
ある。``Aoi-ichi'' The method of the present invention is to form a Si semiconductor active layer, Sio, on an insulating substrate.
After forming a gating film and a Si semiconductor gate electrode, source/drain regions are formed in the active layer, and then SiO2
In a thin film transistor manufacturing method including a step of forming an interlayer insulating film of This method is characterized by adding a step of forming a thick SiO□ oxide film.
このように本発明の薄膜トランジスターの製造方法はゲ
ート酸化膜を残した状態でソース・ドレイン領域を形成
する際、ゲート電極上にもＳｉｏ、酸化膜を形成するこ
とにより、コンタクトホール形成時のゲート電極上での
オーバーエツチングを防止したものである。As described above, in the method for manufacturing a thin film transistor of the present invention, when forming the source/drain regions with the gate oxide film remaining, by forming an Sio and oxide film on the gate electrode as well, the gate oxide film can be formed easily. This prevents over-etching on the electrode.
本発明方法をＣＭＯ３型Ｏ３トランジスターの製造例で
図面に従って説明すると、第１図においてまずガラス板
等の同一絶縁基板１のＰチャンネル及びＮチャンネルト
ランジスターとなる部分に減圧ＣＶＤ法（例えばＳｉＨ
４流量５０ＳＣＣＭ、真空度０．５ｔｏｒｒ及び温度６
３０℃の条件）等でｐｏｌｙ Ｓｉ、ａ−Ｓｉ等のＳｉ
半導体を例えば２０００人厚程度に堆積せしめてＳｉ半
導体膜を形成した後、フォトリソグラフィー・エツチン
グ法によりパターンニングを行なってＳｉ半導体活性層
２を形成する〔第１図（ａ）） 、引続き熱酸化（例え
ばＨｘ ／ Ｏｚ雰囲気中、温度９５０℃の条件）を行
なって１５００人厚程度のＳｉｏ、からなるゲート酸化
膜を形成せしめる〔第１図（ｂ））、次にその上にゲー
ト電極となるＳｉ半導体を減圧ＣＶＤ法等（条件は活性
層の場合と同じでよい、）で例えば４０００人厚程度に
堆積せしめてＳｉ半導体膜４を形成した後、この中に塗
布拡散法又は気相拡散法によりＰ＋を拡散せしめ、Ｓｉ
半導体膜４を低抵抗化せしめる〔第１図（ｃ））、次に
フォトリソグラフィー・エツチング法によりＳｉ半導体
膜４をパターンニングしてゲート電極４′を形成し〔第
１図（ｄ））、レジスト５を残したまま矢印６で示すよ
うにイオン注入法（例えば注入エネルギー８０ｋｅｖ及
びドーズ量２ｘ１０°／ｄの条件）によりゲート酸化膜
３を通して雨活性層２中にＢ＋イオンを注入する。この
操作によりＮチャンネル側の活性層ではソース・ドレイ
ン領域７が形成される（第１図（ｅ））。The method of the present invention will be explained with reference to the drawings using an example of manufacturing a CMO3 type O3 transistor. In Fig. 1, first, a low pressure CVD method (for example, SiH
4 Flow rate 50SCCM, vacuum degree 0.5 torr and temperature 6
Si (poly Si, a-Si, etc.)
After forming a Si semiconductor film by depositing a semiconductor to a thickness of, for example, about 2,000 layers, patterning is performed by photolithography and etching to form a Si semiconductor active layer 2 [Fig. 1(a)], followed by thermal oxidation. (for example, in a Hx/Oz atmosphere at a temperature of 950°C) to form a gate oxide film of about 1,500 layers of Sio (Fig. 1(b)), and then form a gate electrode on top of it. After forming a Si semiconductor film 4 by depositing a Si semiconductor to a thickness of, for example, about 4,000 layers using a low pressure CVD method (the conditions may be the same as those for the active layer), a coating diffusion method or a vapor phase diffusion method is applied to the Si semiconductor film 4. to diffuse P+, and Si
The resistance of the semiconductor film 4 is lowered (FIG. 1(c)), and then the Si semiconductor film 4 is patterned by photolithography and etching to form a gate electrode 4' (FIG. 1(d)). With the resist 5 left in place, B+ ions are implanted into the rain active layer 2 through the gate oxide film 3 by an ion implantation method (for example, under conditions of implantation energy of 80 keV and dose amount of 2×10°/d), as shown by arrow 6. By this operation, source/drain regions 7 are formed in the active layer on the N-channel side (FIG. 1(e)).
次にレジスト５を除去し、Ｎチャンネル側だけレジスト
５′でマスキングした後、矢印６′で示すようにイオン
注入法（例えば注入エネルギー１５０ｋｅｖ及びドーズ
量５ＸＩＯ”／−の条件）によりＰ４をＮチャンネル側
の活性層２に注入する。Next, after removing the resist 5 and masking only the N-channel side with a resist 5', the N-channel P4 is implanted by ion implantation (for example, under the conditions of implantation energy of 150 kev and dose of 5XIO"/-) as shown by arrow 6'. Inject into the active layer 2 on the side.
この操作によりＮチャンネル側の活性層２ではＰｏが８
０をコンペンゼートすることによりソース・ドレイン領
域７′が形成される〔第１図（ｆ）） 、次にレジスト
５′を除去し、全面を熱酸化（例えばＨ２／ ０２雰囲
気中、温度１００℃の条件）により電極４′の周囲にゲ
ート酸化膜３（好ましくはソース・ドレイン上の酸化膜
）とほぼ同じ厚さのＳｉｏ、酸化膜３′を形成する〔第
１図（ｇ））、前記熱酸化条件を３０〜４０分行なえば
ゲート電極の周囲のＳｉＯ２膜厚は約１７００〜１８０
０人となり、ソース・ドレイン領域上のＳｉＯ２、膜厚
も約１７００〜１８００人となり、両膜厚はほぼ同一と
なる。以下、常法により全面にＳｉＯ２、の層間絶縁膜
８及びコンタクトホール９を形成後、このホールにＡＱ
のような金属電極（図示せず）を形成し、シニターを行
なえば、ＣＭＯ８型Ｏ８トランジスターが得られる。With this operation, Po is 8 in the active layer 2 on the N-channel side.
The source/drain region 7' is formed by compensating the resist 5' (FIG. 1(f)). Next, the resist 5' is removed and the entire surface is thermally oxidized (for example, in an H2/02 atmosphere at a temperature of 100°C). An oxide film 3' is formed around the electrode 4' with approximately the same thickness as the gate oxide film 3 (preferably the oxide film on the source/drain) according to If the oxidation conditions are carried out for 30 to 40 minutes, the thickness of the SiO2 film around the gate electrode will be approximately 1700 to 180 mm.
The thickness of the SiO2 film on the source/drain region is approximately 1,700 to 1,800, and both film thicknesses are approximately the same. After forming an interlayer insulating film 8 of SiO2 and a contact hole 9 on the entire surface by a conventional method, this hole is filled with an AQ
A CMO8 type O8 transistor can be obtained by forming a metal electrode (not shown) and performing sintering.
効 果
本発明方法によればコンタクトホール形成前にゲート電
極の周囲にゲート酸化膜とほぼ同じ厚さのＳｉｏ、酸化
膜を形成する工程を付加したので、コンタクトホール形
成時にゲート電極上でオーバーエツチングされることが
なく、このためコンタクトホールの形状、大きさ等のバ
ラツキが少なくなる結果、製品の歩留りを向上すること
ができる。Effects According to the method of the present invention, a step of forming an SiO oxide film with approximately the same thickness as the gate oxide film around the gate electrode is added before forming the contact hole, so that over-etching on the gate electrode is avoided when forming the contact hole. Therefore, variations in the shape, size, etc. of the contact holes are reduced, and as a result, the yield of products can be improved.
第１図は本発明の薄膜トランジスターの一例の製造工程
図である。
１・・・絶縁基板 ２・・・Ｓｉ半導体活性層３
・・・ゲート酸化膜 ４・・・Ｓ、を半導体膜４′・
・・ゲート電極 ５，５′・・・レジスト６．６′
・・・イオン注入 ７，７′・・・ソース・ドレイン
領域８・・・層間絶縁膜 ９・・・コンタクトホー
ル第１図FIG. 1 is a manufacturing process diagram of an example of the thin film transistor of the present invention. 1... Insulating substrate 2... Si semiconductor active layer 3
...Gate oxide film 4...S, semiconductor film 4'.
...Gate electrode 5,5'...Resist 6.6'
...Ion implantation 7,7'...Source/drain region 8...Interlayer insulating film 9...Contact hole Fig. 1
Claims (1)
ト酸化膜及びＳｉ半導体系ゲート電極を形成後、活性層
にソース・ドレイン領域を形成し、ついでＳｉＯ＿２の
層間絶縁膜を形成する工程を含む薄膜トランジスターの
製造方法において、ソース・ドレイン領域の形成工程と
層間絶縁膜の形成工程との間にゲート電極の周囲に熱酸
化によりゲート酸化膜とほぼ同じ厚さのＳｉＯ＿２、酸
化膜を形成する工程を付加したことを特徴とする薄膜ト
ランジスターの製造方法。1. A thin film that includes the steps of forming a Si semiconductor active layer, a SiO_2 gate oxide film, and a Si semiconductor-based gate electrode on an insulating substrate, forming source/drain regions in the active layer, and then forming an SiO_2 interlayer insulating film. In the method for manufacturing a transistor, a step of forming an SiO_2 oxide film with approximately the same thickness as the gate oxide film around the gate electrode by thermal oxidation is performed between the step of forming the source/drain region and the step of forming the interlayer insulating film. A method for manufacturing a thin film transistor characterized by the addition of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33150887A JPH01173649A (en) | 1987-12-26 | 1987-12-26 | Manufacture of thin-film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33150887A JPH01173649A (en) | 1987-12-26 | 1987-12-26 | Manufacture of thin-film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01173649A true JPH01173649A (en) | 1989-07-10 |
Family
ID=18244426
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33150887A Pending JPH01173649A (en) | 1987-12-26 | 1987-12-26 | Manufacture of thin-film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01173649A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6555843B1 (en) | 1991-05-16 | 2003-04-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
-
1987
- 1987-12-26 JP JP33150887A patent/JPH01173649A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6555843B1 (en) | 1991-05-16 | 2003-04-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
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