JPH0117271B2 - - Google Patents
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- Publication number
- JPH0117271B2 JPH0117271B2 JP4149681A JP4149681A JPH0117271B2 JP H0117271 B2 JPH0117271 B2 JP H0117271B2 JP 4149681 A JP4149681 A JP 4149681A JP 4149681 A JP4149681 A JP 4149681A JP H0117271 B2 JPH0117271 B2 JP H0117271B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- gate
- mask material
- etching
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- 239000000463 material Substances 0.000 claims description 47
- 238000005530 etching Methods 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 230000005669 field effect Effects 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 31
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 30
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 6
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 239000011669 selenium Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
この発明はシヨツトキバリアゲート電界効果ト
ランジスタ（MESFET）の製造方法に係り、特
に寄生抵抗を低減することにより高周波化された
高信頼度を有するMESFET装置の製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a shotgun barrier gate field effect transistor (MESFET), and more particularly to a method of manufacturing a MESFET device having high reliability and high frequency by reducing parasitic resistance.
砒化ガリウム（GaAs）を用いたMESFETは
現在マイクロ波通信機器における中心デバイスと
して使用されている。近年このGaAs MESFET
とGaAsダイオード等を一素子上に集積化しGbit
信号を処理しうる集積回路（IC）、特に高速ロジ
ツクやメモリの開発が活発に行なわれ、これらの
GaAs ICを用いて計算機の高速化や通信システ
ムの高性能化が実現できる可能性がでてきた。 MESFETs using gallium arsenide (GaAs) are currently used as central devices in microwave communication equipment. In recent years, this GaAs MESFET
Gbit
Integrated circuits (ICs) that can process signals, especially high-speed logic and memory, are being actively developed.
It is now possible to use GaAs ICs to increase the speed of computers and improve the performance of communication systems.
高速ロジツクやメモリの高性能化に際しては、
まず、これらのICの一構成要素であるFETの高
速化、高周波化を可能にする必要がある。
MESFETの高速化、高周波化を実現するために
は、MESFETのゲート容量Cgとソース・シリー
ズ抵抗Rsの低減、すなわちCg・Rs積の低減を計
ることが必須の要件となる。Cg・Rs積の低減対
策として１ゲート長の短縮化、２ゲート・ソース
間距離の短縮化が必要である。ゲート長の短縮化
には、従来より使用されていた紫外光（UV光）
による露光に代つて、波長が2200Å位の遠紫外光
（DUV光）または電子ビーム（EB）による露光
により0.2〜0.5μの微細パターンの形成が可能に
なつた。しかし、ゲート・ソース間距離の短縮化
の実現のためには、ゲートのパターンとソースの
パターンとの位置合せを厳密に行なう必要があ
り、装置上±0.2〜0.4μ位の精度しか実現できず、
位置合せのばらつきがMESFETの特性上のばら
つきになり、このMESFETを集積化した場合に
は、そのばらつきはより大きくなつてしまい、
ICの特性上の歩留りを低下させる最大の原因に
なる。 When improving the performance of high-speed logic and memory,
First, it is necessary to make FETs, which are one of the components of these ICs, faster and at higher frequencies.
In order to achieve higher speed and higher frequency MESFETs, it is essential to reduce the gate capacitance Cg and source series resistance Rs of the MESFET, that is, reduce the Cg × Rs product. As a measure to reduce the Cg/Rs product, it is necessary to shorten the length of one gate and the distance between two gates and the source. Ultraviolet light (UV light) has traditionally been used to shorten the gate length.
Instead of exposure using rays, it has become possible to form fine patterns of 0.2 to 0.5μ by exposure to deep ultraviolet light (DUV light) with a wavelength of about 2200 Å or electron beam (EB). However, in order to shorten the distance between the gate and the source, it is necessary to precisely align the gate pattern and the source pattern, and the equipment can only achieve an accuracy of about ±0.2 to 0.4 μ. ,
Variations in alignment lead to variations in MESFET characteristics, and when MESFETs are integrated, these variations become even larger.
This is the biggest cause of lower yield in terms of IC characteristics.
この発明は、ゲートパターンとソースパターン
との位置合せをすることなく、すなわち、セルフ
アライメントによりゲートとソースとの実効的な
距離を決め、MESFETのシリーズ抵抗を低減し
もつて、高速、高周波化され、特性上、高歩留り
を実現しうるMESFETの製造方法を提供するも
のである。 This invention determines the effective distance between the gate and source by self-alignment without aligning the gate pattern and source pattern, reduces the series resistance of MESFET, and achieves high speed and high frequency. The present invention provides a method for manufacturing MESFETs that can achieve high yield in terms of characteristics.
この発明は、一導電形半導体層を含む基板面に
絶縁膜を形成し、該絶縁膜上に該絶縁膜とは異な
る第２の物質膜を形成する工程、該第２の物質膜
上にマスク材を形成した後、該マスク材の一部を
除去してゲート相当部に開口を設ける工程、該マ
スク材を利用して、サイドエツチングにより前記
マスク材に設けたゲート相当部の開口よりも広
く、前記第２の物質膜を除去する工程、前記マス
ク材を利用して、異方性エツチングにより前記絶
縁膜の一部を除去し、前記一導電形半導体層の一
部を露出させる工程、マスク材を除去する工程、
耐熱性金属を被着する工程と、前記の第２の物質
膜をエツチングにより除去すると同時に第２の物
質膜上の前記耐熱性金属をリフトオフし耐熱性金
属ゲートを形成する工程、前記耐熱性金属ゲート
をマスクにして、絶縁膜を通して、あるいはアン
ダーカツトのないエツチングにより絶縁膜を薄く
した後、絶縁膜を通して、あるいはアンダーカツ
トのないエツチングにより絶縁膜を除去した後、
絶縁膜を通すことなくドレインおよびソース領域
に前記の一導電形半導体領域と同一導電形を形成
できるイオンを注入し、アニールする工程を含む
ことを特徴とするMESFETの製造方法である。 The present invention includes a step of forming an insulating film on a substrate surface including a semiconductor layer of one conductivity type, and forming a second material film different from the insulating film on the insulating film, and a step of forming a second material film on the second material film. After forming the mask material, a step of removing a part of the mask material to form an opening in the gate-equivalent part, using the mask material to side-etch the opening wider than the opening in the gate-equivalent part provided in the mask material. a step of removing the second material film; a step of removing a part of the insulating film by anisotropic etching using the mask material to expose a part of the one conductivity type semiconductor layer; and a mask. the process of removing material;
a step of depositing a heat-resistant metal; a step of removing the second material film by etching and simultaneously lifting off the heat-resistant metal on the second material film to form a heat-resistant metal gate; and a step of forming a heat-resistant metal gate. Using the gate as a mask, after thinning the insulating film through the insulating film or by etching without undercuts, after removing the insulating film through the insulating film or by etching without undercuts,
This method of manufacturing a MESFET is characterized by including a step of implanting ions capable of forming the same conductivity type as the semiconductor region of one conductivity type into the drain and source regions without passing through an insulating film, and annealing the same.
この製造方法により、イオン注入したソースお
よびドレイン領域はゲートとセルフアライメント
的に位置関係が決まると共に、ゲートとソースお
よびドレイン領域との距離を短かくすることが可
能であり、実効的にシリーズ抵抗を低減すること
ができる。 With this manufacturing method, the positional relationship between the ion-implanted source and drain regions is determined by self-alignment with the gate, and the distance between the gate and the source and drain regions can be shortened, effectively reducing the series resistance. can be reduced.
次に、この発明の効果をGaAs MESFETへの
実施例を用いて説明する。 Next, the effects of this invention will be explained using an example applied to a GaAs MESFET.
第１図ａは半絶縁性GaAs基板１上に成長され
たｎ型GaAs層２を示す。ｎ型GaAs層のドーパ
ントは一般はイオー（Ｓ）、シリコン（Si）、テル
ル（Te）、セレン（Se）、スズ（Sn）等が用いら
れ、そのキヤリア濃度は一般に５×1016cm-3から
３×1017cm-3である。また該ｎ型GaAs層の厚さ
は0.1μmから0.3μmである。次に第１図ｂに示す
ように、前記ｎ型GaAs層２上に例えば２酸化シ
リコン（SiO2）、シリコン窒化膜（SiN）等の絶
縁膜３を、例えば厚さ0.2μm形成し、つづいて該
絶縁膜上に、例えばアルミニウム（Al）等の第
２の物質膜４を形成する。次に第１図ｃに示すよ
うに、、ゲート相当部５をのぞいて、例えばホト
レジスト（PR）等のマスク材６を用いて前記の
第２の物質膜４を被覆する。第１図ｃにおいてゲ
ート相当部５は例えば電子ビームを用いて0.5μm
の幅のスリツトでマスク材６に露光し、現像する
ことにより形成することができる。次に第１図ｄ
に示すように、例えば40℃から60℃リン酸液を用
いてマスク材６をマスクにして第２の物質４のゲ
ート相当部をエツチングし、除去すると共に、前
記のマスク材６のゲート相当部５の幅、例えば
0.5μmよりも広く、サイドエツチングを利用し
て、例えば0.9μm程度の幅までエツチング除去す
る。次に第１図ｅに示すようにマスク材６をマス
クにして、例えば平行電極形ドライエツチングの
ような異方性エツチング方法により、マスク材６
のゲート相当部５、例えば0.5μmの幅に相当する
前記絶縁膜３を除去する。次に、マスク材６を除
去した後、第１図ｆに示すように、例えばTiW
合金（Ti10wt％）のごとき耐熱性金属７を例え
ばスパツタ法のごとき真空被着法により前記第２
の物質膜４および絶縁膜３およびｎ型GaAs層２
上に例えば0.3μの厚さに被着する。次に第１図ｇ
に示すように、例えばリン酸を用いて前記第２の
物質膜４をエツチング除去すると同時に、第２の
物質膜４上に形成された耐熱性金属７をリフトオ
フにより除去し、耐熱性金属ゲート８を形成す
る。次に前記の耐熱性金属ゲート８をマスクにし
て異方性エツチング方法により、前記絶縁膜３を
除去し、さらに耐熱性金属ゲート８をマスクにし
て、イオン注入法により例えばシリコン（Si）を
加速エネルギー200KeVで５×1013cm-2ドーズの
注入を前記のｎ型GaAs層２に行ない、砒素雰囲
気中で800℃の温度で15分間のアニールを行なう
と活性化率の平均が80％の高濃度キヤリア層９が
第１図ｈに示されるように形成される。次に第１
図ｉに示すようにソース電極１０およびドレイン
電極１１を前記の高濃度キヤリア層９上に形成す
るとGaAs MESFETが完成する。 FIG. 1a shows an n-type GaAs layer 2 grown on a semi-insulating GaAs substrate 1. FIG. Dopants for the n-type GaAs layer are generally sulfur (S), silicon (Si), tellurium (Te), selenium (Se), tin (Sn), etc., and their carrier concentration is generally 5×10 16 cm -3 3×10 17 cm -3 . Further, the thickness of the n-type GaAs layer is 0.1 μm to 0.3 μm. Next, as shown in FIG. 1b, an insulating film 3 made of silicon dioxide (SiO 2 ), silicon nitride (SiN), or the like is formed on the n-type GaAs layer 2 to a thickness of, for example, 0.2 μm. Then, a second material film 4 of, for example, aluminum (Al) is formed on the insulating film. Next, as shown in FIG. 1c, the second material film 4 is covered with a masking material 6 such as photoresist (PR), except for the gate-corresponding portion 5. Then, as shown in FIG. In Fig. 1c, the gate equivalent part 5 is formed to a thickness of 0.5 μm using an electron beam, for example.
It can be formed by exposing the mask material 6 to light through a slit having a width of . Next, Figure 1 d
As shown in FIG. 3, the gate-corresponding portion of the second material 4 is etched and removed using the mask material 6 as a mask using, for example, a 40° C. to 60° C. phosphoric acid solution, and the gate-corresponding portion of the mask material 6 is removed. A width of 5, e.g.
Wider than 0.5 μm, use side etching to remove, for example, to a width of about 0.9 μm. Next, as shown in FIG. 1e, using the mask material 6 as a mask, the mask material 6 is etched by an anisotropic etching method such as parallel electrode dry etching.
A portion of the insulating film 3 corresponding to a gate equivalent portion 5, for example, a width of 0.5 μm is removed. Next, after removing the mask material 6, as shown in FIG.
A heat-resistant metal 7 such as an alloy (10wt% Ti) is applied to the second layer by a vacuum deposition method such as a sputtering method.
material film 4, insulating film 3 and n-type GaAs layer 2
For example, it is deposited to a thickness of 0.3μ. Next, Figure 1g
As shown in FIG. 3, the second material film 4 is etched away using, for example, phosphoric acid, and at the same time, the heat-resistant metal 7 formed on the second material film 4 is removed by lift-off, and a heat-resistant metal gate 8 is formed. form. Next, the insulating film 3 is removed by an anisotropic etching method using the heat-resistant metal gate 8 as a mask, and silicon (Si), for example, is accelerated by ion implantation using the heat-resistant metal gate 8 as a mask. When the n-type GaAs layer 2 is implanted at a dose of 5×10 13 cm -2 at an energy of 200 KeV and annealed for 15 minutes at a temperature of 800°C in an arsenic atmosphere, the average activation rate is as high as 80%. A concentration carrier layer 9 is formed as shown in FIG. 1h. Next, the first
A GaAs MESFET is completed by forming a source electrode 10 and a drain electrode 11 on the high concentration carrier layer 9 as shown in FIG.
なお、上記の実施例において、第１図ａに示し
た構成、即ち半絶縁性GaAs基板上上に成長され
たｎ型GaAs層のかわりに、第２図に示すように
半絶縁性、GaAs基板上にまず高抵抗GaAs層つ
いでGaAs層を成長させた構成を有する基板を用
いてもよいし、また、ゲートパツドを形成する領
域のｎ型GaAs層を除去した構成の基板を用いて
もよい。第２図において、１は半絶縁性GaAs基
板、１２は高抵抗GaAs層、２はｎ型GaAs層で
ある。また第１図および第２図において半絶縁性
GaAs基板の代わりに高抵抗GaAs基板を用いて
も本発明の効果には変わりがない。またGaAsの
代わりにインジウムリン（InP）等の他の半導体
物質を用いても同様の効果を本発明は示す。ま
た、上記の実施例において、第１図の絶縁膜と第
２の物質膜の種類は第２の物質膜をエツチングす
るエツチング液で前記の絶縁膜がエツチングされ
ないように選択することは可能である。例えば第
２の物質膜としてAlを用い、リン酸液エツチン
グする場合には絶縁膜としてはリン酸液でエツチ
ングされるSiNではなくSiO2を用いればよい。ま
た第２の物質膜はAlの他にチタンTiクロムCrを
用いてもよい。また、第１図実施例ではAlのサ
イドエツチング後、絶縁膜をエツチングしたが、
Alおよび絶縁膜を異方性エツチングした後、第
２の物質であるAlをサイドエツチングしても良
い。 In the above embodiment, instead of the structure shown in FIG. 1a, that is, the n-type GaAs layer grown on a semi-insulating GaAs substrate, a semi-insulating GaAs substrate is used as shown in FIG. A substrate having a structure on which a high resistance GaAs layer is first grown and then a GaAs layer may be used, or a substrate having a structure in which an n-type GaAs layer in a region where a gate pad is to be formed may be removed. In FIG. 2, 1 is a semi-insulating GaAs substrate, 12 is a high resistance GaAs layer, and 2 is an n-type GaAs layer. Also, in Figures 1 and 2, semi-insulating
Even if a high-resistance GaAs substrate is used instead of the GaAs substrate, the effects of the present invention remain the same. Furthermore, the present invention exhibits similar effects even when other semiconductor materials such as indium phosphide (InP) are used instead of GaAs. Furthermore, in the above embodiment, the types of the insulating film and the second material film shown in FIG. 1 can be selected so that the insulating film is not etched by the etching solution that etches the second material film. . For example, when Al is used as the second material film and etched with phosphoric acid solution, SiO 2 may be used as the insulating film instead of SiN, which is etched with phosphoric acid solution. In addition to Al, titanium, Ti, chromium, and Cr may be used for the second material film. In addition, in the embodiment shown in FIG. 1, the insulating film was etched after the side etching of Al.
After Al and the insulating film are anisotropically etched, the second material Al may be side etched.
さらに上記の実施例においては第２の物質膜の
サイドエツチング量の制御が本発明の効果を決め
る要因の一つであるが、このサイドエツチング量
はエツチング時間により十分制御可能であり、ま
た第２の物質膜のマスク材であるPRを通して観
察、測定することもできる。また第１図ｈに示さ
れる高濃度キヤリア層９を形成するイオンはSiの
かわりにＳ，Se，Sn等のｎ型不純物になりうる
イオンを用いることができる。また高濃度キヤリ
ア層９のかわりに深さ方向に十分な厚さを持つ中
程度の濃度のキヤリア層を用いてもよい。すなわ
ち、イオン注入層の平均濃度Ｎとその深さｄとの
積Ｎ×ｄを十分に大きくすればよい。また本発明
の実施例において第１図ｇに示す工程の後、第３
図ａに示すように絶縁膜２を通してイオン注入を
行ない、例えば水素雰囲気中で800℃の温度で15
分間アニールして、イオン注入層の活性化を行な
い、次に第３図ｂに示すように通常のリングラフ
イ技術と気相または液相エツチングにより、ソー
スおよびドレイン電極領域の絶縁膜２を除去した
後、ソース電極およびドレイン電極を形成して
MESFETを実現することも可能である。また第
３図の絶縁膜を異方性エツチングにより、その厚
さを薄くした後、イオン注入を行なつてもよい。
絶縁膜を通してのイオン注入は当然ながら絶縁膜
のない場合に比べてイオンの加速エネルギーは大
きくしなければならず、また絶縁膜のないイオン
注入によるイオン注入層と同じキヤリア濃度を得
ようとするときは、よりドーズ量を増す必要があ
る。第３図において、１は半絶縁性GaAs基板、
２はｎ型GaAs層、３は絶縁膜、８は耐火性ゲー
ト金属、９はイオン注入層、１０はソース電極、
１１はドレイン電極である。 Furthermore, in the above embodiments, controlling the side etching amount of the second material film is one of the factors that determines the effect of the present invention, but this side etching amount can be sufficiently controlled by the etching time, and It can also be observed and measured through PR, which is a mask material of the material film. Furthermore, instead of Si as the ions forming the highly concentrated carrier layer 9 shown in FIG. Further, instead of the high concentration carrier layer 9, a medium concentration carrier layer having sufficient thickness in the depth direction may be used. That is, the product N×d of the average concentration N of the ion-implanted layer and its depth d may be made sufficiently large. In addition, in the embodiment of the present invention, after the step shown in FIG.
As shown in Figure a, ion implantation is performed through the insulating film 2, for example, at a temperature of 800°C in a hydrogen atmosphere at 15°C.
After annealing for 1 minute to activate the ion-implanted layer, and then removing the insulating film 2 in the source and drain electrode regions by conventional phosphory technique and vapor phase or liquid phase etching as shown in Figure 3b. , forming the source and drain electrodes.
It is also possible to realize MESFET. Alternatively, ion implantation may be performed after the insulating film shown in FIG. 3 is thinned by anisotropic etching.
Ion implantation through an insulating film naturally requires higher ion acceleration energy than when there is no insulating film, and when trying to obtain the same carrier concentration as in an ion-implanted layer without an insulating film, requires a higher dose. In Fig. 3, 1 is a semi-insulating GaAs substrate;
2 is an n-type GaAs layer, 3 is an insulating film, 8 is a refractory gate metal, 9 is an ion implantation layer, 10 is a source electrode,
11 is a drain electrode.
第１図、第３図に示す実施例におけるGaAs
MESFETの実効的なソース・ゲート間領域は第
１図、第３図に示すイオン注入層９の比抵抗を十
分に低くできるため、ソース電極１０のゲート寄
りの端と、ｎ型GaAs層２上の耐火性金属ゲート
８のソース寄りの端ではなく、ソース電極１０が
形成されイオン注入層９のゲート寄りの端とｎ型
GaAs層２上の耐火性金属ゲート８のソース寄り
の端と見なすことが可能であり、この距離は第１
図ｄに示すように第２の物質膜４のサイドエツチ
ング量により決定され、実施例においては0.2μ程
度まで精度よく再現できた。 GaAs in the embodiment shown in Figures 1 and 3
Since the specific resistance of the ion-implanted layer 9 shown in FIG. 1 and FIG. The source electrode 10 is formed not at the source-side end of the refractory metal gate 8, but at the gate-side end of the ion-implanted layer 9 and the n-type
It can be considered as the source-side edge of the refractory metal gate 8 on the GaAs layer 2, and this distance is the first
As shown in FIG. d, it is determined by the amount of side etching of the second material film 4, and in the example, it was possible to accurately reproduce it down to about 0.2μ.
第１図ａ〜ｉは本発明の一実施例を説明するた
めの図、第２図、第３図ａ，ｂは本発明の第１図
に示される以外の他の実施例を説明するための図
である。
図において、１は半絶縁性GaAs基板、２はｎ
型GaAs層、３は絶縁膜、４は第２の物質膜、５
はゲート相当部、６はマスク材、７は耐熱性金
属、８は耐熱性金属ゲート、９はイオン注入層、
１０はソース電極、１１はドレイン電極、１２は
高抵抗GaAs層である。
Figures 1 a to i are diagrams for explaining one embodiment of the present invention, and Figures 2 and 3 a and b are diagrams for explaining other embodiments of the present invention other than those shown in Figure 1. This is a diagram. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an n
type GaAs layer, 3 is an insulating film, 4 is a second material film, 5
is a gate equivalent part, 6 is a mask material, 7 is a heat-resistant metal, 8 is a heat-resistant metal gate, 9 is an ion implantation layer,
10 is a source electrode, 11 is a drain electrode, and 12 is a high resistance GaAs layer.
Claims (1)
成する工程、該絶縁膜の上に該絶縁膜と異なる第
２の物質膜を形成する工程、該第２の物質膜上に
マスク材を形成した後、該マスク材の一部を除去
してゲート相当部に開口を設ける工程、該マスク
材を利用してサイドエツチングにより前記マスク
材に設けたゲート相当部の開口よりも広く、前記
第２の物質膜を除去する工程、前記マスク材を利
用して、異方性エツチングにより前記絶縁膜の一
部を除去し前記一導電形半導体層の一部を露出さ
せる工程、マスク材を除去する工程、耐熱性金属
を被着する工程、前記第２の物質膜をエツチング
により除去してリフトオフにより耐熱性金属ゲー
トを形成する工程、前記耐熱性金属ゲートをマス
クにして、絶縁膜を通して、あるいはアンダーカ
ツトのないエツチングにより絶縁膜を薄くした
後、あるいはアンダーカツトのないエツチングに
より絶縁膜を除去した後、ドレインおよびソース
領域に低抵抗一導電形半導体を形成できるイオン
を注入しアニールする工程を含むことを特徴とす
るシヨツトキバリアゲート電界効果トランジスタ
装置の製造方法。1. A step of forming an insulating film on a substrate surface including a semiconductor layer of one conductivity type, a step of forming a second material film different from the insulating film on the insulating film, and a step of forming a mask material on the second material film. After the formation, a step of removing a part of the mask material to form an opening in the gate-equivalent part, using the mask material, side-etching the mask material to form an opening wider than the gate-equivalent part provided in the mask material; a step of removing a part of the insulating film by anisotropic etching using the mask material to expose a part of the one conductivity type semiconductor layer; and removing the mask material. a step of depositing a heat-resistant metal; a step of removing the second material film by etching and forming a heat-resistant metal gate by lift-off; After thinning the insulating film by etching without cuts or removing the insulating film by etching without undercuts, the method includes a step of implanting and annealing ions capable of forming a low-resistance single-conductivity type semiconductor in the drain and source regions. A method for manufacturing a shot barrier gate field effect transistor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4149681A JPS57155778A (en) | 1981-03-20 | 1981-03-20 | Manufacture of schottky barrier gate fet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4149681A JPS57155778A (en) | 1981-03-20 | 1981-03-20 | Manufacture of schottky barrier gate fet |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57155778A JPS57155778A (en) | 1982-09-25 |
| JPH0117271B2 true JPH0117271B2 (en) | 1989-03-29 |
Family
ID=12609957
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4149681A Granted JPS57155778A (en) | 1981-03-20 | 1981-03-20 | Manufacture of schottky barrier gate fet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57155778A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5873164A (en) * | 1981-10-27 | 1983-05-02 | Sumitomo Electric Ind Ltd | Schottky gate field effect transistor and manufacture thereof |
-
1981
- 1981-03-20 JP JP4149681A patent/JPS57155778A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57155778A (en) | 1982-09-25 |
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