JPH0116052B2 - - Google Patents
Info
- Publication number
- JPH0116052B2 JPH0116052B2 JP57133560A JP13356082A JPH0116052B2 JP H0116052 B2 JPH0116052 B2 JP H0116052B2 JP 57133560 A JP57133560 A JP 57133560A JP 13356082 A JP13356082 A JP 13356082A JP H0116052 B2 JPH0116052 B2 JP H0116052B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- input
- output
- capacitively coupled
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000003321 amplification Effects 0.000 claims description 14
- 239000003990 capacitor Substances 0.000 claims description 14
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 14
- 238000005070 sampling Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 8
- 230000003071 parasitic effect Effects 0.000 description 5
- 230000001052 transient effect Effects 0.000 description 5
- 230000008054 signal transmission Effects 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000001934 delay Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
- H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Amplifiers (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、入力信号電圧と基準電圧との差電圧
を増幅する差電圧増幅回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a voltage difference amplification circuit that amplifies a voltage difference between an input signal voltage and a reference voltage.
たとえば並列比較型Ａ／Ｄコンバータでは量子
化の境界を識別する多数の比較回路により入力信
号を同時に比較判別し、各比較回路の出力に基づ
いて適宜な符号を形成する。従来、この種のＡ／
Ｄコンバータでは、上記比較回路として演算増幅
器等の差動増幅回路を用いたものがある。しかし
ながらこのように演算増幅器を用いたものではオ
フセツト電圧、オフセツト電流によつて誤差を生
じ、また一般に高速性を要求される用途には不向
きである。
For example, in a parallel comparison type A/D converter, input signals are simultaneously compared and determined using a large number of comparison circuits that identify quantization boundaries, and an appropriate code is formed based on the output of each comparison circuit. Conventionally, this type of A/
Some D converters use a differential amplifier circuit such as an operational amplifier as the comparison circuit. However, such a device using an operational amplifier causes errors due to offset voltage and offset current, and is generally unsuitable for applications requiring high speed.
このために、特に高速Ａ／Ｄコンバータでは、
たとえば第１図に示すようなチヨツパ型コンパレ
ータが広く用いられている。すなわち、第１の入
力端子１に基準電圧Vrefを与え、第２の入力端子
２に比較すべき入力信号Vioを与える。そして第
１、第２の各入力端子１，２をクロツク信号φお
よびφの反転信号でオンオフ制御する、たとえ
ばFETアナログスイツチからなる第１、第２の
各スイツチ３，４を介して並列に接続し、コンデ
ンサ５の一端に接続する。そしてこのコンデンサ
５の他端を反転増幅器６の入力に接続するととも
に反転増幅器６の入・出力間に上記クロツク信号
φでオンオフ制御されるたとえばFETアナログ
スイツチからなる第３のスイツチ７を設けてい
る。そして反転増幅器６の出力を出力端子８を介
して出力するようにしている。 For this reason, especially in high-speed A/D converters,
For example, a chopper type comparator as shown in FIG. 1 is widely used. That is, the reference voltage V ref is applied to the first input terminal 1, and the input signal V io to be compared is applied to the second input terminal 2. The first and second input terminals 1 and 2 are connected in parallel via first and second switches 3 and 4, which are comprised of FET analog switches, for example, and which control on/off using clock signals φ and inverted signals of φ. and connect it to one end of the capacitor 5. The other end of this capacitor 5 is connected to the input of an inverting amplifier 6, and a third switch 7, for example, a FET analog switch, is provided between the input and output of the inverting amplifier 6 and is controlled on/off by the clock signal φ. . The output of the inverting amplifier 6 is outputted via an output terminal 8.
このようにすれば第２図に示す波形図のように
クロツク信号φ（第２図ａ）の“Ｈ”の期間は第
１、第３の各スイツチ３，７をオンし、第２のス
イツチ４をオフするので反転増幅器６の入・出力
間を短絡してこの入・出力端子の電圧を回路のし
きい値電圧Vthr、すなわち動作の基準となる動作
点電圧とする。一方、この場合コンデンサ５の入
力側の電極には基準電圧Vrefを印加する。そして
クロツク信号の“Ｈ”の期間は第１、第３の各
スイツチ３，７をオフし、第２のスイツチ４をオ
ンするのでコンデンサ５の入力側の電極には入力
信号Vioを印加し、反転増幅器６の入力電圧はし
きい値電圧Vthrから基準電圧と入力信号との差電
圧Vref−Vioへ変化する。そしてこのような反転
増幅器６の入力電圧の変化は反転増幅器６の増幅
率を乗じて出力端子８から出力する。したがつ
て、入力信号Vio（第２図ｂ）に対して任意の基準
電圧Vrefを設定することにより出力端子８にクロ
ツク信号に同期したパルス列からなる出力信号
（第２図ｃ）を得られる。すなわち、第１図に示
す回路構成ではクロツク信号φにより反転増幅器
６の入・出力を短絡するオートゼロモードと、入
力信号Vioと基準電圧Vrefとの差電圧を得るサン
プリングモードとを交互に繰り返すことになる。 In this way, as shown in the waveform diagram shown in FIG. 2, during the "H" period of the clock signal φ (FIG. 2a), the first and third switches 3 and 7 are turned on, and the second switch is turned on. 4 is turned off, the input and output terminals of the inverting amplifier 6 are short-circuited, and the voltage at this input and output terminal is set as the threshold voltage V thr of the circuit, that is, the operating point voltage serving as the reference for operation. On the other hand, in this case, a reference voltage V ref is applied to the input side electrode of the capacitor 5 . During the "H" period of the clock signal, the first and third switches 3 and 7 are turned off and the second switch 4 is turned on, so that the input signal V io is applied to the input side electrode of the capacitor 5. , the input voltage of the inverting amplifier 6 changes from the threshold voltage V thr to the difference voltage V ref −V io between the reference voltage and the input signal. Such a change in the input voltage of the inverting amplifier 6 is multiplied by the amplification factor of the inverting amplifier 6 and output from the output terminal 8. Therefore, by setting an arbitrary reference voltage V ref to the input signal V io (Figure 2 b), an output signal (Figure 2 c) consisting of a pulse train synchronized with the clock signal can be obtained at the output terminal 8. It will be done. That is, in the circuit configuration shown in FIG. 1, an auto-zero mode in which the input and output of the inverting amplifier 6 are short-circuited by the clock signal φ and a sampling mode in which the difference voltage between the input signal V io and the reference voltage V ref is obtained are alternately repeated. It turns out.
しかしながらこのようなチヨツパ型コンパレー
タは所謂サンプリング系として動作するので入力
信号Vioの周波数はクロツク信号φの周波数の1/2
よりも低くないと、正確に入力信号Vioの変化を
得ることはできない。また、特に高速サンプリン
グを行なう場合は、スイツチのオン期間が短くな
るために寄生容量、スイツチのオン抵抗等が原因
で種々の問題を生じる。すなわちスイツチのオン
抵抗および寄生容量によつて信号の伝達おくれあ
るいはゲインロスを生じる。またこのようなスイ
ツチの信号の入・出力端子とクロツク信号φを入
力する制御端子との間の寄生容量によつて、クロ
ツク成分が信号に重畳されてヒゲ状のパルス信号
を生じる。そしてこの現象は動的には系が定常状
態に戻るまでに時間がかかり、高速動作に支障を
来たし、静的には出力にオフセツトを生じること
になる。
However, since such a chopper type comparator operates as a so-called sampling system, the frequency of the input signal V io is 1/2 of the frequency of the clock signal φ.
Unless it is lower than , it is not possible to accurately obtain changes in the input signal Vio . Furthermore, especially when performing high-speed sampling, the on-period of the switch becomes short, causing various problems due to parasitic capacitance, on-resistance of the switch, and the like. That is, the on-resistance and parasitic capacitance of the switch cause signal transmission delays or gain loss. Furthermore, due to the parasitic capacitance between the signal input/output terminal of such a switch and the control terminal to which the clock signal φ is input, a clock component is superimposed on the signal, producing a whisker-like pulse signal. Dynamically, this phenomenon takes time for the system to return to a steady state, which hinders high-speed operation, and statically, it causes an offset in the output.
本発明は上記の事情に鑑みてなされたもので、
連続的な動作を行なえ高い周波数の入力信号に対
しても高速サンプリングを行なうことなく入力信
号と基準電圧との差電圧を得ることができる差電
圧増幅回路を提供することを目的とするものであ
る。
The present invention was made in view of the above circumstances, and
The object of the present invention is to provide a differential voltage amplifier circuit that can operate continuously and obtain a differential voltage between an input signal and a reference voltage even for high-frequency input signals without performing high-speed sampling. .
すなわち本発明は２組のチヨツパ型コンパレー
タを並列に設けて交互に動作させることにより等
価的に連続的な比較結果を得ることを特徴とする
ものである。
That is, the present invention is characterized in that equivalently continuous comparison results are obtained by providing two sets of chopper type comparators in parallel and operating them alternately.
以下本発明の一実施例を第３図に示すブロツク
図を参照して詳細に説明する。第３図において、
第１の入力端子１１に基準電圧Vrefを与え、第２
の入力端子１２に比較すべき入力信号Vioを与え
る。そして、第１の入力端子１１を第１、第３の
スイツチ１３，１５を介してそれぞれコンデンサ
１７，１８の一方の端子に接続している。また第
２の入力端子１２を第２、第４のスイツチ１４，
１６を介してそれぞれ上記コンデンサ１７，１８
の一方の端子に並列に接続している。さらに上記
コンデンサ１７，１８の他方の端子を増幅手段、
すなわち第１、第２の反転増幅器１９，２０の各
入力に接続している。そして第１、第２の反転増
幅器１９，２０の入・出力間にそれぞれ第５、第
６のスイツチ２１，２２を介挿して動作点電圧発
生手段を構成するとともに出力を出力選択手段、
すなわち第７、第８のスイツチ２３，２４を介し
て並列に出力端子２５に接続している。そして上
記第１乃至第８のスイツチ１３，１４，１５，１
６，２１，２２，２３，２４はたとえばFETア
ナログスイツチで第１、第５のスイツチ１３，２
１はクロツク信号φ1で制御し、第２のスイツチ
１４はクロツク信号φ1の反転信号1によつて制
御する。そして第３、第６のスイツチ１５，２２
はクロツク信号φ2で制御し、第４のスイツチ１
６はクロツク信号φ2の反転信号2によつて制御
する。さらに第７のスイツチ２３はクロツク信号
φ12で制御し、第８のスイツチ２４はクロツク信
号φ12の反転信号12によつて制御する。
Hereinafter, one embodiment of the present invention will be described in detail with reference to the block diagram shown in FIG. In Figure 3,
A reference voltage V ref is applied to the first input terminal 11, and the second
An input signal V io to be compared is applied to the input terminal 12 of . The first input terminal 11 is connected to one terminal of capacitors 17 and 18 via first and third switches 13 and 15, respectively. Further, the second input terminal 12 is connected to the second and fourth switches 14,
16 to the capacitors 17 and 18, respectively.
are connected in parallel to one terminal of the Further, the other terminals of the capacitors 17 and 18 are connected to an amplifying means,
That is, it is connected to each input of the first and second inverting amplifiers 19 and 20. Fifth and sixth switches 21 and 22 are respectively inserted between the input and output of the first and second inverting amplifiers 19 and 20 to constitute operating point voltage generation means and output selection means,
That is, they are connected to the output terminal 25 in parallel via the seventh and eighth switches 23 and 24. And the first to eighth switches 13, 14, 15, 1
6, 21, 22, 23, 24 are FET analog switches, for example, and the first and fifth switches 13, 2
1 is controlled by the clock signal φ 1 , and the second switch 14 is controlled by the inverted signal 1 of the clock signal φ 1 . and third and sixth switches 15, 22
is controlled by the clock signal φ2 , and the fourth switch 1
6 is controlled by the inverted signal 2 of the clock signal φ2 . Further, the seventh switch 23 is controlled by the clock signal φ12 , and the eighth switch 24 is controlled by the inverted signal 12 of the clock signal φ12 .
そして、第１、第２のスイツチ１３，１４およ
びコンデンサ１７によつて第１の印加電圧設定手
段を構成し、同様に第３、第４のスイツチ１５，
１６およびコンデンサ１８によつて第２の印加電
圧設定手段を構成する。そして、各印加電圧設定
手段により動作点電圧、あるいはこの動作点電圧
に上記各入力端子１１，１２へ与えられる電圧の
差電圧を重畳した差信号電圧を得るようにしてい
る。 The first and second switches 13 and 14 and the capacitor 17 constitute a first applied voltage setting means, and similarly the third and fourth switches 15 and 17 constitute a first applied voltage setting means.
16 and capacitor 18 constitute a second applied voltage setting means. Then, each applied voltage setting means obtains an operating point voltage, or a difference signal voltage obtained by superimposing the operating point voltage with the difference voltage between the voltages applied to each of the input terminals 11 and 12.
しかして、第１、第２、第５のスイツチ１３，
１４，２１およびコンデンサ１７、反転増幅器１
９によつて容量結合型増幅手段を有する第１のチ
ヨツパ型コンパレータ１０１を構成している。ま
た第３、第４、第６のスイツチ１５，１６，２２
およびコンデンサ１８、反転増幅器２０によつて
同様に容量結合型増幅手段を有する第２のチヨツ
パ型コンパレータ１０２を構成している。そして
上記第１、第２のチヨツパ型コンパレータ１０
１，１０２は交互にかつ180゜の位相差で反転増幅
器１９，２０の入・出力を短絡するオートゼロ動
作と入力信号Vioをサンプリングするサンプリン
グ動作とを繰り返す。 Therefore, the first, second, and fifth switches 13,
14, 21 and capacitor 17, inverting amplifier 1
9 constitutes a first chopper comparator 101 having capacitively coupled amplification means. In addition, the third, fourth, and sixth switches 15, 16, 22
The capacitor 18 and the inverting amplifier 20 constitute a second chopper comparator 102 which similarly has capacitively coupled amplification means. and the first and second chopper type comparators 10.
1 and 102 alternately and with a phase difference of 180° repeat the auto-zero operation of shorting the inputs and outputs of the inverting amplifiers 19 and 20 and the sampling operation of sampling the input signal Vio .
なお各スイツチはクロツク信号φが“Ｈ”のと
きオンし、“Ｌ”のときオフするものとして説明
する。 Each switch will be described assuming that it is turned on when the clock signal φ is "H" and turned off when it is "L".
このような構成であれば、たとえばクロツク信
号φ1（第４図ａ）が“Ｈ”のT1〜T2のとき第１の
チヨツパ型コンパレータ１０１は第１、第５のス
イツチ１３，２１がオンし、第２のスイツチ１４
をオフして反転増幅器１９の入・出力の電位を動
作点電圧とするオートゼロ動作を行なう。一方、
この期間およびその前後でクロツク信号φ2（第４
図ｂ）は“Ｌ”であり、第２のチヨツパ型コンパ
レータ１０２は第３、第６のスイツチ１５，２２
をオフし、第４のスイツチ１６をオンして入力信
号Vio（第４図ｃ）のサンプリング動作を行ない上
記入力信号Vioと基準電圧Vrefの差電圧を反転増
幅器２０へ入力する。したがつてこの期間中第１
のチヨツパ型コンパレータ１０１の出力（第４図
ｅ）は反転増幅器１９のしきい値電圧Vthrとな
り、また第２のチヨツパ型コンパレータ１０２の
出力（第４図ｆ）は入力信号Vioと基準電圧Vref
との比較結果となる。そしてこの期間中はクロツ
ク信号φ12は“Ｌ”で第７のスイツチ２３はオフ、
第８のスイツチ２４はオンし、第２のチヨツパ型
コンパレータ１０２の出力信号を出力端子２５か
ら出力する。 With such a configuration, for example, when the clock signal φ 1 (FIG. 4a) is “H” at T 1 to T 2 , the first chopper type comparator 101 switches the first and fifth switches 13 and 21. turn on and turn on the second switch 14.
is turned off to perform an auto-zero operation in which the input and output potentials of the inverting amplifier 19 are set to the operating point voltage. on the other hand,
During and before and after this period, the clock signal φ 2 (fourth
Figure b) is "L", and the second chopper type comparator 102 is connected to the third and sixth switches 15, 22.
is turned off, and the fourth switch 16 is turned on to perform a sampling operation of the input signal V io (FIG. 4c), and input the difference voltage between the input signal V io and the reference voltage V ref to the inverting amplifier 20 . Therefore, during this period, the first
The output of the second chopper type comparator 101 (Fig. 4 e) becomes the threshold voltage V thr of the inverting amplifier 19, and the output of the second chopper type comparator 102 (Fig. 4 f) is the input signal V io and the reference voltage. V ref
This is the comparison result. During this period, the clock signal φ12 is "L" and the seventh switch 23 is off.
The eighth switch 24 is turned on and outputs the output signal of the second chopper type comparator 102 from the output terminal 25.
そして時刻T2でクロツク信号φが“Ｌ”にな
ると、第１のチヨツパ型コンパレータ１０１の第
１、第５のスイツチ１３，２１はオフし、第２の
スイツチ１４はオンして入力信号Vioのサンプリ
ング動作を行なう。しかしながらこの場合、サン
プリング動作の開始直後、すなわち第２のスイツ
チ１４のオン直後からしばらくの間はスイツチ等
の寄生容量によるクロツク漏れ、スイツチのオン
抵抗による入力信号の伝達遅れ等の過渡現象のた
めに第１のチヨツパ型コンパレータ１０１の出力
は第４図ｄ図示破線で示すように正常値にならな
いことがある。したがつて、上記過渡現象が安定
する期間t1を設け、この期間t1を経過後時刻t3で
クロツク信号φ12を反転させ、第７のスイツチ２
３をオン、第８のスイツチ２４をオフし第１のチ
ヨツパ型コンパレータ１０１の比較結果信号を出
力端子２５から出力する。 Then, when the clock signal φ becomes "L" at time T2 , the first and fifth switches 13 and 21 of the first chopper type comparator 101 are turned off, and the second switch 14 is turned on, and the input signal V io Perform sampling operation. However, in this case, immediately after the sampling operation starts, that is, immediately after the second switch 14 is turned on, transient phenomena such as clock leakage due to parasitic capacitance of the switch, input signal transmission delay due to the on-resistance of the switch, etc. The output of the first chopper type comparator 101 may not reach a normal value as shown by the broken line in FIG. 4d. Therefore, a period t 1 is provided during which the above-mentioned transient phenomenon is stabilized, and after this period t 1 has elapsed, the clock signal φ 12 is inverted at time t 3 and the seventh switch 2 is inverted.
3 is turned on, the eighth switch 24 is turned off, and the comparison result signal of the first chopper type comparator 101 is outputted from the output terminal 25.
さらにこの後、時刻T4でクロツク信号φ2を反
転し第２のチヨツパ型コンパレータ１０２の第
３、第６のスイツチ１５，２２をオンし、第４の
スイツチ１６をオフして、オートゼロ動作を行な
う。なおこの場合、第１のチヨツパ型コンパレー
タ１０１の状態は不変でサンプリング動作を継続
し、その比較結果信号を出力する。そして以後時
刻T5，T6…で上述の時刻T1，T2…の動作を第２
のチヨツパ型コンパレータ１０２で行ない、オー
トゼロ動作およびサンプリング動作を第１、第２
のチヨツパ型コンパレータ１０１，１０２で交互
に繰り返すことになる。 Furthermore, at time T4 , the clock signal φ2 is inverted, the third and sixth switches 15 and 22 of the second chopper type comparator 102 are turned on, and the fourth switch 16 is turned off, thereby starting the auto-zero operation. Let's do it. In this case, the state of the first chopper type comparator 101 remains unchanged, continues the sampling operation, and outputs the comparison result signal. Thereafter, at times T 5 , T 6 . . . , the operations at times T 1 , T 2 .
The chipper type comparator 102 performs auto-zero operation and sampling operation on the first and second
This is alternately repeated by the chopper type comparators 101 and 102.
したがつて基準電圧Vrefと入力信号Vioとの比
較結果を連続的に得ることができる。 Therefore, the comparison results between the reference voltage V ref and the input signal V io can be continuously obtained.
なお、本発明は上記実施例に限定されるもので
はなく、たとえばサンプリング動作の開始時に過
渡現象による異常出力を生じないとき、あるいは
これを無視できる場合には、第１、第２のチヨツ
パ型コンパレータ１０１，１０２のサンプリング
期間を重なるようにしなくてもよい。したがつ
て、このような場合には、出力側の第７、第８の
スイツチ２３，２４を制御するクロツク信号φ12
あるいはこの反転信号12をクロツク信号φ2，φ1
として用いればよい。 Note that the present invention is not limited to the above-mentioned embodiments. For example, when an abnormal output due to a transient phenomenon does not occur at the start of a sampling operation, or when this can be ignored, the first and second chopper type comparators may be used. The sampling periods 101 and 102 do not have to overlap. Therefore, in such a case, the clock signal φ 12 that controls the seventh and eighth switches 23 and 24 on the output side
Alternatively, this inverted signal 12 can be used as clock signals φ 2 and φ 1
It can be used as
また、オートゼロ動作のために反転増幅器１
９，２０へしきい値電圧を与える場合、たとえば
第５図に示すようにしてもよい。すなわち第５図
は第１のチヨツパ型コンパレータ１０１だけを示
すブロツク図で反転増幅器１９と同一特性の反転
増幅器２６の入・出力間を短絡してクロツク信号
φ1によつて制御するスイツチ２７を介して反転
増幅器１９の入力へ与えればよい。このようにす
ればスイツチ２７のオンと同時に反転増幅器１９
の入力へしきい値電圧を与えることができるので
所謂オートゼロ動作を短時間で行なえ、それによ
つて全体のサンプリング周期を短縮でき反転増幅
器１９にかえて同一特性の非反転増幅器を用いて
もよい。 Additionally, an inverting amplifier 1 is used for auto-zero operation.
When applying threshold voltages to the circuits 9 and 20, it may be done as shown in FIG. 5, for example. That is, FIG. 5 is a block diagram showing only the first chopper type comparator 101, in which the input and output of an inverting amplifier 26 having the same characteristics as the inverting amplifier 19 are short-circuited via a switch 27 controlled by the clock signal φ1 . It is sufficient to apply the signal to the input of the inverting amplifier 19. By doing this, the inverting amplifier 19 is turned on at the same time as the switch 27 is turned on.
Since a threshold voltage can be applied to the input of the inverting amplifier 19, a so-called auto-zero operation can be performed in a short time, thereby shortening the overall sampling period, and a non-inverting amplifier with the same characteristics may be used in place of the inverting amplifier 19.
さらにチヨツパ型コンパレータは、たとえば第
６図に示すようにコンデンサC1，C2…Coおよび
反転増幅器Iv1，Iv2…Ivoを交互に複数組縦続し、
かつ各反転増幅器Iv1，Iv2…Ivoの入・出力間にオ
ートゼロ動作時にオンするスイツチS1，S2…Soを
介挿するようにしてもよい。 Further, a chopper type comparator is constructed by alternately cascading multiple sets of capacitors C 1 , C 2 . . . C o and inverting amplifiers I v1 , I v2 .
In addition, switches S 1 , S 2 , . . . S o , which are turned on during auto-zero operation, may be inserted between the input and output of each inverting amplifier I v1 , I v2 , . . . I vo .
また第７図に示すブロツク図のように反転増幅
器Iv1を用いたチヨツパ型コンパレータの後段に
動作点電圧のほぼ等しい複数の反転増幅器Iv2，
…，Ivoを縦続に接続してもよい。 Furthermore, as shown in the block diagram shown in Fig. 7, a plurality of inverting amplifiers I v2 with approximately equal operating point voltages are installed after the chopper type comparator using the inverting amplifier I v1 .
..., I vo may be connected in cascade.
なお上記反転増幅器の具体例としては第８図ａ
に示すようにＰチヤンネルFETとＮチヤンネル
FETを組み合せたＣ―MOS型のもの、同図ｂに
示すように負荷MOSFETを飽和領域で動作させ
るもの、同図ｃに示すようにデイプレツシヨンモ
ードのFETを用いるもの同図ｄに示すように線
形抵抗ｒとFETとを組み合せたもの等を適宜に
用いることができる。 A specific example of the above-mentioned inverting amplifier is shown in Fig. 8a.
P channel FET and N channel as shown in
A C-MOS type that combines FETs, a type that operates the load MOSFET in the saturation region as shown in figure b, and a type that uses a depletion mode FET as shown in figure c, and a type shown in figure d. A combination of a linear resistor r and a FET can be used as appropriate.
さらにスイツチの具体的な回路としては第９図
ａ，ｂに示すように単一のＮチヤンネルあるいは
ＰチヤンネルのFETを用いるもの、同図ｃに示
すように一対のＮチヤンネルおよびＰチヤンネル
のFETを組み合せた所謂トランスミツシヨンゲ
ート、同図ｄに示すようにＮチヤンネルFETの
基板に電源電圧VDD，VSSの中間の電圧VBを印加
し、ＰチヤンネルFETの基板に電源電圧VDDを印
加したトランスミツシヨンゲートの変形等を用い
ることができる。 Furthermore, specific switch circuits include those that use a single N-channel or P-channel FET as shown in Figure 9a and b, and a pair of N-channel and P-channel FETs as shown in Figure 9c. In the combined so-called transmission gate, as shown in Figure d, a voltage V B between the power supply voltages V DD and V SS is applied to the substrate of the N-channel FET, and a power supply voltage V DD is applied to the substrate of the P-channel FET. A modification of the transmission gate, etc., can be used.
以上のように本発明によれば入力信号と基準電
圧の比較結果を連続的に出力することができるの
で入力信号の周波数は比較回路のクロツク周波数
の1/2以下に制限されず、入力信号の周波数がよ
り高い場合にも比較結果を得ることができる。ま
た寄生容量によるクロツク漏れ、スイツチのオン
抵抗による入力信号の伝達遅れ等の過渡現象に対
してこの過渡現象による異常出力が消勢した後に
比較結果を出力し、影響を受けないようにでき
る。
As described above, according to the present invention, the comparison result between the input signal and the reference voltage can be output continuously, so the frequency of the input signal is not limited to 1/2 or less of the clock frequency of the comparison circuit, and the frequency of the input signal is not limited to 1/2 or less of the clock frequency of the comparison circuit. Comparison results can also be obtained for higher frequencies. Furthermore, it is possible to output the comparison result after the abnormal output due to the transient phenomenon is extinguished with respect to transient phenomena such as clock leakage due to parasitic capacitance and input signal transmission delay due to the on-resistance of the switch, so that the comparison result is not affected.
第１図は従来のチヨツパ型コンパレータの一例
を示すブロツク図、第２図は第１図に示すチヨツ
パ型コンパレータの動作を説明する波形図、第３
図は本発明の一実施例を示すブロツク図、第４図
は第３図に示す実施例の動作を示す波形図、第５
図乃至第７図は本発明のチヨツパ型コンパレータ
の各別の他の実施例を示す図、第８図ａ〜ｄは反
転増幅器の各別の一例を示す図、第９図ａ〜ｄは
スイツチの各別の一例を示す図である。
１１……第１の入力端子（Vref）、１２……第
２の入力端子（Vio）、１３，１４，１５，１６，
２１，２２，２３，２４……スイツチ、１７，１
８……コンデンサ、２５……出力端子、１０１，
１０２……チヨツパ型コンパレータ。
FIG. 1 is a block diagram showing an example of a conventional chopper type comparator, FIG. 2 is a waveform diagram explaining the operation of the chopper type comparator shown in FIG. 1, and FIG.
The figure is a block diagram showing one embodiment of the present invention, FIG. 4 is a waveform diagram showing the operation of the embodiment shown in FIG. 3, and FIG.
7 to 7 show different embodiments of the chopper type comparator of the present invention, FIGS. 8 a to d show different examples of the inverting amplifier, and FIGS. 9 a to d show the switch. It is a figure which shows an example of each different. 11...First input terminal ( Vref ), 12...Second input terminal ( Vio ), 13, 14, 15, 16,
21, 22, 23, 24...Switch, 17, 1
8... Capacitor, 25... Output terminal, 101,
102...Chiyotupa type comparator.
Claims (1)
１、第２の容量結合形増幅手段と、基準電圧信号
と入力電圧信号を交互に選択して上記第１、第２
の容量結合形増幅手段にそれぞれ伝達印加する第
１、第２の入力選択手段と、上記第１、第２の容
量結合形増幅手段の増幅出力信号を選択する出力
選択手段とを具備し、上記第１と第２の容量結合
形増幅手段はそれぞれ時間的に区別される動作点
電圧を自己設定するオートゼロ期間と入力電圧を
増幅する信号増幅期間とを有し上記第１と第２の
容量結合形増幅手段のそれぞれのオートゼロ期間
は時間的に重なることはなく、上記第１と第２の
入力選択手段は第１と第２の容量結合形増幅手段
のそれぞれのオートゼロ期間に対応して基準電圧
信号を選択し、信号増幅期間に対応して入力電圧
信号を選択し、上記出力選択手段は上記第１と第
２の容量結合形増幅手段でオートゼロ期間が終了
しそれぞれの信号増幅動作が定常状態に達した時
点のそれぞれの増幅出力信号を選択し出力するこ
とによつて上記基準電圧信号と入力電圧信号の差
電圧信号を時間的に連続して増幅出力するように
構成されていることを特徴とする差電圧増幅回
路。 ２ 前記第１、第２の容量結合形増幅手段のそれ
ぞれがMOS形素子を用いて構成されている特許
請求の範囲第１項に記載の差電圧増幅回路。 ３ 前記第１、第２の容量結合形増幅手段のそれ
ぞれが反転増幅器からなりそれぞれの入出力間に
接続されたスイツチ素子により動作点電圧発生手
段が構成されている特許請求の範囲第２項に記載
の差電圧増幅回路。[Scope of Claims] 1. First and second capacitively coupled amplifying means that receive an input voltage signal through a capacitor and amplify and output the signal, and alternately select a reference voltage signal and an input voltage signal to
the first and second input selection means for respectively transmitting and applying signals to the capacitively coupled amplifying means; and the output selecting means for selecting the amplified output signals of the first and second capacitively coupled amplifying means; The first and second capacitively coupled amplifying means each have an auto-zero period for self-setting a temporally distinct operating point voltage and a signal amplifying period for amplifying the input voltage. The respective auto-zero periods of the capacitively coupled amplifying means do not overlap in time, and the first and second input selecting means select the reference voltage corresponding to the respective auto-zero periods of the first and second capacitively coupled amplifying means. the output selection means selects the input voltage signal corresponding to the signal amplification period, and the output selection means selects the signal amplification operation in the first and second capacitively coupled amplification means when the auto-zero period ends and each signal amplification operation is in a steady state. The voltage difference signal between the reference voltage signal and the input voltage signal is temporally continuously amplified and output by selecting and outputting each amplified output signal at the time when A differential voltage amplification circuit. 2. The differential voltage amplification circuit according to claim 1, wherein each of the first and second capacitively coupled amplification means is constructed using a MOS type element. 3. According to claim 2, each of the first and second capacitively coupled amplification means is an inverting amplifier, and the operating point voltage generation means is constituted by a switch element connected between the input and output of each of the first and second capacitively coupled amplification means. The differential voltage amplification circuit described.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57133560A JPS5923907A (en) | 1982-07-30 | 1982-07-30 | Differential voltage amplifying circuit |
| DE8383107285T DE3369615D1 (en) | 1982-07-30 | 1983-07-25 | Differential voltage amplifier |
| EP83107285A EP0101571B1 (en) | 1982-07-30 | 1983-07-25 | Differential voltage amplifier |
| US06/518,443 US4539551A (en) | 1982-07-30 | 1983-07-29 | Differential voltage amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57133560A JPS5923907A (en) | 1982-07-30 | 1982-07-30 | Differential voltage amplifying circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5923907A JPS5923907A (en) | 1984-02-07 |
| JPH0116052B2 true JPH0116052B2 (en) | 1989-03-22 |
Family
ID=15107654
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57133560A Granted JPS5923907A (en) | 1982-07-30 | 1982-07-30 | Differential voltage amplifying circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5923907A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5487152A (en) * | 1977-12-19 | 1979-07-11 | Intersil Inc | Active analog processing system |
| JPS55135418A (en) * | 1979-04-10 | 1980-10-22 | Sharp Corp | Comparator circuit |
| JPS56141617A (en) * | 1980-04-08 | 1981-11-05 | Mitsubishi Electric Corp | Comparator circuit |
-
1982
- 1982-07-30 JP JP57133560A patent/JPS5923907A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5487152A (en) * | 1977-12-19 | 1979-07-11 | Intersil Inc | Active analog processing system |
| JPS55135418A (en) * | 1979-04-10 | 1980-10-22 | Sharp Corp | Comparator circuit |
| JPS56141617A (en) * | 1980-04-08 | 1981-11-05 | Mitsubishi Electric Corp | Comparator circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5923907A (en) | 1984-02-07 |
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