JPH01160038A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01160038A JPH01160038A JP31986187A JP31986187A JPH01160038A JP H01160038 A JPH01160038 A JP H01160038A JP 31986187 A JP31986187 A JP 31986187A JP 31986187 A JP31986187 A JP 31986187A JP H01160038 A JPH01160038 A JP H01160038A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- polysilicon
- etching
- film
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 13
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 28
- 229920005591 polysilicon Polymers 0.000 abstract description 28
- 239000012535 impurity Substances 0.000 abstract description 8
- 238000001039 wet etching Methods 0.000 abstract description 7
- 230000003647 oxidation Effects 0.000 abstract description 6
- 238000007254 oxidation reaction Methods 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 10
- 239000013078 crystal Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000012792 core layer Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 241001122767 Theaceae Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000779 smoke Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に目己整合技
術による微細コンタクト形成に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to forming fine contacts using a self-alignment technique.
従来、この（事のコンタクト形成方法は、第３図（ａｌ
〜ｔｅａのようになっ°Ｃいた。すなわち、半導体基板
２１を酸化して酸化膜２２を形成する。その上部にボロ
ンドープされたポリシリコン２３全形成し、これを選択
的にエツチングした後このポリシリコン２３が露出しな
いように窒化膜２４で覆い。Conventionally, this method of forming a contact is shown in FIG.
It was like ~tea °C. That is, the semiconductor substrate 21 is oxidized to form the oxide film 22. A boron-doped polysilicon 23 is entirely formed on top of the polysilicon 23, which is selectively etched, and then covered with a nitride film 24 so that the polysilicon 23 is not exposed.
酸化膜２２上にポリシリコン２３と窒化膜２４の開孔部
を選択的に形成する（第３図（ａ））。ウェットエツチ
ングにより半導体基板２１上の酸化膜２２をポリシリコ
ン２３の下部の一部までも除去するようにサイドエツチ
ングする（第３図（ｂ））。その後、全面に不純物を含
まないポリシリコン２５ケ形成し、ボロンドープされた
ポリシリコン２３から不純物？含まないポリシリコン２
５ヘボロンを熱拡散する（第３図（Ｃ１）。ヒドラジン
による選択エツチングによって不純物を含まないボリシ
リコン２５を除去する。この時、酸化膜２２がサイドエ
ッチされた部分にポリシリコン２５が残る（第３図（ｄ
Ｊ）。しかる後、基板全熱酸化し、絶！＃膜２６を形成
する（第３図（ｅ））。かかる従来例においては、第３
図（ｄＪと（ｅｌの工程においてヒドラジンによるウェ
ットエツチングの際に、半導体基板２１のエツチングス
ピードが不純物を含まないポリシリコン２５のエツチン
グスピードより十分小さくなるように（１１１）基板を
使用している。しかる後酸化膜２６をエツチングして半
導体基板２１を露出し、金属電極を取り付けていた。Openings in polysilicon 23 and nitride film 24 are selectively formed on oxide film 22 (FIG. 3(a)). The oxide film 22 on the semiconductor substrate 21 is side-etched by wet etching so as to remove even a part of the lower part of the polysilicon 23 (FIG. 3(b)). After that, 25 pieces of polysilicon containing no impurities are formed on the entire surface, and impurities are added from the polysilicon 23 doped with boron. Contains no polysilicon 2
Polysilicon 25 containing no impurities is removed by selective etching with hydrazine. At this time, polysilicon 25 remains in the area where oxide film 22 is side-etched (Fig. 3 (C1)). Figure 3 (d
J). After that, the board is completely oxidized and is completely destroyed! A # film 26 is formed (FIG. 3(e)). In such a conventional example, the third
During the wet etching with hydrazine in the steps of FIGS. Thereafter, the oxide film 26 was etched to expose the semiconductor substrate 21, and metal electrodes were attached.
上述した従来のコンタクト形成方法は、不純物金言まな
いポリシリコン２５をヒドラジンによるウェットエツチ
ングにより除去する工程において、ヒドラジンが原液の
ままエツチングを行ったのでは斑点状の残りが生じる。In the conventional contact forming method described above, in the step of removing the impurity-free polysilicon 25 by wet etching with hydrazine, if the etching is performed with the undiluted hydrazine solution, a spot-like residue will be produced.
また、アルコールにより希釈してエツチングを行えば、
斑点状の残りは生じないが、アルコールの蒸発によりウ
ェットエツチングスピードが変化し、終点が定まらない
。Also, if you dilute it with alcohol and perform etching,
Although no spot-like residue is produced, the wet etching speed changes due to the evaporation of the alcohol, and the end point is not determined.
また、半導体基板の＜１１１＞表面は他の結晶軸表面を
もつ半導体基板と比べ結晶の欠陥密度が高く、半導体素
子の形成において歩留りの低下を招いている。また、（
１１１＞表面は、界面準位が高いので、バイポーラトラ
ンジスタとＭＯＳトランジスタの混在を考えた場合、Ｍ
ＯＳトランジスタの電流制御が困難になるという欠点が
ある。Furthermore, the <111> surface of a semiconductor substrate has a higher density of crystal defects than semiconductor substrates having other crystal axis surfaces, leading to a decrease in yield in the formation of semiconductor elements. Also,(
111> Since the surface has a high interface state, when considering the coexistence of bipolar transistors and MOS transistors, M
There is a drawback that current control of the OS transistor becomes difficult.
本発明のコンタクト形成方法は、半導体基板上に将来電
極になる導電膜全形成する工程と、前記基板全酸化する
工程と、前記基板上の全面に酸化膜全形成し該酸化膜全
異方性エツチングにより前記導電膜の側壁に残るように
形成する工程と、前記基板上の全面に酸化膜の除去に耐
えられる換金形成し核層を異方性エツチングにより前記
側壁の酸化膜が除去できる厚さとなるように形成する工
程と、前記仰１壁の酸化膜を除去し、かつ前記側壁の酸
化膜の下部酸化膜′に除去する工程と、前記酸化膜の除
去に耐えられる膜を除去する工程を有する。The contact forming method of the present invention includes a step of completely forming a conductive film that will become an electrode in the future on a semiconductor substrate, a step of completely oxidizing the substrate, and a step of completely forming an oxide film on the entire surface of the substrate and making the oxide film completely anisotropic. A step of forming the conductive film so as to remain on the side wall of the conductive film by etching, and forming a core layer on the entire surface of the substrate to a thickness that can withstand the removal of the oxide film, and anisotropically etching the core layer to a thickness that allows the oxide film on the side wall to be removed. a step of removing the oxide film on the first wall, a step of removing the oxide film below the oxide film of the side wall, and a step of removing a film that can withstand the removal of the oxide film. have
次に、不発明について図面全参照して説明する。 Next, the invention will be explained with reference to all the drawings.
第１図（ａｌ〜＋ｋ）は本発明の一実施例の製造工程を
示す図である。半導体基板１上に２５００Ａ程度の熱酸
化膜２全形成し、その上に３５００Ａ程度のポリシリコ
ン３を形成し、ポリシリコン３へ不純物（例えばボロン
）を導入（例えばイオン注入少し、さらに４０００Ａ程
度のＣＶＤ＆化膜４全形成し例えば１０００℃２０分で
スチーム処理をして焼きしめ、ＰＲ工工程へて選択的に
開孔部を形成する（同図（ａ））。次に基板１全酸化し
て酸化膜５全形成する（同図（ｂ））。ＣＶＤ酸化膜６
′ｋ例えハフｏｏ。FIG. 1 (al to +k) is a diagram showing the manufacturing process of an embodiment of the present invention. A thermal oxide film 2 of approximately 2,500 A is formed on the semiconductor substrate 1, a polysilicon 3 of approximately 3,500 A is formed on it, and an impurity (for example, boron) is introduced into the polysilicon 3 (for example, a small amount of ion implantation is performed, and then a thermal oxide film of approximately 4,000 A is formed on the semiconductor substrate 1. After the entire CVD & chemical film 4 is formed, it is baked by steam treatment at 1000° C. for 20 minutes, and openings are selectively formed in the PR process (see figure (a)).Next, the substrate 1 is completely oxidized. The entire oxide film 5 is formed (FIG. (b)).CVD oxide film 6
'k analogy huffoo.
へ程度成長（同図（Ｃ１）Ｌ、異方性エツチングにてエ
ツチングバックして側壁に酸化ｉ７’に残す（同図（ｄ
））。全面に例えばレジスト８を塗布する（同図（ｅＪ
）。異方性エツチングにてレジスト８をエツチングする
（同図（ｆ））。ウェットエツチングにより酸化膜７か
ら酸化膜５ヘエッチング金行う（同図（ｇ））。レジス
ト８を除去する（同図（ｈ））。ポリシリコン１（ｌ全
面に成長する（同図（ｉ］）。異方性エッチングにてエ
ツチングバックする（同図（ｊυ。(Figure (C1) L) etched back by anisotropic etching to leave oxidized i7' on the side wall (Figure (d)
)). For example, resist 8 is applied to the entire surface (see figure (eJ
). The resist 8 is etched by anisotropic etching (FIG. 8(f)). Etching is carried out from the oxide film 7 to the oxide film 5 by wet etching (FIG. 3(g)). The resist 8 is removed ((h) in the same figure). Polysilicon 1 (l grows on the entire surface (I) in the same figure). It is etched back by anisotropic etching (Jυ in the same figure).
熱酸化して絶縁膜１１をポリシリコン１０上に作る（同
図（ｋ））。その後、酸化膜５を除去して半導体基板を
露出し、電極金属全被着してコンタクト全形成する。An insulating film 11 is formed on the polysilicon 10 by thermal oxidation (FIG. 4(k)). Thereafter, the oxide film 5 is removed to expose the semiconductor substrate, and all electrode metals are deposited to form all contacts.
第２図ｆａｔ〜（ｋ＋は本発明の他の実施例の製造工程
を示す図である。半導体基板１２ ｋ ２５００Ａ程度
に熱酸化し、３５００Ａ程度のポリシリコン１４を形成
し、不純物の導入を行い、ＰＲ工程をへて選択的に開孔
部を形成する（同図（ａ））。熱酸化して酸化膜１５を
形成する（同図（ｂ））。ＣＶＤ酸化膜１６を例えば７
０００Ａ程度成長する（同図（Ｃ））。FIG. 2 fat~(k+ is a diagram showing the manufacturing process of another embodiment of the present invention. Semiconductor substrate 12 k is thermally oxidized to about 2500A, polysilicon 14 of about 3500A is formed, and impurities are introduced. , selectively form openings through a PR process ((a) in the same figure). Form an oxide film 15 by thermal oxidation ((b) in the same figure). For example, the CVD oxide film 16 is
It grows to about 000A ((C) in the same figure).
異方性エツチングにてエッチバックする（同図（ｄ））
。Etch back using anisotropic etching ((d) in the same figure)
.
全面に例えばレジスト１７を塗布する（同図（ｅ））。For example, a resist 17 is applied to the entire surface (FIG. 2(e)).
異方性エツチングにてレジスト１７をエツチングする（
同図（ｆ））。不純物の導入全行い、ウェットエツチン
グにより酸化膜１６から酸化膜１５ヘエッチングを行う
（同図（ｇＪ ）。レジスト１７を除去する（同図（ｈ
））。ポリシリコン１９を全面に成長する（同図（ｉ）
）。異方性エツチングにてエッチパツクする（同図（ｊ
））。熱酸化して絶縁膜２０をポリシリコン１９上に作
る（同図（ｋ））。この実施例ではポリシリコン１４の
上に第１図の実施例のように絶縁膜４がないのでポリシ
リコン１４への不純物の導入が第２図（ａｌや（ｇｌの
工程において可能であるという自由度がある。Etch the resist 17 by anisotropic etching (
Figure (f)). After all impurities are introduced, the oxide film 16 is etched from the oxide film 15 by wet etching ((gJ) in the same figure).The resist 17 is removed ((h) in the same figure).
)). Polysilicon 19 is grown over the entire surface ((i) in the same figure).
). Etch-pack using anisotropic etching (see figure (j)
)). An insulating film 20 is formed on the polysilicon 19 by thermal oxidation (FIG. 4(k)). In this embodiment, there is no insulating film 4 on the polysilicon 14 as in the embodiment shown in FIG. There is a degree.
以上説明したように本発明は、ヒドラジンによる選択エ
ツチング全行なう必要がないので、半導体装置全製造す
る過程において不安定なエツチング工程全省略でき、比
較的結晶欠陥密度の高い〈１１１〉基板を使用する必要
がなく歩留り全同上させる効果がある。As explained above, in the present invention, since it is not necessary to perform selective etching with hydrazine, the unstable etching process can be omitted in the entire process of manufacturing semiconductor devices, and a <111> substrate with a relatively high density of crystal defects can be used. This is not necessary and has the effect of increasing the yield.
第１図（ａ）〜（ｋｌは本発明の一実施例による製造工
程を示す断面図、第２図（ａＪ〜（ｋｌは本発明の他の
実施例による製造工程を示す断面図、第３図（ａｌ〜（
ｅｌは従来の製造工程を示す断面図である。
１・・・半導体基板、２・・・酸化膜、３・・・ポリシ
リコン、４・・・酸化膜、５・・・酸化膜、６・・・Ｃ
ＶＤ酸化膜、７・・・側壁ＣＶＤ酸化膜、８・・・レジ
スト、９・・・コンタクト開孔部、１０・・・ポリシリ
コン、１１・・・酸化膜、１２・・・半導体基板、１３
・・・酸化膜、１４・・・ポリシリコン、１５・・・酸
化膜、１６・・・ＣＶＤ酸化膜、１７・・・レジスト、
１８・−・コンタクト開孔部、１９・・−ポリシリコン
、２０・・・酸化膜、２１・・・基板、２２・・・酸化
膜、２３・・・ポリシリコン、２４・・・窒化膜、２５
・・・ポリシリコン、２６・・・酸化展代理人 弁理士
内 原 晋
−へ（イ）寸の３−
＼ｊ−（Ｙ’） （’Ｊ
寸 Ｍ（Ｎ 寸 η Ｎ＝ Ｎ
’ ｃＶ−Ｊ寸端ト ■）
牛 Ｃ
（ｂ へく
−一〇ヘ ハ へ
烟 惨 ０Figures 1(a) to (kl are cross-sectional views showing the manufacturing process according to one embodiment of the present invention, Figures 2 (aJ to (kl) are cross-sectional views showing the manufacturing process according to another embodiment of the present invention, Figure (al~(
el is a cross-sectional view showing a conventional manufacturing process. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Oxide film, 3... Polysilicon, 4... Oxide film, 5... Oxide film, 6... C
VD oxide film, 7... Sidewall CVD oxide film, 8... Resist, 9... Contact opening portion, 10... Polysilicon, 11... Oxide film, 12... Semiconductor substrate, 13
... Oxide film, 14... Polysilicon, 15... Oxide film, 16... CVD oxide film, 17... Resist,
18... Contact opening portion, 19... - Polysilicon, 20... Oxide film, 21... Substrate, 22... Oxide film, 23... Polysilicon, 24... Nitride film, 25
...Polysilicon, 26... Oxidation agent Susumu Uchihara, patent attorney
' cV-J dimension ■) Cow C (b heku
-10 He ha He smoke misery 0
Claims (1)
と、前記半導体基板を酸化する工程と、前記半導体基板
上の全面に酸化膜を形成し該酸化膜を異方性エッチング
により前記導電膜の側壁に残るように形成する工程と、
前記半導体基板上の全面に酸化膜の除去に耐えられる膜
を形成し該膜を異方性エッチングにより前記側壁の酸化
膜が除去できる厚さとなるように形成する工程と、前記
側壁の酸化膜を除去し、かつ前記側壁の酸化膜の下部酸
化膜を除去する工程と、前記酸化膜の除去に耐えられる
前記膜を除去する工程とを有することを特徴とする半導
体装置の製造方法。A process of forming a conductive film that will become an electrode in the future on a semiconductor substrate, a process of oxidizing the semiconductor substrate, and forming an oxide film on the entire surface of the semiconductor substrate and anisotropically etching the oxide film to remove the conductive film. a step of forming it so that it remains on the side wall;
forming a film that can withstand the removal of the oxide film on the entire surface of the semiconductor substrate and forming the film to a thickness that allows the oxide film on the side walls to be removed by anisotropic etching; and removing the oxide film on the side walls. and removing a lower oxide film of the oxide film on the sidewall; and removing a portion of the film that can withstand removal of the oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31986187A JPH01160038A (en) | 1987-12-16 | 1987-12-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31986187A JPH01160038A (en) | 1987-12-16 | 1987-12-16 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01160038A true JPH01160038A (en) | 1989-06-22 |
| JPH0581182B2 JPH0581182B2 (en) | 1993-11-11 |
Family
ID=18115051
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31986187A Granted JPH01160038A (en) | 1987-12-16 | 1987-12-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01160038A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6596632B2 (en) | 1995-02-17 | 2003-07-22 | Micron Technology, Inc. | Method for forming an integrated circuit interconnect using a dual poly process |
-
1987
- 1987-12-16 JP JP31986187A patent/JPH01160038A/en active Granted
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6596632B2 (en) | 1995-02-17 | 2003-07-22 | Micron Technology, Inc. | Method for forming an integrated circuit interconnect using a dual poly process |
| US6740573B2 (en) | 1995-02-17 | 2004-05-25 | Micron Technology, Inc. | Method for forming an integrated circuit interconnect using a dual poly process |
| US7160801B2 (en) | 1995-02-17 | 2007-01-09 | Micron Technology, Inc. | Integrated circuit using a dual poly process |
| US7332811B2 (en) | 1995-02-17 | 2008-02-19 | Micron Technology, Inc. | Integrated circuit interconnect |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0581182B2 (en) | 1993-11-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH02239630A (en) | Manufacture of semiconductor device | |
| JP3346348B2 (en) | Method for manufacturing semiconductor device | |
| JPS60194570A (en) | Manufacture of semiconductor device | |
| US5254495A (en) | Salicide recessed local oxidation of silicon | |
| JPH01160038A (en) | Manufacture of semiconductor device | |
| JPS5856436A (en) | Manufacture of semiconductor device | |
| JPH0629554A (en) | Manufacture of semiconductor device | |
| JPH05326497A (en) | Manufacture of semiconductor device | |
| JPH03109739A (en) | Manufacture of thin-film semiconductor device | |
| JP2583243B2 (en) | Method for manufacturing MOS transistor | |
| JP2705933B2 (en) | Semiconductor integrated circuit device and method of manufacturing the same | |
| KR100296125B1 (en) | Gate electrode formation method of semiconductor device | |
| KR100226483B1 (en) | Method of forming a device isolation film of semiconductor device | |
| JPH09129876A (en) | Manufacture of semiconductor device | |
| JP2812298B2 (en) | Manufacturing method of bipolar transistor | |
| JPS61220372A (en) | Manufacture of semiconductor device | |
| JP2551028B2 (en) | Method for manufacturing semiconductor device | |
| JPH08236475A (en) | Formation of contact window | |
| JPS6279625A (en) | Manufacture of semiconductor device | |
| KR19990062507A (en) | Method of forming isolation film for semiconductor device | |
| JPS62291941A (en) | Method for isolating elements in semiconductor device | |
| JPH1126756A (en) | Manufacture of semiconductor device | |
| JPH11289082A (en) | Semiconductor device and its manufacture | |
| JPH02304931A (en) | Semiconductor device and manufacture thereof | |
| JPS6159870A (en) | Manufacture of semiconductor device |